EE476 VLSI Digital Circuits Summer 2011 Lecture 02: IC Manufacturing

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.]

CSE477 L05 IC Manufacturing.1

Irwin&Vijay, PSU, 2002

Review: CMOS Inverter

VDD

Full rail-to-rail swing high noise margins Low output impedance High input impedance No direct path steady-state between power and ground no static power dissipation Propagation delay is a function of load capacitance and on resistance of transistors
Irwin&Vijay, PSU, 2002

Vin CL

Vout

CSE477 L05 IC Manufacturing.2

Growing the Silicon Ingot

Base material is a singlecrystalline, lightly doped wafer between 4 and 12 inches and a thickness of, at most, 1 mm obtained from cutting a singlecrystal ingot into thin slices. Starting wafer of p- type around 2 x 10**21 impurities/m**3. Lightly doped

From Smithsonian, 2000

CSE477 L05 IC Manufacturing.3 Irwin&Vijay, PSU, 2002

CSE477 L05 IC Manufacturing.4

Irwin&Vijay, PSU, 2002

The CMOS process requires that both n-channel (NMOS) and p-channel (PMOS) transistors be built in the same silicon material

CSE477 L05 IC Manufacturing.5

Irwin&Vijay, PSU, 2002

CSE477 L05 IC Manufacturing.6

Irwin&Vijay, PSU, 2002

CMOS Process at a Glance

One full photolithography sequence per layer (mask) Built (roughly) from the bottom up 5 metal 2 4 metal 1 3 polysilicon 2 source and drain diffusions 1 tubs (aka wells, active areas)
The processing step can be any of a wide range of tasks including oxidation, etching, metal and polysilicon deposition, and ion implantation. The technique to accomplish this selective masking, called photolithography,

Define active areas Etch and fill trenches

Implant well regions

Deposit and pattern polysilicon layer

Implant source and drain regions and substrate contacts

Create contact and via windows Deposit and pattern metal layers

CSE477 L05 IC Manufacturing.7

Irwin&Vijay, PSU, 2002

Photolithographic Process
optical mask

oxidation

stepper exposure photoresist removal (ashing) photoresist coating

photoresist development process step

spin, rinse, dry

CSE477 L05 IC Manufacturing.8

acid etch

Irwin&Vijay, PSU, 2002

Patterning - Photolithography
1. Oxidation 2. Photoresist (PR) coating 3. Stepper exposure 4. Photoresist development and bake 5. Acid etching
Unexposed (negative PR) Exposed (positive PR)
SiO2 PR UV light mask

6. Spin, rinse, and dry 7. Processing step

Ion implantation Plasma etching Metal deposition

8. Photoresist removal (ashing)

CSE477 L05 IC Manufacturing.9 Irwin&Vijay, PSU, 2002

Example of Patterning of SiO2

Chemical or plasma etch Hardened resist SiO 2 Si-substrate Si-substrate

Silicon base material

Photoresist SiO2 Si-substrate

4. After development and etching of resist, chemical or plasma etch of SiO2

Hardened resist SiO2 Si-substrate

1&2. After oxidation and deposition of negative photoresist

UV-light Patterned optical mask Exposed resist Si-substrate

5. After etching

SiO2 Si-substrate

3. Stepper exposure
CSE477 L05 IC Manufacturing.10

8. Final result after removal of resist

Irwin&Vijay, PSU, 2002

Diffusion and Ion Implantation

1. Area to be doped is exposed (photolithography) 2. Diffusion or Ion implantation
Needed for well, source and drain regions, doping of polysilicon, adjustment of thresholds Diffusion wafer placed in quartz tube embedded in a furnace (900 to 1100 C). Gas containing dopant is introduced in the tub. Dopands diffused into the exposed surface both vertically and horizontally. Final dopant concentration is highest at surface and decreases in a gaussian profile deeper in the material Ion implantation Dopants are introduced as ions into the material by sweeping a beam of purified ions over the surface - acceleration determines how deep ions will penetrate and the beam current and exposure time determine dosage. Independent control of depth and dosage ion implantation has largely displaced diffusion. However, has a side effect of causing lattice damage to substrate, so usually follow with an annealing step (wafer heated to 1000C for 15 to 30 minutes and allowed to cool slowly). Heating vibrates atoms and allows the bonds to reform.
CSE477 L05 IC Manufacturing.11 Irwin&Vijay, PSU, 2002

Deposition and Etching

1. Pattern masking (photolithography)

2. Deposit material over entire wafer

CVD (Si3N4) chemical deposition (polysilicon) sputtering (Al)

3. Etch away unwanted material

wet etching dry (plasma) etching Needed for insulating SiO2, silicon nitride (sacrificial buffer), polysilicon, metal interconnect
CSE477 L05 IC Manufacturing.12 Irwin&Vijay, PSU, 2002

Planarization: Polishing the Wafers

Essential to keep the surface of the wafer approximately flat between processing steps.
uses a slurry compound a liquid carrier with a suspended abrasive component such as aluminum oxide or silica to microscopical plane a device layer and to reduce step heights.
From Smithsonian, 2000
CSE477 L05 IC Manufacturing.13 Irwin&Vijay, PSU, 2002

Self-Aligned Gates
1. Create thin oxide in the active regions, thick elsewhere 2. Deposit polysilicon 3. Etch thin oxide from active region (poly acts as a mask for the diffusion) 4. Implant dopant defining the precise location of the channel region and the locations of the source and drain regions
CSE477 L05 IC Manufacturing.14 Irwin&Vijay, PSU, 2002

Simplified CMOS Inverter Process

cut line

p well

CSE477 L05 IC Manufacturing.15

n type substrate - p well/tub

Irwin&Vijay, PSU, 2002

P-Well Mask

After p-well use implants to adjust VTn

CSE477 L05 IC Manufacturing.16 Irwin&Vijay, PSU, 2002

Active Mask

Grown thick oxide. Then use active mask to create thin oxide layers over the active areas where we are going to place the transistors (source, gate, and drain areas)
CSE477 L05 IC Manufacturing.17 Irwin&Vijay, PSU, 2002

Poly Mask

First used chemical deposition to deposit polysilicon on wafer. 0.25 micron technology -> 6.5 to 5.5 microns thick
CSE477 L05 IC Manufacturing.18 Irwin&Vijay, PSU, 2002

P+ Select Mask

Followed by diffusion (ion implant) to build pfets source and drain areas
CSE477 L05 IC Manufacturing.19 Irwin&Vijay, PSU, 2002

N+ Select Mask

Followed by diffusion (ion implant) to build nfets source and drain areas
CSE477 L05 IC Manufacturing.20 Irwin&Vijay, PSU, 2002

Contact Mask

After deposition of SiO2 insulator, then contact holes are etched (in this case to make contacts to source and drain regions)
CSE477 L05 IC Manufacturing.21 Irwin&Vijay, PSU, 2002

Metal Mask

CSE477 L05 IC Manufacturing.22

Irwin&Vijay, PSU, 2002

A Modern CMOS Process

Dual-Well Trench-Isolated CMOS
gate oxide Al (Cu) TiSi2 SiO2 tungsten field oxide

p well p-epi n+ p-

n well p+

SiO2

dual-well approach uses both n- and p- wells grown on top of a epitaxial layer(using trench isolation areas of SiO2)
CSE477 L05 IC Manufacturing.23 Irwin&Vijay, PSU, 2002

Modern CMOS Process Walk-Through

p-epi + p

Base material: p+ substrate with p-epi layer

Si N 34 p-epi + p SiO 2

After deposition of gate-oxide and sacrifical nitride (acts as a buffer layer)

p+

After plasma etch of insulating trenches using the inverse of the active area mask

CSE477 L05 IC Manufacturing.24

Irwin&Vijay, PSU, 2002

CMOS Process Walk-Through, cont

SiO After trench filling, CMP 2

planarization, and removal of sacrificial nitride

After n-well and VTp adjust implants

After p-well and VTn adjust implants

CSE477 L05 IC Manufacturing.25

Irwin&Vijay, PSU, 2002

CMOS Process Walk-Through, cont

poly(silicon)

After polysilicon deposition and etch

n +

+ p

After n+ source/dram and p+ source/drain implants. These steps also dope the polysilicon.

SiO 2

After deposition of SiO2 insulator and contact hole etch

CSE477 L05 IC Manufacturing.26

Irwin&Vijay, PSU, 2002

CMOS Process Walk-Through, cont

Al

After deposition and patterning of first Al layer.

Al SiO 2

After deposition of SiO2 insulator, etching of vias, deposition and patterning of second layer of Al.

CSE477 L05 IC Manufacturing.27

Irwin&Vijay, PSU, 2002

Layout Editor: max Design Frame

CSE477 L05 IC Manufacturing.28

Irwin&Vijay, PSU, 2002

max Layer Representation

Metals (five) and vias/contacts between the interconnect levels

Note that m5 connects only to m4, m4 only to m3, etc., and m1 only to poly, ndif, and pdif Some technologies support stacked vias

Active active areas on/in substrate (poly gates, transistor channels (nfet, pfet), source and drain diffusions (ndif, pdif), and well contacts (nwc, pwc)) Wells (nw) and other select areas (pplus, nplus, prb)
Irwin&Vijay, PSU, 2002

CSE477 L05 IC Manufacturing.29

Whats that?
Out metal1 metal2 In metal1-poly via polysilicon VDD

pfet pdif metal1-diff via PMOS (4/.24 = 16/1) NMOS (2/.24 = 8/1) ndif nfet GND metal2-metal1 via

CSE477 L05 IC Manufacturing.30

Irwin&Vijay, PSU, 2002

Simplified Layouts in max

Online design rule checking (DRC) Automatic fet generation (just overlap poly and diffusion and it creates a transistor) Simplified via/contact generation

v12, v23, v34, v45 ct, nwc, pwc

0.44 x 0.44 m1 0.3 x 0.3 ct 0.44 x 0.44 poly

CSE477 L05 IC Manufacturing.31

Irwin&Vijay, PSU, 2002

Design Rule Checker

poly_not_fet to all_diff minimum spacing = 0.14 um

CSE477 L05 IC Manufacturing.32

Irwin&Vijay, PSU, 2002

Design Rules

Interface between the circuit designer and process engineer Guidelines for constructing process masks Unit dimension: minimum line width

scalable design rules: lambda parameter absolute dimensions: micron rules

Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur A complete set includes

set of layers intra-layer: relations between objects in the same layer inter-layer: relations between objects on different layers
Irwin&Vijay, PSU, 2002

CSE477 L05 IC Manufacturing.33

Why Have Design Rules?

To be able to tolerate some level of fabrication errors such as

1. Mask misalignment

2. Dust

3. Process parameters (e.g., lateral diffusion)

4. Rough surfaces
CSE477 L05 IC Manufacturing.34 Irwin&Vijay, PSU, 2002

Intra-Layer Design Rule Origins

Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab

minimum line width is set by the resolution of the patterning process (photolithography)

Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab

0.3 micron 0.15 0.15 0.3 micron

CSE477 L05 IC Manufacturing.35

Irwin&Vijay, PSU, 2002

Intra-Layer Design Rules

Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 2
Metal2 3

Different Potential 9 Polysilicon 2 Metal1 3

4

Well

CSE477 L05 IC Manufacturing.36

Irwin&Vijay, PSU, 2002

Inter-Layer Design Rule Origins

1.

Transistor rules transistor formed by overlap of active and poly layers

Transistors
Catastrophic error

Unrelated Poly & Diffusion

Thinner diffusion, but still working

CSE477 L05 IC Manufacturing.37

Irwin&Vijay, PSU, 2002

Transistor Layout

Transistor

CSE477 L05 IC Manufacturing.38

Irwin&Vijay, PSU, 2002

Select Layer
2 3 2 1 3 3 Select

Substrate

Well

CSE477 L05 IC Manufacturing.39

Irwin&Vijay, PSU, 2002

Inter-Layer Design Rule Origins, Cont

2.

Contact and via rules

M1 contact to p-diffusion M1 contact to n-diffusion M1 contact to poly Mx contact to My

Contact Mask Via Masks mask misaligned

both materials

0.3

Contact: 0.44 x 0.44

0.14

CSE477 L05 IC Manufacturing.40

Irwin&Vijay, PSU, 2002

Vias and Contacts

2 Via 1 1 5 Metal to 1 Active Contact Metal to Poly Contact 3 2 4

2 2

CSE477 L05 IC Manufacturing.41

Irwin&Vijay, PSU, 2002

Next Lecture and Reminders

Next lecture

Static complementary CMOS gate design

- Reading assignment Rabaey, et al, 6.1-6.2.1

Reminders

Project Title due September 12th (next class!) HW2 due September 24th Evening midterm exam scheduled
- Wednesday, October 10th from 8:15 to 10:15pm in 260 Willard - Only one midterm conflict filed for so far

CSE477 L05 IC Manufacturing.42

Irwin&Vijay, PSU, 2002