AMERICAN COLLEGE OF
TECHNOLOGY
CONTROL UNIT OPERATION
Group Members
1. Kidus Tafese – RDCS - 154 - 21A
2. Moti Abebe – RDCS - 164 – 21A
3. Naol Getnet – RDCS - 168 – 21A
4. Gulet Mohamed _RDCS – 148-21A
5. Michael mesfin _ RDCS – 160-21A
Computer Organization and Architecture
Section B - CS Dept
2015/2022
1
Table of Contents
List of figures I
Abstract II
Introduction III
Micro Operation 1
The Indirect Cycle 1
The Interrupt Cycle 1
The Execute Cycle 2
The Instruction Cycle 3
Control of the processor 4
Basic Elements of Processor 5
Functions of Control Unit (CU) 5
Control Signal 6
Internal Processor Organization 7
The Intel 8085 7
Control Unit Logic 8
Summary 10
References 11
I
List of Figures
Fig.1 - Indirect cycle
Fig.2 - Interrupt cycle
Fig.3 - Execute cycle
Fig.4 - Execute cycle incremented by 1
Fig.5 - Instruction cycle
Fig.6 - Block diagram of the Control unit
Fig.7 - Internal processor organization
Fig.8 - CPU with internal bus
Fig.9 - Intel 8085 CPU Block
Fig.10 - Intel 8085 Pin configuration
I
Abstract
The main objective of this paper is to explore and comprehend the key components of the
Control Unit Operation and how they work in alliance to carry out operations performed by the
computer. We go through the different cycles that each instruction goes through which involves
the processor registers.
While also going through the other functional parts of the Control Unit, this will give a more in-
depth look at what goes behind each instruction that the computer receives and process it.
A more in-depth look was taken in following the instructions and how it moves through the
cycles and reach its path.
I
Introduction
Control Unit is the part of the computer’s central processing unit (CPU), which directs the
operation of the processor. It was included as part of the Von Neumann Architecture by John von
Neumann. It is the responsibility of the Control Unit to tell the computer’s memory,
arithmetic/logic unit and input and output devices how to respond to the instructions that have
been sent to the processor. It fetches internal instructions of the programs from the main memory
to the processor instruction register, and based on this register contents, the control unit generates
a control signal that supervises the execution of these instructions.
A control unit works by receiving input information to which it converts into control signals,
which are then sent to the central processor. The computer’s processor then tells the attached
hardware what operations to perform. The functions that a control unit performs are dependent
on the type of CPU because the architecture of CPU varies from manufacturer to manufacturer.
I
Micro operation
Micro-operations are the functional, or atomic, operations of a processor. These are low-level
instructions used in some designs to implement complex machine instructions. They generally
perform operations on data stored in one or more registers. They transfer data between registers
or between external buses of the CPU and perform arithmetic and logical operations on registers.
The operation of a computer consists of a sequence of instruction cycles, with one machine
instruction per cycle. Each instruction cycle is made up of several smaller units Fetch, Indirect,
Execute and Interrupt cycles. Each of these cycles involves a series of steps, each of which
involves the processor registers. These steps are referred to as micro-operations. the prefix micro
refers to the fact that each of the steps is very simple and accomplishes very little.
The Indirect Cycle
Once an instruction is fetched, the next step is to fetch source operands. Continuing our simple
example, let us assume a one-address instruction format, with direct and indirect addressing
allowed. If the instruction specifies an indirect address, then an indirect cycle must precede the
execute cycle.
Figure 1
The address field of the instruction is transferred to the MAR. This is then used to fetch the
address of the operand. Finally, the address field of the IR is updated from the MBR, so that it
now contains a direct rather than an indirect address.
The IR is now in the same state as if indirect addressing had not been used, and it is ready for the
execute cycle. We skip that cycle for a moment, to consider the interrupt cycle.
The Interrupt Cycle
At the completion of the execute cycle, a test is made to determine whether any enabled
interrupts have occurred. If so, the interrupt cycle occurs. The nature of this cycle varies greatly
from one machine to another.
Figure 2
1
In the first step, the contents of the PC are transferred to the MBR, so that they can be saved for
return from the interrupt. Then the MAR is loaded with the address at which the contents of the
PC are to be saved, and the PC is loaded with the address of the start of the interrupt-processing
routine. These two actions may each be a single micro-operation. However, because most
processors provide multiple types and/or levels of interrupts, it may take one or more additional
micro-operations to obtain the Save_Address and the Routine_Address before they can be
transferred to the MAR and PC, respectively. In any case, once this is done, the final step is to
store the MBR, which contains the old value of the PC, into memory. The processor is now ready
to begin the next instruction cycle.
The Execute Cycle
The fetch, indirect, and interrupt cycles are simple and predictable. Each involves a small, fixed
sequence of micro-operations and, in each case, the same micro-operations are repeated each
time around.
This is not true of the execute cycle. Because of the variety of opcodes, there are several
different sequences of micro-operations that can occur. Let us consider several hypothetical
examples.
First, consider an add instruction:
ADD R1, X
which adds the contents of the location X to register R1. The following sequence of micro-
operations might occur:
Figure 3
We begin with the IR containing the ADD instruction. In the first step, the address portion of the
IR is loaded into the MAR. Then the referenced memory location is read. Finally, the contents of
R1 and MBR are added by the ALU. Again, this is a simplified example. Additional micro-
operations may be required to extract the register reference from the IR and perhaps to stage the
ALU inputs or outputs in some intermediate registers.
Let us look at two more complex examples. A common instruction is increment and skip if zero:
ISZ X
The content of location X is incremented by 1. If the result is 0, the next instruction is skipped. A
possible sequence of micro-operations is
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Figure 4
The new feature introduced here is the conditional action. The PC is incremented If (MBR) = 0.
This test and action can be implemented as one micro-operation. Note also that this micro-
operation can be performed during the same time unit during which the updated value in MBR is
stored back to memory.
Finally, consider a subroutine call instruction. As an example, consider a branch and- save-
address instruction:
BSA X
The address of the instruction that follows the BSA instruction is saved in location X, and
execution continues at location X + 1. The saved address will later be used for return. This is a
straightforward technique for providing subroutine calls. The following micro-operations suffice:
Figure 5
The address in the PC at the start of the instruction is the address of the next instruction in
sequence. This is saved at the address designated in the IR. The latter address is also incremented
to provide the address of the instruction for the next instruction cycle.
The Instruction Cycle
We have seen that each phase of the instruction cycle can be decomposed into a sequence of
elementary micro-operations. In our example, there is one sequence each for the fetch, indirect,
and interrupt cycles, and, for the execute cycle, there is one sequence of micro-operations for
each opcode.
To complete the picture, we need to tie sequences of micro-operations together. We assume a
new 2-bit register called the instruction cycle code (ICC).The ICC designates the state of the
processor in terms of which portion of the cycle it is in:
00: Fetch
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01: Indirect
10: Execute
11: Interrupt
At the end of each of the four cycles, the ICC is set appropriately. The indirect cycle is always
followed by the execute cycle. The interrupt cycle is always followed by the fetch cycle. For
both the fetch and execute cycles, the next cycle depends on the state of the system.
Thus, the flowchart of Figure 3.3 defines the complete sequence of microoperations, depending
only on the instruction sequence and the interrupt pattern. Of course, this is a simplified example.
The flowchart for an actual processor would be more complex. In any case, we have reached the
point in our discussion in which the operation of the processor is defined as the performance of a
sequence of microoperations. We can now consider how the control unit causes this sequence to
occur.
Figure 6
Control of the processor
Functional Requirements of the Control Unit
The behavior or functioning of the CPU was decomposed into elementary operations called
micro-operations.
Defines the functional requirements of the Control Unit (those functions that the Control Unit
must perform)
Basis for the design and implementation of the control unit
A three-step process that leads to a characterization of the CU:
Define the basic elements of the processor
Describe micro-operations that the processor performs
Determine the functions that the CU must perform to cause a micro-opto to be performed
Basic Elements of Processor
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Execution of a program consists of operations involving the following processor elements
ALU
The essential functional unit of the CPU
Registers
Store data internal to the CPU
e.g. status information to manage instruction sequencing (program data that ord); data
that go to or come from the ALU, memory and I/O modules
Internal data paths
Used to move data between registers, and between registers and ALU
External data paths
Link registers to memory and I/O modules (system bus)
Control Unit
Causes operation to happen within the CPU
Types of Micro-operation Categories
Operations involving processor elements consist of a sequence of micro-operations
Categories of micro-operations
Transfer data between registers
Transfer data from the register to an external interface
e.g. system bus
Transfer data from an external interface to a register
Perform arithmetic or logical operations, using registers for input and output.
Functions of Control Unit (CU)
The control unit performs two basic tasks
Sequencing
Based on the program being executed, the CPU causes the proper sequencing of micro-
operations
Execution
The Control Unit causes each micro-operation to be performed
This is done by using control Signals
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Control signal
Control signals are the output of the learning and processing block, which are sent to different
output interfaces to produce the desired output in the real physical world.
Clock: This is how the control unit “keeps time.” The control unit causes one micro-operation (or
a set of simultaneous micro-operations) to be performed for each clock pulse. This is sometimes
referred to as the processor cycle time or the clock cycle time.
Instruction register: The opcode and addressing mode of the current instruction is used to
determine which micro-operations to perform during the execution time.
Flags: These are needed by the control unit to determine the status of the processor and the
outcome of previous ALU operations. For example, for the increment- and- skip- if- zero (ISZ)
instruction, the control unit will increment the PC if the zero flags are set.
Control signals from control bus: The control bus portion of the system bus provides signals to
the control unit
Figure 7
Control signals within the processor: These are two types: those that cause data to be moved
from one register to another, and those that activate specific ALU functions.
Control signals to control bus: These are also of two types: control signals to memory, and
control signals to the I/O modules. Three types of control signals are used: those that activate an
ALU function; those that activate a data path; and those that are signals on the external system
bus or other external interfaces. All these signals are ultimately applied directly as binary inputs
to individual logic gates.
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Internal Processor Organization
There are three basic components of the CPU: register bank, ALU, and Control Unit. There are
several data movements between these units and for that, an internal CPU bus is used. An
internal CPU bus is needed to transfer data between the various registers and the ALU.
t1: MAR - (IR (address))
t2: MBR - Memory
t3: Y - (MBR)
t4: Z - (AC) + (Y)
t5: AC - (Z)
Other organizations are possible, but, in general, some sort of internal bus or set of internal buses
is used. The use of common data paths simplifies the interconnection layout and the control of
the processor. Another practical reason for the use of an internal bus is to save space.
Figure 8
The intel 8085
is an 8-bit microprocessor produced by Intel and introduced in March 1976. It is software-binary
compatible with the more-famous Intel 8080 with only two minor instructions added to support its
added interrupt and serial input/output features.it requires less support circuitry.
Incrementor/ Decrementer address latch: Logic that can add 1 to or subtract 1 from the contents
of the stack pointer or program counter. This saves time by avoiding the use of the ALU for this
purpose.
Interrupt control: This module handles multiple levels of interrupt signals.
Serial I/O control: This module interfaces to devices that communicate 1 bit at a time.
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Figure 9
Figure 10
Intel 8085 CPU Block Diagram Intel 8085 Pin Configuration
hardwired implementation
Control Unit is the part of the computer’s central processing unit (CPU), which directs the
operation of the processor. It was included as part of the Von Neumann Architecture by John von
Neumann. It is the responsibility of the Control Unit to tell the computer’s memory,
arithmetic/logic unit, and input and output devices how to respond to the instructions that have
been sent to the processor.
The clock portion of the control unit issues a repetitive sequence of pulses. This is useful for
measuring the duration of micro-operations. Essentially, the period of the clock pulses must be
long enough to allow the propagation of signals along data paths and through processor circuitry.
Control Unit Logic
A control unit, or CU, is circuitry within a computer's processor that directs operations. It
instructs the memory, logic unit, and both output and input devices of the computer on how to
respond to the program's instructions. CPUs and GPUs are examples of devices that use control
units.
what must be done is, for each control signal, to derive a Boolean
expression of that signal as a function of the inputs. The micro-operation sequences and control
signals needed to control three of the four phases of the instruction cycle. Let us consider a single
control signal, C5. This signal causes data to be read from the external data bus into the MBR.
Let us define two new control signals, P and Q, that have the following interpretation:
PQ = 00 Fetch Cycle
PQ = 01 Indirect Cycle
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PQ = 10 Execute Cycle
PQ = 11 Interrupt Cycle
Then the following Boolean expression defines C5:
C5 = P•Q•T2 + P•Q•T2
That is, the control signal C5 will be asserted during the second time unit of both the fetch and
indirect cycles.
This expression is not complete. C5 is also needed during the execute cycle. For our simple
example, let us assume that there are only three instructions that read from memory: LDA, ADD,
and AND. Now we can define C5 as
C5 = P•Q•T2 + P•Q•T2 + P•Q•(LDA + ADD + AND)•T2
This same process could be repeated for every control signal generated by the processor. The
result would be a set of Boolean equations that define the behavior of the control unit and hence
the processor.
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Summary
Micro-operations are the functional, or atomic, operations of a processor.
Memory address register (MAR): Is connected to the address lines of the system bus.
Memory buffer register (MBR): Is connected to the data lines of the system bus.
Program counter (PC): Holds the address of the next instruction to be fetched.
Instruction registers (IR): Holds the last instruction fetched.
MICRO-OPERATIONS
The Fetch Cycle
The Indirect Cycle
The Interrupt Cycle
The Execute Cycle
The Instruction Cycle
the basic functional elements of the processor are:
ALU
Registers
Internal data paths
External data paths
Control unit
The control unit performs two basic tasks sequencing and execution
Control signals
Clock
Instruction register.
Flags.
Control signals from the control bus.
Control signals within the processor.
Control signals to control bus.
Internal organization
The intel 8085 - Incrementor/decrementer address latch, Interrupt control, Serial I/O control
Hardwired implementation
Control unit inputs and control unit logics.
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References
Introduction of Control Unit and its Design: https://www.geeksforgeeks.org/introduction-of-
control-unit-and-its-design
What are the three types of control signals?: https://studybuff.com/what-are-the-three-types-of-
control-signals/
Microprocessor - 8085 Architecture :
https://www.tutorialspoint.com/microprocessor/microprocessor_8085_architecture.htm
https://www.bing.com/images/search?q=+
+A+Decoder+with+4+Inputs+and+16+Outputs&qs=n&form=QBIDMH&sp=-
1&pq=a+decoder+with+4+inputs+and+16+outputs&sc=0-
38&cvid=859BB91E81314180AC79918F75A6C0A2&ghsh=0&ghacc=0&first=1&tsc=ImageH
overTitle
https://www.google.com/search?
q=A+Decoder+with+4+Inputs+and+16+Outputs&source=lnms&tbm=isch&sa=X&ved=2ahUK
Ewi4gvPm8sn7AhVGhP0HHRcwDF4Q_AUoAXoECAEQAw#imgrc=8IluZXMprRdB0M&im
gdii=zJWffwYMvgfq4M
Control Unit Operation: https://cnx.org/contents/
[email protected]:mur-kqun@1/Module-6-
Control-Unit-Operation
Computer Organization | Micro-Operation: https://www.geeksforgeeks.org/computer-
organization-micro-operation/
Control unit: https://wachemo-elearning.net/courses/computer-organization-and-architecture-
itec2024/lessons/chapter-three-assembly-level-machine-organization/topic/3-2-control-unit/
Functional Requirements of the Control Unit:
https://www.coursehero.com/file/p3daumd/Functional-Requirements-of-the-Control-Unit-
Behavior-or-functioning-of-the-CPU/
Microprocessor – Classification:
https://www.tutorialspoint.com/microprocessor/microprocessor_classification.htm
Arithmetic Logic Unit: https://en.wikipedia.org/wiki/Arithmetic_logic_unit
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