TDA7706

Highly integrated tuner for AM/FM car-radio

Data brief  production data

Features
■ FM, AM and weather band reception
■ Fully integrated VCO for world tuning
■ High performance PLL for fast RDS system
■ Integrated AM-LNA and PIN diodes
■ Automatic self alignment for FM front-end pre-
selection filter and image rejection
'!0'03

■ Integrated IF filters with high selectivity,

dynamic range and adaptive bandwidth control LQFP64
■ Drift-free Digital-IF signal processing with high
performance
■ RDS demodulation with group and block
synchronization
■ High performance stereo decoder with noise- It contains mixers and IF amplifiers for AM, FM
blanker and WX, fully integrated VCO and PLL
■ Digital interface for HD Radio™ reception with synthesizer, IF- processing including adaptive
digital audio blending bandwidth control, stereo-decoder, RDS decoder,
and digital interfaces for external HD Radio™
■ Fully programmable DSP core
decoding on a single IC.
■ I2C bus-controlled
AM/FM IBOC or DRM base band filtering is
■ I2S input/output digital audio interfaces available in parallel to standard analog reception.
■ Single 5 V supply
The utilization of digital signal processing results
■ LQFP64 package in numerous advantages against today's tuners:
very low number of external components, very
Description small space occupation and easy application,
very high selectivity due to digital filters, high
The TDA7706 highly integrated tuner is a customization possibility through software control,
high/performance AM/FM tuner IC for car-radio automatic alignment and a powerful DSP for
applications, suitable for HD Radio™ reception. custom processing.

Table 1. Device summary

Order code Package Packing

TDA7706CB LQFP64 (10x10x1.4mm) Tray

September 2013 Doc ID 022898 Rev 3 1/16

This is information on a product in full production. For further information contact your local STMicroelectronics sales www.st.com 16
office.
Contents TDA7706

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 FM - mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 FM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 AM - LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 AM - AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 AM - Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 IF A/D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Audio D/A converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9.1 Tuner PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.11 DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.12 HD Radio connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Basic application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/16 Doc ID 022898 Rev 3

 1

1.1
TDA7706

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Block diagram and pin description
Block diagram and pin description TDA7706

1.2 Pin description

Figure 2. Pin connection (top view)

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Table 2. Pin description

Pin Pin name I/O Function Description Equivalent circuit

1 FMPINDRV Out FM PIN diode driver output

'!0'03

Integrated FM PINdiode
2 FMPINDdec In
decoupling
FM '!0'03

3 FMMIXdec - FM RF signal ground

4 FMMIXin2 In FM mixer input 2

5 FMMIXin1 In FM mixer input 1

'!0'03

6 GNDRF - - RF power ground -

4/16 Doc ID 022898 Rev 3

TDA7706 Block diagram and pin description

Table 2. Pin description (continued)

Pin Pin name I/O Function Description Equivalent circuit

7 TCAM - - AM AGC time constant

 
'!0'03

8 VCCRF In - RF 5V supply -

Master/Slave clock operation

9 CK_SEL In -
select

'!0'03

10 GNDVCO - VCO ground -

11 LFref - Loop filter reference -
12 LF1 - Loop filter output -
13 VCCVCO In VCO 5V supply -
VCO

14 TCAM2 - AM AGC 2nd order time constant

 
'!0'03

AM AGC internal PIN diode

15 PINDdec -
decoupling

AM pin diode '!0'03

16 PINDin - AM AGC internal PIN diode input

'!0'03

17 GNDLNA - AM LNA ground -

18 LNAin In AM LNA input

'!0'03

AM LNA

19 LNAdec - AM LNA decoupling

'!0'03

20 LNAout Out AM LNA output -

21 LNAin2 - AM LNA input 2nd stage -

Doc ID 022898 Rev 3 5/16

Block diagram and pin description TDA7706

Table 2. Pin description (continued)

Pin Pin name I/O Function Description Equivalent circuit

22 LNAout2 - AM LNA output 2nd stage

'!0'03

AM LNA

23 LNAdec2 - AM LNA decoupling 2nd stage

'!0'03

24 AMMIXin1 In AM mixer input 1

AM mixer
25 AMMIXin2 In inputs AM mixer input 2
'!0'03

Internal inter-IC communication

26 GNDSLINK - -
bus ground
27 Vdig In Front-end digital 5 V supply -
28 VCCreg1V2 In Internal 1.2 V regulator 5 V supply -
29 REG1V2 Out Internal 1.2 V regulator output

30 Vreg3v3 Out Supply, Internal 3.3 V regulator output

ground and
reset '!0'03

Reset (low active)

31 RSTN In
Pull-up 50 k to 3.3 V IO supply
'!0'03

RDS interrupt output

32 RDSint Out -
Pull-down 50 k to ground

I2C bus data

33 I2CSDA In/Out
Pull-up 50 k to 3.3 V IO supply

I2C interface
'!0'03

I2C bus clock

34 I2CSCL In
Pull-up 50 k to 3.3 V IO supply
'!0'03

35 VDD3V3 In - IO ring (3.3V) supply -

36 GND3V3 - - IO ring (3.3V) supply -

6/16 Doc ID 022898 Rev 3

TDA7706 Block diagram and pin description

Table 2. Pin description (continued)

Pin Pin name I/O Function Description Equivalent circuit

SAI clk
37 GPIO8 In/Out Pull-down 50 k to ground,
SINE_3V3_LIN pad
Audio SAI word-select
38 GPIO7 In/Out Pull-down 50 k to ground,
SINE_3V3_LIN pad
Audio SAI data-output
39 GPIO6 In/Out Pull-down 50 k to ground,
SINE_3V3_LIN pad
Audio SAI data-input
40 GPIO5 In/Out Pull-down 50 k to ground,
SINE_3V3_LIN pad
SAI Base-Band clock
HD Radio
41 GPIO4 In/Out Pull-down 50 k to ground,
connectivity/
SINE_3V3_LIN pad '!0'03

Audio output
I2S interface SAI Base-Band word-select
42 GPIO3 In/Out Pull-down 50 k to ground,
SINE_3V3_LIN pad
SAI Base-Band I data
43 GPIO2 Out Pull-down 50 k to ground,
SINE_3V3_LIN pad
SAI Base-Band Q data
44 GPIO1 Out Pull-down 50 k to ground,
SINE_3V3_LIN pad

HD blend
45 GPIO0 In
Pull-down 50 k to ground
'!0'03

46 GND1V2 - - DSP core ground -

47 VDD core 1V2 In - DSP core 1.2V supply -

Test Mode
48 Test In -
Pull-down 50 k to ground
'!0'03

49 VDDPLL1V2 In - Digital PLL 1.2 V supply -

Internal inter-IC communication
50 VDDIO1V2 In - -
1.2V supply
Front-end reference frequency and
51 VCC-REF In - -
regulator 5 V supply

Doc ID 022898 Rev 3 7/16

Block diagram and pin description TDA7706

Table 2. Pin description (continued)

Pin Pin name I/O Function Description Equivalent circuit

52 OSCin In Crystal oscilllator input -

Oscillator
53 OSCout Out Crsystal oscillator output

'!0'03

Front-end reference frequency and

54 GND-REF - - -
regulator ground

55 Vrefdec - - 3.3 V Bias generation decoupling

'!0'03

56 GND-ADC_DAC - IFADC and audio DAC ground -

57 DACoutL Out Audio output left

DAC
58 DACoutR Out Audio output right
'!0'03

59 VCC-ADC_DAC In IFADC and audio DAC 5V supply -

60 VCC-PLL In Tuning PLL 5V supply -
61 GND-PLL - Tuning PLL ground -

PLL
62 PLLtest Out PLL Test output

'!0'03

63 TCFM - - FM AGC time constant

'!0'03

64 TVDAC Out - Tuning voltage output -

8/16 Doc ID 022898 Rev 3

TDA7706 Function description

2 Function description

2.1 FM - mixers
The FM Image Rejection mixer has two single ended inputs, selectable through software.
They are designed for achieving best performance both in case of a passive tuned
preselection and for a passive fixed band-pass preselection without tuning for lower cost
applications.
The input frequency is down-converted to very low IF with high image rejection.
The tuned application is supported by an 8-bit tuning DAC. The alignment of the DAC is
performed automatically on-chip.

2.2 FM - AGC
The programmable RFAGC senses the mixer input to avoid overload.
When the RFAGC threshold is reached, the PIN diode output is activated in order to
attenuate the incoming RF signal
The PIN diode driver is able to drive external PIN diodes with up to 15 mA current.
The time constant of the FM AGC is defined by the combination of an external capacitor and
internal currents. There are two programmable attack and decay time constants.

2.3 AM - LNA
The integrated AM LNA feature is integrated with low-noise and high IIP2 and IIP3. The gain
of the LNA is controlled by the AGC. The maximum gain is set with an external resistor,
typically 26 dB with 470 ohm.

2.4 AM - AGC
The programmable AM RFAGC senses the mixer inputs and controls the internal PIN diodes
and LNA gains.
Firstly the LNA gain is reduced by about 10d B, and then the PIN diodes are activated to
further attenuate the signal.
The time constant of the 2nd order AM AGC LPF is defined by both external components
and programmable internal currents.

2.5 AM - Mixers
The image rejection mixer has two AM inputs selectable via software. It easily supports low-
cost applications for extended frequency bands like short-waves.
The input frequency is converted to low IF with high image rejection.

Doc ID 022898 Rev 3 9/16

Function description TDA7706

2.6 IF A/D converters

A high performance IQ-IFADC converts the IF signal to the digital domain for subsequent
digital signal processing.
Two fully differential, continuous-time Sigma-Delta () IF-ADCs are used for both the'I' path
and the 'Q' path. For each IFADC, two fully differential input nodes are fed with an input
signal having a bandwidth up to 325 kHz. This fully differential design provides good
suppression of even-order harmonics. For complex filtering, the input signals of the 'I' path
and the 'Q' path have a 90 degree phase shift. The IFADC sampling frequency is 36.48
MHz.

2.7 Audio D/A converters

A CD-quality (>100dB DR) stereo DAC provides the left/right audio signals after IF
processing and stereo-decoding by the DSP. In presence of an external HD Radio decoder
the DAC outputs the high quality audio resulting from the decoding of the HD Radio
transmissions.

2.8 VCO
The VCO is fully integrated without any external tuning component. It covers all the FM
frequency bands including EU, US, Japan, East-Europe, Weather-Band and the AM-bands
including LW, MW and SW. Its center frequency is approximately 2.7 GHz.

2.9 PLL

2.9.1 Tuner PLL

The very high-speed tuning PLL is able to settle within about 100 µs for fast RDS
applications. The frequency step can be as low as 5 kHz in FM and 500 Hz in AM.

2.10 Crystal oscillator

The device works with a 36.48 MHz fundamental tone crystal. The oscillator block diagram
is shown in Figure 3. On the PCB the crystal must be connected as close as possible to the
chip oscillator input and output pins of the chip. The internal load capacitance together with
pin and pad capacitance is optimized for fundamental tone crystal units at 36.48MHz. It is
not recommended to put any additional external load capacitors. By suitably configuring pin
#9 (CK_SEL), the device can be operated as either a clock master or a clock slave. If pin 9
is left open or tied to GND, the device is configured as clock master (typical operation
mode). In case the device is configured as clock slave, pin 9 needs to be connected to 5V.
Then the crystal oscillator is switched off and the device expects a crystal equivalent signal
on the OSCout/OSCin pins.

10/16 Doc ID 022898 Rev 3

TDA7706 Function description

Figure 3. Crystal oscillator block diagram

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2.11 DSP
The TDA7706 embeds two DSP cores for high computational power and achievable
customization. The first DSP and its hardware accelerators take care of all the tuner digital
signal processing. The main program is fixed in ROM. Control parameters are copied to
RAM and they are accessible and modifiable there, thus allowing a parametric performance
optimization. The first DSP core performs:
● digital down-conversion of IF
● bandwidth selection with variable controlled bandwidth
● FM and AM noise blanking
● FM/AM demodulation with soft-mute, high-cut, weak signal processing and quality
detection
● FM stereo decoding with stereo-blend
● RDS demodulation including error correction and block synchronization with generation
of an RDS interrupt for the main µP
● Autonomous control of RDS-AF tests
● Self-alignment of pre-selection tuning
The second DSP is totally free for custom processing implementation. The second
(customizable DSP) can interact with the main DSP by tapping the signal at the access
points as shown in the Figure 4 below.

Doc ID 022898 Rev 3 11/16

Function description TDA7706

Figure 4. Secondary DSP signal access points in main signal path

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2.12 HD Radio connectivity

The HIT2 complies with HD Radio interface specifications as per Ibiquity's "RX_SSS_1108
HD Radio power efficient RF-IF and peripheral processing (power RIPP) specification", thus
providing an external HD Radio decoder with I/Q base-band signals and receiving the
decoded digital audio from it, as shown in Figure 5.

Figure 5. HD Radio system architecture example

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Package information TDA7706

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 7. LQFP64 (10x10x1.4mm) mechanical data and package dimensions

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14/16 Doc ID 022898 Rev 3

TDA7706 Revision history

5 Revision history

Table 3. Document revision history

Date Revision Changes

07-Mar-2012 1 Initial release.

25-Jun-2012 2 Updated Table 1: Device summary on page 1.
16-Sept-2013 3 Updated Disclaimer

Doc ID 022898 Rev 3 15/16

 TDA7706

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16/16 Doc ID 022898 Rev 3