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Asynchronous Reset Sync Challenges

The document discusses challenges with asynchronous resets in synchronous circuits and provides solutions. Asynchronous resets can cause intermittent failures if not coordinated with the clock signal. While asynchronous resets have advantages like lower latency, they may cause metastability issues if not synchronized properly. The key is to synchronize the release of the asynchronous reset to the clock signal to avoid synchronization failures. Distribution of resets also needs to be carefully handled like clock trees to avoid skew problems. Reset synchronizers can be used to safely synchronize the asynchronous reset signal to the clock domain.

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Roshan Raju
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213 views2 pages

Asynchronous Reset Sync Challenges

The document discusses challenges with asynchronous resets in synchronous circuits and provides solutions. Asynchronous resets can cause intermittent failures if not coordinated with the clock signal. While asynchronous resets have advantages like lower latency, they may cause metastability issues if not synchronized properly. The key is to synchronize the release of the asynchronous reset to the clock signal to avoid synchronization failures. Distribution of resets also needs to be carefully handled like clock trees to avoid skew problems. Reset synchronizers can be used to safely synchronize the asynchronous reset signal to the clock domain.

Uploaded by

Roshan Raju
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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https://www.embedded.

com/asynchronous-reset-synchronization-and-distribution-
challenges-and-solutions/

Lack of coordination between asynchronous resets and synchronous logic clocks


=> intermittent failures on power up

Reset brings synchronous circuitry to known state after power up


Reset is mostly required for the control logic and may be eliminated from the
data path logic
reset can be asynchronous or synchronous

Coordinate async reset release with sync clock signal to eliminate synchronization
failures

Handle reset distribution like CTS


=> reset require similar area and routing resources

Synchronous reset
requires an active clock,
incurs certain clock-cycle related latency and
may impact the timing of the data paths

but, is deterministic and do not incur metastability

Asynchronous reset
does not require an active clock,
has a lower latency than a synchronous reset and
can exploit special flip-flop input pins that do not affect data path timing

may cause metastability in flip-flops


must be made directly accessible to enable DFT
may incur reliability problems in rad-hard applications (susceptible to
Single Event Transient phenomena)

Asynchronous reset drivers


external ports,
depending on power supply status (RC circuits, watchdog devices),
manual reset buttons and
external masters, such as microprocessors

Asynchronous reset is compulsory in cases like clock-gated/power-gated logics

For Asynchronous reset,


relative timing between clock and reset can be ignored during reset assertion
reset assertion affects flip-flop output Q within a deterministically
bounded time
ie., only propagation delay (TR-pd ) and regardless of clock signal CLK
but, reset release must be synchronized to the clock
setup and hold timing conditions must be satisfied for the RST port
relative to the clock port CLK
violation of the setup and hold conditions for the RST port (aka reset
recovery and removal timing) cause metastability

Clock and reset skew can arise due to


design variations - unequal wire length, unequal load, IR drop
process variations - buffer and wire

skew can result in reset triggering at different times - breaking


functionality

Reset synchronizers

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