Counters
Mr. Varun Sangwan
Assistant Professor
Electronics and Communication Engg.
DTU
Counters
• Counters are important digital electronic circuits.
• They are Sequential logic circuits because timing is obviously important
and they need a memory characteristic.
• Digital counters have the following important characteristics,
1. Maximum number of count
2. Up-Down Count
3. Asynchronous or Synchronous Operation
4. Free-Running or Self-Stopping
• counters are mainly used in counting applications, where they either
measure the time interval between two unknown time instants or measure
the frequency of a given signal
Ripple (Asynchronous) Counter
• Asynchronous counters are commonly referred to as ripple counter
because the effect of the input clock pulse is first “felt” by first flip-
flop (FF0).
• Cannot get to the second flip-flop (FF1) immediately because of the
propagation delay through FF0.
• So the effect of an input clock pulse “ripples” through the counter,
taking some time, due to propagation delays, to reach the last flip-
flop.
Only the first FF receive clock pulse from the source ( clock genarator),
others FFs receive clock pulse from either Q or Q’ of prior FF
Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter
N = number of FFs
As the number of FFs in the counter increases, the total propagation delay increases and fmax decreases
Four-bit binary ripple counter
Modulus of a Counter
• The modulus (MOD number) of a counter is the number of different logic states it goes
through before it comes back to the initial state to repeat the count sequence
• An N-bit counter that counts through all its natural states and does not skip any of the
states has a modulus of 2N
• In general, the arrangement of a minimum number of N flip-flops can be used to
construct any counter with a modulus given by the equation
MOD-7 counter
The counter thus always
counts from 0000 to 0110 and
resets back to 0000
The remaining nine states,
which include
0111,
1000,
1001,
1010,
1011,
1100,
1101,
1110 and 1111,
are skipped
3 Bit Up/Down Counter
Decoding a Counter
The decoding network therefore is going to be a logic circuit that takes its inputs from the outputs of the
different flip-flops constituting the counter and then makes use of those data to generate outputs equal to
the modulus or MOD-number of the counter
One typical application could be a need to initiate or trigger some action after the counter reaches a specific
state.
The decoding gates used to decode the states of a ripple counter produce glitches (or spikes) in the
decoded waveforms
These glitches basically result from the cumulative propagation delay as we move
from one flip-flop to the next in a ripple counter.
Use strobe signal to remove decoding error
Synchronous (or Parallel) Counters
The propagation delay becomes prohibitively large in a ripple counter (which is
asynchronous in nature) with a large count.
On the other hand, in a synchronous counter, all flip-flops in the counter are
clocked simultaneously in synchronism with the clock, and as a consequence all
flip-flops change state at the same time.
The propagation delay in this case is independent of the number of flip-flops used.
flip-flop FF0 toggles with every clock pulse,
FF1 toggles only when the output of FF0 is in the ‘1’ state,
FF2 toggles only with those clock pulses when the outputs of
FF0 and FF1 i.e. Q0, Q1 are both in the logic ‘1’ state
FF3 toggles only with those clock pulses when Q0 , Q1 and Q2 are
all in the logic ‘1’ state.
Contd.
Design a counter with the irregular binary count sequence shown in the state diagram. Use D flip flop.
➢ This Ring Counter can also be used for counting the number of pulses.
➢ No decoding circuitry is required.
➢ Since there is one pulse at the output for each of the N clock pulses, this circuit is referred to as a divide-by-
N counter
➢ No. of states in Ring counter = No. of flip-flop used
• In a Johnson counter, the complement of the output of the last flip-flop is connected back to the
D input of the first flip-flop (it can be implemented with other types of flip-flops as well).
• If the counter starts at 0, this feedback arrangement produces a characteristic sequence of states.
• In general, a Johnson counter will produce a modulus of 2n, where n is the number of stages in
the counter.
• In the Johnson counter, the unutilized states are greater than the states being utilized.
• Also called as :
• Twisted-Ring Counter
• Moebius Counter
It is a divide-by-2N counter.
Counters can be connected in cascade to achieve higher-modulus operation.
In essence, cascading means that the last-stage output of one counter drives the input of the next counter.
CTEN= counter enabled
TC=terminal count
• The terminal count (TC) output of counter 1 is connected to the count enable (CTEN) input of counter 2.
• Counter 2 is inhibited by the LOW on its CTEN input until counter 1 reaches its last state and its terminal count
output goes HIGH
• This HIGH now enables counter 2, so that when the first clock pulse after counter 1 reaches its terminal count
(CLK10), counter 2 goes from its initial state to its second state.
