Counters

Chapter 8
 Counters

• A counter is a sequential circuit that goes through a

predetermined sequence of states upon the
application of clock pulses.

• Counters may count the number of occurrences of a

certain event, generate timing intervals for the control
of tasks in a system, keep track of time elapsed
between specific events, et.al.

• An n-bit binary counter implemented with n flip-flops

can have 2n unique states, i.e. it can count from 0 to
2 n -1.
 Counters

▪ The number of flip-flops determines the count limit or

number of states.
(STATES = 2 # of flip flops)

▪ The number of states used is called the MODULUS.

▪ For example, a Modulus-12 counter would count from

0 (0000) to 11 (1011) and requires four flip-flops (16
states - 12 used).

▪ Output of the last flip-flop (MSB) divides the input

clock frequency by the MOD number of the counter,
hence a counter is also a frequency divider.
 Counters

• Counters are categorized as:

– Synchronous Counters (Parallel Counters):
All FFs receive the common clock pulse, and the
change of state is determined from the present
state.

– Asynchronous Counters (Ripple /Serial Counters):

The FF output transition serves as a source for
triggering other FFs. No common clock.
 Asynchronous Counters

• Only the first FF receive clock pulse from the source

( clock generator), others FFs receive clock pulse
from either Q or Q’ of prior FF.

• The output of each flip-flop is connected to the Clk

input of the next higher order flip-flop with the flip-flop
representing the least significant bit receiving the
incoming Clock pulses.

• A simple asynchronous counter can be built using

T –type flip-flops cascaded together.
 Asynchronous Counters

Design Basic Counters

▪ Same polarity for down counters:

Q → PET or Q → NET

▪ Opposite polarity for up counters:

Q → NET or Q → PET
 2-bit ripple binary counter
HIGH

J Q0 J Q1

CLK C C
Q0
K K

FF0 FF1

CLK 1 2 3 4

Q0

Q0 0 1 0 1 0

Q1 0 0 1 1 0
 3-bit ripple binary counter
HIGH

J Q0 J Q1 J Q2

CLK C C C
Q0 Q1
K K K

FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0
 Asynchronous Counters
▪ Propagation delays in an asynchronous (ripple-
clocked) binary counter.
▪ If the accumulated delay is greater than the clock
pulse, some counter states may be misrepresented!

CLK 1 2 3 4

Q0

Q1

Q2

tPHL (CLK to Q0) tPHL (CLK to Q0)

tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)
 Decoding A Counter

▪ Decoding a counter involves determining which state

in the sequence the counter is in.

▪ Active-HIGH decoding: output HIGH if the counter is

in the state concerned.
▪ Active-LOW decoding: output LOW if the counter is in
the state concerned.
Decoding A Counter
 n
Asyn. Counters with MOD no. < 2

▪ Decade counters (or BCD counters) are counters

with 10 states (modulus-10) in their sequence.
They are commonly used in daily life (e.g.: utility
meters, odometers, etc.).
▪ Design an asynchronous decade counter.
(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C

K K K K
CLR CLR CLR CLR
Asynchronous Decade/BCD counter (cont’d).

HIGH
D C B A
J Q J Q J Q J Q (A.C)'

CLK C C C C
K K K K
CLR CLR CLR CLR

1 2 3 4 5 6 7 8 9 10 11
Clock

D 0 1 0 1 0 1 0 1 0 1 0

C 0 0 1 1 0 0 1 1 0 0 0

B 0 0 0 0 1 1 1 1 0 0 0

A 0 0 0 0 0 0 0 0 1 1 0
NAND
output
 Asynchronous Down Counters
▪ So far we are dealing with up counters. Down
counters, on the other hand, count downward from a
maximum value to zero, and repeat.
▪ Example: A 3-bit binary (MOD-23) down counter.
1

Q0 Q1 Q2
J J J
Q Q Q
3-bit binary
CLK C C C
Q' Q' Q' up counter
K K K

J
Q0
J
Q1
J
Q2 3-bit binary
Q Q Q
CLK C C C
down counter
Q' Q' Q'
K K K
 Asynchronous 3-bit binary (MOD-8)
down counter.

1 000
001 111
Q0 Q1 Q2
J J J
Q Q Q
010 110
CLK C C C
Q' Q' Q'
K K K
011 101
100

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 1 1 0 0 1 1 0 0

Q2
0 1 1 1 1 0 0 0 0
Asynchronous 3 bit binary up-down
counter

Count-up=1,count-dn=0 : count up mode

Count-up=0,count-dn=1 : count down mode
 Synchronous Counters

• A synchronous counter differs from an asynchronous counter

in that the clock pulses are applied to all of the flip-flops.

• The common clock triggers all the flip-flops simultaneously,

rather than one at a time in succession as in a ripple counter.

• The advantage of synchronous counters is that it is possible to

build larger, and faster counters, without affecting
synchronization to other portions of a larger system.

• Synchronous counters require additional combinational logic to

control the transition of the individual flip-flops rather than
being driven directly by the Q or Q' outputs of other flip-flops.
 Synchronous Counters
▪ We can design these counters using the sequential
logic design process (covered in Chapter # 9).
▪ Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).
Present Next Flip-flop
00 01 state state inputs
A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
0 1 1 0 1 1
11 10
1 0 1 1 0 1
1 1 0 0 1 1
1

A0 A1
J Q J Q
C C
K
Q'
K
Q' TA1 = A0
TA0 = 1
CLK
Synchronous binary counter(Mod-8)
 Synchronous 4-bit up/dn counter

Count up

clock

Count dn

Count up mode: clk applied to count up and count dn held low

Count down mode: clk applied to count dn and count up held low
 Changing the Counter Modulus
• A Mod-3 Counter
A Mod-6 Counter
A Mod-5 Counter
A Decade Counter(Mod-5 X Mod-2)
A Decade Counter(Mod-2 X Mod-5)
Cascading BCD (Decade)counters

D from the counter will have a single negative

Transition as that counter progresses from 9 to 0
 Presettable Counters

• Basic building block that can be used to implement

a counter that has any modulus.
• Nearly all the presettable counters (TTL MSI) are
constructed using 4 FFs and referred to as 4-bit
counters.
• e.g.
– 54/74161,54/74163: Syn. Binary up counters
– 54/74191,54/74193: Syn. Binary up/dn counters
– 54/74160,54/74162: Syn. Decade (up) counters
– 54/74190,54/74192: Syn. Decade (up/dn) counters
 54/74163: Syn. Binary up counter

Pin 15 :units tens hundreds applications.

Pin 7&10 : both must be high for counter operation.
Pin1 :Synchronous reset.
Pin 9 :when low level applied inputs(DCBA) loaded
on the +ve edge
(to count from a predetermined count )
54/74163: Syn. Binary up counter
54/74193: Syn. Binary up/dn counter
 DIGITAL CLOCK

Decoding gate to
reset (00) after 11
• Synchronous Counter design with auto
correction
• Irregular counter design