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Direct Memory Access

Direct Memory Access (DMA) allows I/O devices to access main memory directly without intervention from the CPU. A DMA controller provides the address and control signals to transfer blocks of data between I/O devices and memory. The CPU initiates DMA transfers by informing the DMA controller of the starting address, number of words, and transfer direction. DMA controllers can operate in cycle stealing mode, accessing memory interwoven with the CPU, or in burst mode where it has exclusive access for longer periods.

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0% found this document useful (0 votes)
87 views16 pages

Direct Memory Access

Direct Memory Access (DMA) allows I/O devices to access main memory directly without intervention from the CPU. A DMA controller provides the address and control signals to transfer blocks of data between I/O devices and memory. The CPU initiates DMA transfers by informing the DMA controller of the starting address, number of words, and transfer direction. DMA controllers can operate in cycle stealing mode, accessing memory interwoven with the CPU, or in burst mode where it has exclusive access for longer periods.

Uploaded by

Herambh Dubey
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© © All Rights Reserved
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Direct Memory Access

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Direct Memory Access
●Direct Memory Access (DMA):
● A special control unit may be provided to transfera block of data directly
between an I/O device and the main memory, without continuous
intervention by the processor.

●Control unit which performs these transfers is a


part of the I/O device’s interface circuit. This
control unit is called as a DMA controller.
●DMA controller performs functions that would
be normally carried out by the processor:
● Foreach word, it provides the memory address and all the control signals.
● To transfera block of data, it increments the memory addresses and keeps
track of the numberof transfers.
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Direct Memory Access
● DMA controller can transfera block of data from an external
device to the processor, without any intervention from the
processor.
● However, the operation of the DMA controller must be under
the control of a program executed by the processor. That is, the
processor must initiate the DMA transfer.
● To initiate the DMA transfer, the processor informs the DMA
controller of:
● Starting address,
● Numberof words in the block.
● Direction of transfer (I/O device to the memory, or memory to
the I/O device).
● Once the DMA controller completes the DMA transfer, it informs
the processor by raising an interrupt signal.

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Direct Memory Access
•DMA controller connects a high-speed network to the computer bus.
Main
Processor memory

System bus

Disk/DMA DMA
Printer Keyboard
controller controller

Disk Disk Network


Interface

•Disk controller, which controls two disks also has DMA capability.
It provides two DMA channels.
•It can perform two independent DMA operations, as if each disk
has its own DMA controller. The registers to store the memory
address, word count and status and control information are
duplicated.

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Direct Memory Access (contd..)
● Processor and DMA controllers have to use the bus in an
interwoven fashion to access the memory.
● DMA devices are given higher priority than the processor to
access the bus.
● Among different DMA devices, high priority is given to high-
speed peripherals such as a disk or a graphics display device.
● Processor originates most memory access cycles on the bus.
● DMA controller can be said to “steal” memory access cycles
from the bus. This interweaving technique is called as “cycle
stealing”.
● An alternate approach is the provide a DMA controller an
exclusive capability to initiate transfers on the bus, and hence
exclusive access to the main memory. This is known as the block
or burst mode.

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Bus arbitration
● Processor and DMA controllers both need to initiate data
transfers on the bus and access main memory.
● The device that is allowed to initiate transfers on the bus at any
given time is called the bus master.
● When the current bus master relinquishes its status as the bus
master, anotherdevice can acquire this status.
● The process by which the next device to become the bus master
is selected and bus mastership is transferred to it is called bus
arbitration.
● Centralized arbitration:
● A single bus arbiter performs the arbitration.
● Distributed arbitration:
● All devices participate in the selection of the next bus master.

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Centralized Bus Arbitration

B BSY

BR

Processor

DMA DMA
controller controller
BG1 1 BG2 2

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Centralized Bus Arbitration(cont.,)
• Bus arbiter may be the processor or a separate unit connected to
the bus.
• Normally, the processor is the bus master, unless it grants bus
membership to one of the DMA controllers.
• DMA controller requests the control of the bus by asserting the
Bus Request (BR) line.
• In response, the processor activates the Bus-Grant1 (BG1) line,
indicating that the controller may use the bus when it is free.
• BG1 signal is connected to all DMA controllers in a daisy chain
fashion.
• BBSY signal is 0, it indicates that the bus is busy. When BBSY
becomes 1, the DMA controller which asserted BR can acquire

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Centralized arbitration
(contd..)
DMA controller 2
asserts the BR signal.
T ime

Processor asserts
BR the BG1 signal

BG1 BG1 signal propagates


to DMA#2.

BG2

B B S Y

Bus
master
Processor DMA controller 2 Processor

Processor relinquishes control


of the bus by setting BBSY to 1.

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Distributed arbitration
● All devices waiting to use the bus share the responsibility of
carrying out the arbitration process.
● Arbitration process does not depend on a central arbiter and
hence distributed arbitration has higher reliability.
● Each device is assigned a 4-bit ID number.
● All the devices are connected using 5 lines, 4 arbitration lines to
transmit the ID, and one line for the Start-Arbitration signal.
● To request the bus a device:
● Asserts the Start-Arbitration signal.
● Places its 4-bit ID numberon the arbitration lines.
● The pattern that appears on the arbitration lines is the logical-OR
of all the 4-bit device IDs placed on the arbitration lines.

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• In this DMA controller transfers one
word at a time after which it must
return the control of the buses to the
CPU.
• The CPU merely delays its operation
for one memory cycle to allow the
direct memory I/O transfer to “steal”
one memory cycle.
Steps Involved are:

1.Buffer the byte into the buffer


2.Inform the CPU that the device
has 1 byte to transfer (i.e. bus grant
request)
3.Transfer the byte (at system bus
speed)
4.Release the control of the bus
back to CPU.

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DMA returns the bus after complete data
transfer.
A register is used as a byte count,
being decremented for each byte transfer,
and upon the byte count reaching zero, the
DMAC will release the bus.
When the DMAC operates in burst mode,
the CPU is halted for the duration of the
data transfer.
Steps involved are:
1. Bus grant request time.
2. Transfer the entire block of data at
transfer rate of device because the
device is usually slow than the
speed at which the data can be
transferred to CPU.
3. Release the control of the bus back
to CPU

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Once the DMA controller is
granted access to the system
bus by the CPU, it transfers
all bytes of data in the data
block before releasing control
of the system buses back to
the CPU, but renders the CPU
inactive for relatively long
periods of time. The mode is
also called "Block Transfer
Mode".

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