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8x8 Dadda Multiplier Design

This document describes the design and implementation of an 8x8 bit multiplier using the Dadda algorithm. It begins with an abstract that outlines the goal of studying an 8-bit Dadda multiplier and increasing its speed and reducing power by using compressors. It then provides an introduction to multipliers and the Dadda algorithm. The body explains the Dadda algorithm and how it was implemented for an 8x8 bit multiplier over multiple stages using components like AND gates, full adders, half adders, and compressors. It compares the proposed design using compressors to a conventional Dadda multiplier. Finally, it mentions that Verilog code was written and a testbench was developed to test the design.

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MaLik Atif
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0% found this document useful (0 votes)
82 views14 pages

8x8 Dadda Multiplier Design

This document describes the design and implementation of an 8x8 bit multiplier using the Dadda algorithm. It begins with an abstract that outlines the goal of studying an 8-bit Dadda multiplier and increasing its speed and reducing power by using compressors. It then provides an introduction to multipliers and the Dadda algorithm. The body explains the Dadda algorithm and how it was implemented for an 8x8 bit multiplier over multiple stages using components like AND gates, full adders, half adders, and compressors. It compares the proposed design using compressors to a conventional Dadda multiplier. Finally, it mentions that Verilog code was written and a testbench was developed to test the design.

Uploaded by

MaLik Atif
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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I

UNIVERSITY OF ENGINEERING AND TECHNOLOGY


TAXILA.

DEPARTMENT OF ELECTRONICS ENGINEERING

FPGA LAB PROJECT

Submitted To:
Engr. Tahir Khan

Submitted By:
Obaid Ur Rehman (19-EN-11)
Malik Muhammad Atif Awan(19-ENC-17)
Asadullah Jutt (19-ENC-27)

Dated: 03-Feb-2023
II

Table of Contents
Abstract: .......................................................................................................................................................3
Introduction: ................................................................................................................................................4
Dadda Algorithm: ........................................................................................................................................5
Dadda Multiplier implementation: ............................................................................................................5
Conventional Dadda Multiplier: .................................................................................................................7
PROPOSED METHOD: .............................................................................................................................8
Dadda Verilog Code: ...................................................................................................................................8
Testbench: ..................................................................................................................................................13
III

Design and Implementation of 8x8 bit Multiplier


using Dadda Algorithm

Abstract:

Multipliers are vital components of any processor or computing machine. The performance of
microcontrollers and digital signal processors are evaluated on the basis of number of
multiplications performed in unit time. To increase speed and to reduce power the dadda
multiplier used with different compressors. The use of compressors in the multipliers not only
reduces the vertical critical path but also reduce the stage operation simultaneously. The speed of
the dadda multiplier is improved by introducing different compressors instead of 4:2 compressors.
Fast speed multiplication is a key requirement of the high performing digital systems. Here we
made a high speed dadda multiplier. This design uses less power than earlier designs, but power
consumption must still be decreased drastically, therefore it will be useful in bigger circuits where
the multiplier serves as a building block. The aim of this project is to study 8 bit dadda multiplier.
To increase speed and to reduce power the dadda multiplier used with different compressors. The
use of compressor in the multipliers not only reduce the vertical critical path but also reduce the
stage simultaneously
IV

Introduction:

One of most significant circuitry in the design of computer devices is indeed the multiplier. A
hardware binary multiplier is the Dadda multiplier. It sums the partial products in stages using a
variety of full and half adders until only two numbers remain. The model is very similar to the
Wallace multiplier, however the reductiontree decreases the power and area necessary and speeds
up the process significantly. To develop an optimized multiplier circuit, many design
implementation of a full adder and half adder circuits were used to reduce power and delay,
including pass transistor logic, split proportion information logic, and CMOS process
technology. Aside from that, many multiplication algorithms such as the Dadda, Wallace tree,
Vedic, and Booth procedures have been utilized to generate optimum power and delay products.
Multiplication is the basic arithmetic operations. Multiplication operations are widely used in
convolution, Fast Fourier Transform (FFT), filtering, as a frequency mixer in digital electronics.
A multiplier is a combinational logic circuit that we use to multiply binary digits. Full adders
and half adders are used asbuilding blocks. Different design implementations of a full adder and
half adder circuits have been used to reduce power and delay in order to design an optimized
multiplier circuit which includes pass transistor logic, CMOS process technology, split
percentage data-driven logic. Dadda Algorithm has been used to reduce the propagation delay
of the multiplier. The Dadda multiplier is a hardware multiplier design, invented by computer
scientist Luigi Dadda in 1965. It is one type of parallel multiplier. It is slightly faster (for all
operand sizes) and requires fewer gates (for all but the smallest operand sizes) than array
multiplier Dadda multipliers have less expensive reduction phase. Compared to a Wallace tree,
which requires ten full adders and half adders, the reduction phase of the Dadda multiplier
requires only six. The Dadda Multiplier requires less hardware than the Wallace. Compressors
are primary component of the multiplier. Large delay was observed in partial products addition
stage that increase the amount of power consumed. Using compressor adders, that add four, five,
six or seven bits at a time, the number of full adders and half adders are reduced and hence the
power consumed is less. Compressors are building blocks used for accumulating partial products
during the multiplication process. The basic idea in an n: 2compressor is that n operands can be
reduced to two, by doing the addition while keeping the carries and sums separate.
V

Dadda Algorithm:

One of the most efficient algorithms is Dadda algorithm. The proposed 8*8multiplier has a total of
64 partial products and it has 16 bits final result. For this simple technique, we have to use the
ripple carry adder, it also consumes less power, but the delay is significantly high. To reduce the
overall propagation delay of the multiplier Dadda algorithm has been applied. In the first stage, the
partial product matrix is formed. In the second stage, this partial product matrix is reduced to a
height of two. In the final stage, these two rows are combined using a carry propagating adder.

Dadda Multiplier implementation:

Dadda multiplier reduction scheme is implemented on the 8x8 bits which is shown in figure.

Figure: 8x8-bit Dadda Multiplier Reduction Scheme

Dadda multipliers do as few reductions as possible. Because of this, dadda multipliers have a less
expensive reduction phase, but the numbers may be a few bits longer, thus requiring slightly
bigger adders. To achieve this, the structure of the second step is governed by slightly more
complex rules than in the Wallace tree. As in the Wallace tree, a new layer is added if any weight
is carried by three or more wires. The reduction rules for the Dadda tree, however, are as follows:
Take any three wires with the same weights and input them into a full adder. The result will be an
output wire of the same weight and an output wire with a higher weight for each three input wires.
If there are two wires of the same weight left, and the current number of output wires with that
weight is equal to 2 (modulo 3), input them into a half adder. Otherwise, pass them through to the
next layer.
VI
If there is just one wire left, connect it to the next layer.
Dadda Multiplier uses in the first part, the AND gates to generate all partial products. In first
stage, two full adder, two half adder and nine compressors are used. In second stage, nine full
adders and four half adders are used. In third stage, two half adders and eleven full adders are
used. In fourth stage, ten half adders are used.
VII

Conventional Dadda Multiplier:

Dadda multipliers do as few reductions as possible. Because of this, dadda multipliers have a
less expensive reduction phase, but the numbers may be a few bits longer, thus requiring
slightly bigger adders. To achieve this, the structure of the second step is governed by slightly
more complex rules than in the Wallace tree. As in the Wallace tree, a new layer is added if any
weight is carried by three or more wires. The reduction rules for the Dadda tree, however, are as
follows:
1. Take any three wires with the same weights and input them into a full adder. Theresult will be
an output wire of the same weight and an output wire with a higher weight for each three input
wires.
2. If there are two wires of the same weight left, and the current number of output wires with
that weight is equal to 2 (modulo 3), input them into a half adder. Otherwise, pass them through
to the next layer.
3. If there is just one wire left, connect it to the next layer.

Fig.7.Dadda multiplier
VIII

PROPOSED METHOD:

Fig.8. Dadda multiplier using compressor

Dadda Multiplier uses in the first part, the AND gates to generate all partial products. In first
stage, two full adder, two half adder and nine compressors are used. In second stage, nine full
adders and four half adders are used. In third stage, two half adders and eleven full adders are
used. In fourth stage, ten half adders are used.

Dadda Verilog Code:


timescale 1ns / 1ps

module daddamultiplier(A,B,Y);
input [7:0] A;
input [7:0] B;
output wire [15:0]Y;
wire gen_pp [0:7][7:0];
// stage-1 sum and carry
wire [0:5]s1,c1;
// stage-2 sum and carry

wire [0:13]s2,c2;
// stage-3 sum and carry
wire [0:9]s3,c3;
// stage-4 sum and carry
wire [0:11]s4,c4;
// stage-5 sum and carry
IX
wire [0:13]s5,c5;

// generating partial products


genvar i;
genvar j;
for(i = 0; i<8; i=i+1)
begin
for(j = 0; j<8;j = j+1)
begin
assign gen_pp[i][j] = A[j]*B[i];
end
end

//Reduction by stages.
// di_values = 2,3,4,6,8,13...
//Stage 1 - reducing fom 8 to 6
HA h1(.a(gen_pp[6][0]),.b(gen_pp[5][1]),.Sum(s1[0]),.Cout(c1[0]));
HA h2(.a(gen_pp[4][3]),.b(gen_pp[3][4]),.Sum(s1[2]),.Cout(c1[2]));
HA h3(.a(gen_pp[4][4]),.b(gen_pp[3][5]),.Sum(s1[4]),.Cout(c1[4]));
csa_dadda c11(.A(gen_pp[7][0]),.B(gen_pp[6][1]),.Cin(gen_pp[5][2]),.Y(s1[1]),.Cout(c1[1])
);
csa_dadda c12(.A(gen_pp[7][1]),.B(gen_pp[6][2]),.Cin(gen_pp[5][3]),.Y(s1[3]),.Cout(c1[3])
);
csa_dadda c13(.A(gen_pp[7][2]),.B(gen_pp[6][3]),.Cin(gen_pp[5][4]),.Y(s1[5]),.Cout(c1[5])
);

//Stage 2 - reducing fom 6 to 4

HA h4(.a(gen_pp[4][0]),.b(gen_pp[3][1]),.Sum(s2[0]),.Cout(c2[0]));
HA h5(.a(gen_pp[2][3]),.b(gen_pp[1][4]),.Sum(s2[2]),.Cout(c2[2]));
csa_dadda c21(.A(gen_pp[5][0]),.B(gen_pp[4][1]),.Cin(gen_pp[3][2]),.Y(s2[1]),.Cout(c2[1])
);
csa_dadda c22(.A(s1[0]),.B(gen_pp[4][2]),.Cin(gen_pp[3][3]),.Y(s2[3]),.Cout(c2[3]));
csa_dadda c23(.A(gen_pp[2][4]),.B(gen_pp[1][5]),.Cin(gen_pp[0][6]),.Y(s2[4]),.Cout(c2[4])
);
csa_dadda c24(.A(s1[1]),.B(s1[2]),.Cin(c1[0]),.Y(s2[5]),.Cout(c2[5]));
X
csa_dadda c25(.A(gen_pp[2][5]),.B(gen_pp[1][6]),.Cin(gen_pp[0][7]),.Y(s2[6]),.Cout(c2[6])
);

csa_dadda c26(.A(s1[3]),.B(s1[4]),.Cin(c1[1]),.Y(s2[7]),.Cout(c2[7]));
csa_dadda c27(.A(c1[2]),.B(gen_pp[2][6]),.Cin(gen_pp[1][7]),.Y(s2[8]),.Cout(c2[8]));
csa_dadda c28(.A(s1[5]),.B(c1[3]),.Cin(c1[4]),.Y(s2[9]),.Cout(c2[9]));
csa_dadda c29(.A(gen_pp[4][5]),.B(gen_pp[3][6]),.Cin(gen_pp[2][7]),.Y(s2[10]),.Cout(c2[10]));
csa_dadda c210(.A(gen_pp[7][3]),.B(c1[5]),.Cin(gen_pp[6][4]),.Y(s2[11]),.Cout(c2[11]));
csa_dadda c211(.A(gen_pp[5][5]),.B(gen_pp[4][6]),.Cin(gen_pp[3][7]),.Y(s2[12]),.Cout(c2[
12]));
csa_dadda c212(.A(gen_pp[7][4]),.B(gen_pp[6][5]),.Cin(gen_pp[5][6]),.Y(s2[13]),.Cout(c2[
13]));

//Stage 3 - reducing fom 4 to 3


HA h6(.a(gen_pp[3][0]),.b(gen_pp[2][1]),.Sum(s3[0]),.Cout(c3[0])); csa_dadda
c31(.A(s2[0]),.B(gen_pp[2][2]),.Cin(gen_pp[1][3]),.Y(s3[1]),.Cout(c3[1]));
csa_dadda c32(.A(s2[1]),.B(s2[2]),.Cin(c2[0]),.Y(s3[2]),.Cout(c3[2]));
csa_dadda c33(.A(c2[1]),.B(c2[2]),.Cin(s2[3]),.Y(s3[3]),.Cout(c3[3]));
csa_dadda c34(.A(c2[3]),.B(c2[4]),.Cin(s2[5]),.Y(s3[4]),.Cout(c3[4]));
csa_dadda c35(.A(c2[5]),.B(c2[6]),.Cin(s2[7]),.Y(s3[5]),.Cout(c3[5]));

csa_dadda c36(.A(c2[7]),.B(c2[8]),.Cin(s2[9]),.Y(s3[6]),.Cout(c3[6]));
csa_dadda c37(.A(c2[9]),.B(c2[10]),.Cin(s2[11]),.Y(s3[7]),.Cout(c3[7]));

csa_dadda c38(.A(c2[11]),.B(c2[12]),.Cin(s2[13]),.Y(s3[8]),.Cout(c3[8]));
csa_dadda c39(.A(gen_pp[7][5]),.B(gen_pp[6][6]),.Cin(gen_pp[5][7]),.Y(s3[9]),.Cout(c3[9])
);

//Stage 4 - reducing fom 3 to 2

HA h7(.a(gen_pp[2][0]),.b(gen_pp[1][1]),.Sum(s4[0]),.Cout(c4[0]));

csa_dadda c41(.A(s3[0]),.B(gen_pp[1][2]),.Cin(gen_pp[0][3]),.Y(s4[1]),.Cout(c4[1]));
csa_dadda c42(.A(c3[0]),.B(s3[1]),.Cin(gen_pp[0][4]),.Y(s4[2]),.Cout(c4[2]));
csa_dadda c43(.A(c3[1]),.B(s3[2]),.Cin(gen_pp[0][5]),.Y(s4[3]),.Cout(c4[3]));
csa_dadda c44(.A(c3[2]),.B(s3[3]),.Cin(s2[4]),.Y(s4[4]),.Cout(c4[4]));
csa_dadda c45(.A(c3[3]),.B(s3[4]),.Cin(s2[6]),.Y(s4[5]),.Cout(c4[5]));
XI
csa_dadda c46(.A(c3[4]),.B(s3[5]),.Cin(s2[8]),.Y(s4[6]),.Cout(c4[6]));
csa_dadda c47(.A(c3[5]),.B(s3[6]),.Cin(s2[10]),.Y(s4[7]),.Cout(c4[7]));
csa_dadda c48(.A(c3[6]),.B(s3[7]),.Cin(s2[12]),.Y(s4[8]),.Cout(c4[8]));
csa_dadda c49(.A(c3[7]),.B(s3[8]),.Cin(gen_pp[4][7]),.Y(s4[9]),.Cout(c4[9]));
csa_dadda c410(.A(c3[8]),.B(s3[9]),.Cin(c2[13]),.Y(s4[10]),.Cout(c4[10]));
csa_dadda c411(.A(c3[9]),.B(gen_pp[7][6]),.Cin(gen_pp[6][7]),.Y(s4[11]),.Cout(c4[11]));

//Stage 5 - reducing fom 2 to 1


// adding total sum and carry to get final output

HA h8(.a(gen_pp[1][0]),.b(gen_pp[0][1]),.Sum(Y[1]),.Cout(c5[0]));

csa_dadda c51(.A(s4[0]),.B(gen_pp[0][2]),.Cin(c5[0]),.Y(Y[2]),.Cout(c5[1]));
csa_dadda c52(.A(c4[0]),.B(s4[1]),.Cin(c5[1]),.Y(Y[3]),.Cout(c5[2]));
csa_dadda c54(.A(c4[1]),.B(s4[2]),.Cin(c5[2]),.Y(Y[4]),.Cout(c5[3]));

csa_dadda c55(.A(c4[2]),.B(s4[3]),.Cin(c5[3]),.Y(Y[5]),.Cout(c5[4]));
csa_dadda c56(.A(c4[3]),.B(s4[4]),.Cin(c5[4]),.Y(Y[6]),.Cout(c5[5]));

csa_dadda c57(.A(c4[4]),.B(s4[5]),.Cin(c5[5]),.Y(Y[7]),.Cout(c5[6]));
csa_dadda c58(.A(c4[5]),.B(s4[6]),.Cin(c5[6]),.Y(Y[8]),.Cout(c5[7]));
csa_dadda c59(.A(c4[6]),.B(s4[7]),.Cin(c5[7]),.Y(Y[9]),.Cout(c5[8]));
csa_dadda c510(.A(c4[7]),.B(s4[8]),.Cin(c5[8]),.Y(Y[10]),.Cout(c5[9]));
csa_dadda c511(.A(c4[8]),.B(s4[9]),.Cin(c5[9]),.Y(Y[11]),.Cout(c5[10]));

csa_dadda c512(.A(c4[9]),.B(s4[10]),.Cin(c5[10]),.Y(Y[12]),.Cout(c5[11]));
csa_dadda c513(.A(c4[10]),.B(s4[11]),.Cin(c5[11]),.Y(Y[13]),.Cout(c5[12]));
csa_dadda c514(.A(c4[11]),.B(gen_pp[7][7]),.Cin(c5[12]),.Y(Y[14]),.Cout(c5[13]));

assign Y[0] = gen_pp[0][0]; assign Y[15] = c5[13];


endmodule
XII
CSA Dadda:

module csa_dadda(A,B,Cin,Y,Cout);
input A,B,Cin;
output Y,Cout;

assign Y = A^B^Cin;
assign Cout = (A&B)|(A&Cin)|(B&Cin);

endmodule

Half Adder:

`timescale 1ns / 1ps


//////////////////////////////////////////////////////////////////////////////////
// Designing in Half Adder
// Sum = a XOR b, Cout = a AND b

module HA(a, b, Sum, Cout);


input a, b; // a and b are inputs with size 1-bit
output Sum, Cout; // Sum and Cout are outputs with size 1-bit
assign Sum = a ^ b;
assign Cout = a & b;
endmodule

FULL ADDER:

module Full_Add(Sum,Carry,a,b,cin);
input a,b,cin;
output Sum,Carry;
wire M,N,O;
xor X1(M,X,Y);
and A1(N,X,Y);
xor X2(Sum,M,cin);
and A2(O,M,cin);
or O1(Carry,O,N);
endmodule
XIII

Testbench:
module daddamultiplier_tb( );
parameter N=8,M=8;
reg [N-1:0]A;
reg [M-1:0]B;
wire [N+M-1:0]Y;
daddamultiplier v1(.A(A),.B(B),.Y(Y));
initial
begin
A=8'b00011100; B=8'b00011001;
#15
A=8'b00011101; B=8'b00000111;
#15
A=8'b00011110; B=8'b00010100;
#15
A=8'b00000101; B=8'b00000111;
#15
A=8'b00001010; B=8'b00001011;
end
endmodule
XIV

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