University of Engineering
&
Technology, Taxila
DSD
Lab Manual# 03
GROUP NO 3
6TH SEMESTER
OMEGA SECTION
SUBMITTED TO: ENGR.ASGHAR ISMAIL
Dated;
18/07/2023
Objective:
Designing, Simulating and Implementing the HDL code for 4-bit 4x1 Mux, 2-bit 4x1 Mux, 1-bit
1x8 Demultiplexer, 3x8 Decoder, and 4x16 decoder using two 3x8 decoder and additional logic (Enable)
Procedure:
1. Writing the Source Code of module and simulating it
2. Opening Elaborated Design
3. Setting Constraints
4. Running Synthesis
5. After Successful Synthesis Running Implementation
6. After Successful Implementation Generating Bit Stream
7. Downloading Bit Stream to FPGA kit using Hardware Manager
Apparatus List:
• Verilog HDL
• FPGA Development Board
• Xilinx Vivado or any other Verilog simulation and synthesis tool
TASK 1:
Verilog Code for 4-bit 4x1 Mux and simulate it only.
Verilog Code:
Source code Testbench
module mux4x1(a,b,c,d,sel,out); module mux4to1(); reg
input [3:0]a; input [3:0]b; input [3:0] a,b,c,d; wire
[3:0]c; //array input [3:0]d; [3:0]out; reg [1:0]sel;
input [1:0]sel; output [3:0]out; integer i; mux4x1
reg [3:0]out; always@(*) begin DUT(.a(a), .b(b),
case(sel) 2'b00: out<=a; 2'b01: .c(c),.d(d),.sel(sel),.out(out)); initial
out<=b; 2'b10: out<=c; 2'b11:
begin a=4'b0000; b=4'b0001;
out<=d; endcase end endmodule
c=4'b0010; d=
4'b0011;
for(i=0; i<=3;
i=i+1) begin #10
sel=1; end
end
endmodule
RESULTS:
Schematic Diagram:
Simulation
TASK 2:
2-bit 4x1 Mux Simulation and Implementation on FPGA Kit
Truth Table
sel out
2’b00 A
2’b01 B
2’b10 C
2’b11 D
Verilog Code:
Source code Testbench
module module tb_mux4x1_2B();
mux4x1_2B(a,b,c,d,sel,out); input
[1:0]a, b, c, d; input [1:0]sel; output reg [1:0] a,b,c,d;
reg [1:0]out; always@(*) begin wire [1:0]out; reg
case(sel) 2'b00: out<=a; 2'b01: [1:0]sel; integer
out<=b; 2'b10: out<=c; 2'b11: i;
out<=d; endcase end endmodule
mux4x1_2B DUT(.a(a), .b(b),
.c(c),.d(d),.sel(sel),.out(out)); initial
begin a=2'b00; b=2'b01; c=2'b10; d=
2'b11;
for(i=0; i<=1; i=i+1)
begin
#10 sel=1;
end
endmodule
RESULTS:
Schematic Diagram:
Simulation:
FPGA Implementation
Sel=00 Sel=01
Sel=10 Sel=11
TASK 3:
1-bit 1x8 Demultiplexer Simulation and Implementation on FPGA Kit
Truth Table:
S2 S1 S0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Verilog Code:
Source code Testbench
module module
oneto8demux(d0,s0,s1,s2,OUT); input test_bench(); reg
s2,s1,s0; output [7:0]OUT; reg s0,s1,s2; wire
[7:0]OUT; input d0; [7:0]OUT; reg d0;
always@(d0 or s0 or s1 or s2) oneto8demux
begin DUT(.d0(d0),.s0(s0),.s1(s1),.s2(s2),.OUT(O
case({s2,s1,s0}) UT)); initial begin
0:OUT=8'b00000001; #10 s2=1'b0;s1=1'b0;s0=1'b0;d0=1'b1;
#10 s2=1'b0;s1=1'b0;s0=1'b1;d0=1'b1;
1:OUT=8'b00000010;
#10 s2=1'b0;s1=1'b1;s0=1'b0;d0=1'b1;
2:OUT=8'b00000100;
#10 s2=1'b0;s1=1'b1;s0=1'b1;d0=1'b1;
3:OUT=8'b00001000;
#10 s2=1'b1;s1=1'b0;s0=1'b0;d0=1'b1;
4:OUT=8'b00010000; #10 s2=1'b1;s1=1'b0;s0=1'b1;d0=1'b1;
5:OUT=8'b00100000;
#10 s2=1'b1;s1=1'b1;s0=1'b0;d0=1'b1;
6:OUT=8'b01000000;
#10
7:OUT=8'b10000000;
s2=1'b1;s1=1'b1;s0=1'b1;d0=1'b1;
endcase
end end endmodule
endmodule
RESULTS:
Schematic Diagram:
Simulation:
FPGA Implementation:
1) S0=1, S1=1, S2=1
2) S0=1, S1=0, S2=1
TASK 4:
3x8 Decoder Simulation and Implementation on FPGA Kit
Truth Table
S2 S1 S0 D1 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Verilog Code:
Source code Testbench
module module tb_decod3x8();
decod3x8(data_out,data_in); input reg [2:0] data_in;
[2:0]data_in; wire [7:0] data_out;
output [7:0]data_out; decod3x8 DUT (
reg [7:0]data_out; .data_in(data_in),
always@(data_in) begin .data_out(data_out)
case(data_in) 8'b00000_001; ); initial begin data_in =
8'b00000_010; 3'b000; #10; data_in = 3'b001; #10;
3'b000: data_out=
data_in = 3'b010; #10; data_in =
3'b001: data_out= 8'b00000_100; 3'b011; #10; data_in = 3'b100; #10;
3'b010: data_out= 8'b00001_000; data_in = 3'b101; #10; data_in =
3'b110; #10; data_in = 3'b111; #10;
3'b011: data_out= 8'b00010_000;
end endmodule
3'b100: data_out= 8'b00100_000;
3'b101: data_out= 8'b01000_000;
8'b10000_000;
3'b110: data_out= 3'b111:
data_out= default: data_out=
8'b10000_000;
endcase
end
endmodule
RESULTS:
Schematic Diagram:
Simulation:
FPGA Implementation:
1) S0=0, S1=1, S2=0
2) S0=1, S1=1, S2=1
TASK 5:
4x16 decoder using two 3x8 decoder and additional logic (Enable) Simulation and
Implementation on FPGA Kit.
Truth Table
Enable S S S D0 D2 D4 D6 D8 D10D D12D D14D
ew 2 1 0 D1 D3 D5 D7 D9 11 13 15
0 0 0 0 10 00 00 00 00 00 00 00
0 0 0 1 01 00 00 00 00 00 00 00
0 0 1 0 00 10 00 00 00 00 00 00
0 0 1 1 00 01 00 00 00 00 00 00
0 1 0 0 00 00 10 00 00 00 00 00
0 1 0 1 00 00 01 00 00 00 00 00
0 1 1 0 00 00 00 10 00 00 00 00
0 1 1 1 00 00 00 01 00 00 00 00
1 0 0 0 00 00 00 00 10 00 00 00
1 0 0 1 00 00 00 00 01 00 00 00
1 0 1 0 00 00 00 00 00 10 00 00
1 0 1 1 00 00 00 00 00 01 00 00
1 1 0 0 00 00 00 00 00 00 10 00
1 1 0 1 00 00 00 00 00 00 01 00
1 1 1 0 00 00 00 00 00 00 00 10
1 1 1 1 00 00 00 00 00 00 00 01
Verilog Code:
Source code Testbench
module module sim_4x16_decoder();
reg [2:0]Data_in;
task5(Data_out,Data_in,enable); reg enable; wire
input [2:0] Data_in; input [15:0]Data_out;
task5
enable ; output [15:0] Data_out; DUT(.Data_in(Data_in),.enable(enable),.Data_out(Data_out));
reg [15:0] Data_out; initial begin enable=1'b0; Data_in=4'b000;
#10
always@(Data_in) Data_in=4'b010;
if(enable==0) case(Data_in) #10
enable=1'b1; Data_in=4'b000;
3'b000:Data_out=8'b00000001;
#10
3'b001:Data_out=8'b00000010; Data_in=4'b010;
3'b010:Data_out=8'b00000100; end endmodule
3'b011:Data_out=8'b00001000;
3'b100:Data_out=8'b00010000;
3'b101:Data_out=8'b00100000;
3'b110:Data_out=8'b01000000;
3'b111:Data_out=8'b10000000;
default:Data_out=8'b10000000;
endcase else case(Data_in)
3'b000:Data_out=8'b00000001;
3'b001:Data_out=8'b00000010;
3'b010:Data_out=8'b00000100;
3'b011:Data_out=8'b00001000;
3'b100:Data_out=8'b00010000;
3'b101:Data_out=8'b00100000;
3'b110:Data_out=8'b01000000;
3'b111:Data_out=8'b10000000;
default:Data_out=8'b10000000; endcase
endmodule
RESULTS:
Schematic Diagram:
Simulation:
FPGA Implementation:
1) a0a1a2e= 1110
2) a0a1a2e= 0101
Conclusion:
We can conclude
• A 4-bit 4x1 mux will have 4 inputs, 4-bit each, and a 4- bit output with 2 bits select line. Mux will
select 1 of 4 inputs on the basis of select line.
• 2-bit 4x1 mux will have 4 inputs, 2-bit each, and a 2-bit output and with 2 bits select line. Mux
will select 1 of 4 inputs because of select line. Results are verified through implementation on
FPGA Kit.
• One common input line of 1x8 demux will be switched to one of the 8 output lines according to
select bits. Results are verified on FPGA Kit.
• 3x8 decoder works on the basis of 3 inputs which are used to select one of 8 outputs.
• When two 3 to 8 Decoder circuits are combined to make a 4x16 decoder, the enable pin acts as
the input for both the decoders. When enable pin is high at one 3 to 8 decoder circuits then it is
low at another 3 to 8 decoder circuit. Results are verified on Kit.
∙∙·▫▫ᵒᴼᵒ▫ₒₒ▫ᵒᴼᵒ▫ₒₒ▫ᵒᴼᵒ THE END ᵒᴼᵒ▫ₒₒ▫ᵒᴼᵒ▫ₒₒ▫ᵒᴼᵒ▫▫·∙∙
