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Verilog Lab File

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Bipin Kumar
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34 views41 pages

Verilog Lab File

Uploaded by

Bipin Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Laboratory File

of
DIGITAL SYSTEM DESIGN USING VERILOG
Name :- Bipin Kumar
Entry no. :- 22BEC038
Faculty Guide:- Dr. Vijay Kumar Sharma
Semester :- 5th
INDEX
EXPERIMENT 1:- AND gate
EXPERIMENT 2:- XNOR gate
EXPERIMENT 3:- Half Adder
EXPERIMENT 4:- Full Adder
EXPERIMENT 5:- 2x1 mux
EXPERIMENT 6:- 4x1 mux
EXPERIMENT 7:- 2x4 decoder
EXPERIMENT 8:- 3x8 decoder
EXPERIMENT 9:- D Flip-Flop
EXPERIMENT 10:- JK Flip-Flop
EXPERIMENT 11:- T Flip-Flop
1. AND gate

1.1. Verilog Code:

module and_gate(
input a,
input b,
output out );

assign out=a&b;

endmodule

1.2. Test Bench:

module and_tb;
reg a,b;
wire out;

and_gate uut(.a(a),.b(b),.out(out));

ini al begin
$dumpfile("dump.vcd"); $dumpvars;
a=0;
b=0;

#10 a=1;b=0;
#10 a=0;b=1;
#10 a=1;b=1;
#10 $finish;
end
endmodule
1.3. Output Waveforms:
2. XNOR gate
2.1. Verilog Code:

module xnor_gate(
input a,
input b,
output out );

assign out=~(a^b);

endmodule

2.2. Test Bench:

module xnor_tb;
reg a,b;
wire out;

xnor_gate uut(.a(a),.b(b),.out(out));

ini al begin
$dumpfile("dump.vcd"); $dumpvars;
a=0;
b=0;

#10 a=1;b=0;
#10 a=0;b=1;
#10 a=1;b=1;
#10 $finish;
end
endmodule
2.3. Output Waveforms:
3. Half Adder
3.1. Verilog Code:

module half_adder(
input a,b,
output sum,cout);

assign sum=a^b;
assign cout=a&b;

endmodule

3.2. Test Bench:

module half_adder_tb;
reg in1,in2;
wire sum1,cout1;

half_adder uut(.a(in1),.b(in2),.sum(sum1),.cout(cout1));

ini al begin
$dumpfile("dump.vcd"); $dumpvars;
in1=0;in2=0;
#10 in1=0;in2=1;
#10 in1=1;in2=0;
#10 in1=1;in2=1;
#10 $finish;
end
endmodule

3.3. Output Waveforms:


4. Full Adder
4.1. Verilog Code:

module full_adder(
input a,b,cin,
output sum,cout);

assign sum=a^b^cin;
assign cout=(a&b)|(b&cin)|(cin&a);

endmodule

4.2. Test Bench:

module half_adder_tb;
reg in1,in2,cin1;
wire sum1,cout1;

full_adder uut(.a(in1),.b(in2),.cin(cin1),.sum(sum1),.cout(cout1));

ini al begin
$dumpfile("dump.vcd"); $dumpvars;
in1=0;in2=0;cin1=0;
#10 in1=0;in2=0;cin1=1;
#10 in1=0;in2=1;cin1=0;
#10 in1=0;in2=1;cin1=1;
#10 in1=1;in2=0;cin1=0;
#10 in1=1;in2=0;cin1=1;
#10 in1=1;in2=1;cin1=0;
#10 in1=1;in2=1;cin1=1;
#10 $finish;
end
endmodule

4.3. Output Waveforms:


5. 2x1 mux
5.1. Verilog Code:

module mux_2_1(
input a,b,sel,
output reg out);

always @(*)
begin
if(sel)
out=b;
else
out=a;
end

endmodule
5.2. Test Bench:

module mux_2_1_tb;
reg a1,a2,sel1;
wire out1;

mux_2_1 uut(.a(a1),.b(a2),.sel(sel1),.out(out1));

ini al begin
$dumpfile("dump.vcd"); $dumpvars;
a1=0;a2=0;sel1=0;
#10 a1=0;a2=0;sel1=1;
#10 a1=0;a2=1;sel1=0;
#10 a1=0;a2=1;sel1=1;
#10 a1=1;a2=0;sel1=0;
#10 a1=1;a2=0;sel1=1;
#10 a1=1;a2=1;sel1=0;
#10 a1=1;a2=1;sel1=1;
#10 $finish;
end
endmodule

5.3. Output Waveforms:


6. 4x1 mux
6.1. Verilog Code:
module mux_4_1(
input a, b, c, d, sel0, sel1,
output reg out
);

always @(*) begin


case ({sel1, sel0})
2'b00: out = a;
2'b01: out = b;
2'b10: out = c;
2'b11: out = d;
endcase
end

endmodule
6.2. Test Bench:
module mux_4_1_tb;
reg a1, b1, c1, d1, sel0, sel1;
wire out1;

mux_4_1 uut(
.a(a1),
.b(b1),
.c(c1),
.d(d1),
.sel0(sel0),
.sel1(sel1),
.out(out1)
);

ini al begin
$dumpfile("dump.vcd"); $dumpvars;
a1 = 0; b1 = 0; c1 = 0; d1 = 0; sel0 = 0; sel1 = 0;
#10 a1 = 0; b1 = 1; c1 = 0; d1 = 0; sel0 = 1; sel1 = 0;
#10 a1 = 0; b1 = 0; c1 = 1; d1 = 0; sel0 = 0; sel1 = 1;
#10 a1 = 0; b1 = 0; c1 = 0; d1 = 1; sel0 = 1; sel1 = 1;
#10 a1 = 1; b1 = 0; c1 = 0; d1 = 0; sel0 = 0; sel1 = 0;
#10 a1 = 0; b1 = 1; c1 = 0; d1 = 0; sel0 = 1; sel1 = 0;
#10 a1 = 0; b1 = 0; c1 = 1; d1 = 0; sel0 = 0; sel1 = 1;
#10 a1 = 0; b1 = 0; c1 = 0; d1 = 1; sel0 = 1; sel1 = 1;
#10 $finish;
end
endmodule
6.3. Output Waveforms:
7. 2x4 decoder
7.1. Verilog Code:
module decoder_2x4(
input [1:0] in,
input enable,
output reg [3:0] out
);

always @(*) begin


if (enable)
case (in)
2'b00: out = 4'b0001;
2'b01: out = 4'b0010;
2'b10: out = 4'b0100;
2'b11: out = 4'b1000;
default: out = 4'b0000;
endcase
else
out = 4'b0000;
end

endmodule
7.2. Test Bench:
module decoder_2x4_tb;
reg [1:0] in_tb;
reg enable_tb;
wire [3:0] out_tb;

decoder_2x4 uut (
.in(in_tb),
.enable(enable_tb),
.out(out_tb)
);
ini al begin
$dumpfile("decoder.vcd");
$dumpvars(0, decoder_2x4_tb);

enable_tb = 0; in_tb = 2'b00; #10;


enable_tb = 1; in_tb = 2'b00; #10;
enable_tb = 1; in_tb = 2'b01; #10;
enable_tb = 1; in_tb = 2'b10; #10;
enable_tb = 1; in_tb = 2'b11; #10;
enable_tb = 0; in_tb = 2'b11; #10;

$finish;
end
endmodule
7.3. Output Waveforms:
8. 3x8 decoder
8.1. Verilog Code:
module decoder_3x8(
input [2:0] in,
input enable,
output reg [7:0] out
);

always @(*) begin


if (enable)
case (in)
3'b000: out = 8'b00000001;
3'b001: out = 8'b00000010;
3'b010: out = 8'b00000100;
3'b011: out = 8'b00001000;
3'b100: out = 8'b00010000;
3'b101: out = 8'b00100000;
3'b110: out = 8'b01000000;
3'b111: out = 8'b10000000;
default: out = 8'b00000000;
endcase
else
out = 8'b00000000;
end

endmodule
8.2. Test Bench:
module decoder_3x8_tb;
reg [2:0] in_tb;
reg enable_tb;
wire [7:0] out_tb;

decoder_3x8 uut (
.in(in_tb),
.enable(enable_tb),
.out(out_tb)
);

ini al begin
$dumpfile("decoder.vcd");
$dumpvars(0, decoder_3x8_tb);

enable_tb = 0; in_tb = 3'b000; #10;


enable_tb = 1; in_tb = 3'b000; #10;
enable_tb = 1; in_tb = 3'b001; #10;
enable_tb = 1; in_tb = 3'b010; #10;
enable_tb = 1; in_tb = 3'b011; #10;
enable_tb = 1; in_tb = 3'b100; #10;
enable_tb = 1; in_tb = 3'b101; #10;
enable_tb = 1; in_tb = 3'b110; #10;
enable_tb = 1; in_tb = 3'b111; #10;
enable_tb = 0; in_tb = 3'b111; #10;

$finish;
end
endmodule
8.3. Output Waveforms:
9. D Flip-Flop
9.1. Verilog Code:
module d_flip_flop(
input d,
input clk,
input reset,
output reg q
);

always @(posedge clk or posedge reset) begin


if (reset)
q <= 0;
else
q <= d;
end

endmodule
9.2. Test Bench:
module d_flip_flop_tb;
reg d_tb;
reg clk_tb;
reg reset_tb;
wire q_tb;

d_flip_flop uut (
.d(d_tb),
.clk(clk_tb),
.reset(reset_tb),
.q(q_tb)
);

ini al begin
$dumpfile("d_flip_flop.vcd");
$dumpvars(0, d_flip_flop_tb);
clk_tb = 0;
reset_tb = 0; d_tb = 0; #10;
reset_tb = 1; #10;
reset_tb = 0; d_tb = 1; #10;
d_tb = 0; #10;
d_tb = 1; #10;

$finish;
end

always #5 clk_tb = ~clk_tb;

endmodule
9.3. Output Waveforms:
10. JK Flip-Flop
10.1. Verilog Code:
module jk_flip_flop(
input j,
input k,
input clk,
input reset,
output reg q
);

always @(posedge clk or posedge reset) begin


if (reset)
q <= 0;
else begin
case ({j, k})
2'b00: q <= q;
2'b01: q <= 0;
2'b10: q <= 1;
2'b11: q <= ~q;
endcase
end
end

endmodule
10.2. Test Bench:
module jk_flip_flop_tb;
reg j_tb;
reg k_tb;
reg clk_tb;
reg reset_tb;
wire q_tb;

jk_flip_flop uut (
.j(j_tb),
.k(k_tb),
.clk(clk_tb),
.reset(reset_tb),
.q(q_tb)
);

ini al begin
$dumpfile("jk_flip_flop.vcd");
$dumpvars(0, jk_flip_flop_tb);

clk_tb = 0;
reset_tb = 1; j_tb = 0; k_tb = 0; #10;
reset_tb = 0; j_tb = 0; k_tb = 0; #10;
j_tb = 0; k_tb = 1; #10;
j_tb = 1; k_tb = 0; #10;
j_tb = 1; k_tb = 1; #10;
$finish;
end

always #5 clk_tb = ~clk_tb;

endmodule
10.3. Output Waveforms:
11. T Flip-Flop
11.1. Verilog Code:
module t_flip_flop(
input t,
input clk,
input reset,
output reg q
);

always @(posedge clk or posedge reset) begin


if (reset)
q <= 0;
else if (t)
q <= ~q;
end

endmodule
11.2. Test Bench:
module t_flip_flop_tb;
reg t_tb;
reg clk_tb;
reg reset_tb;
wire q_tb;

t_flip_flop uut (
.t(t_tb),
.clk(clk_tb),
.reset(reset_tb),
.q(q_tb)
);

ini al begin
$dumpfile("t_flip_flop.vcd");
$dumpvars(0, t_flip_flop_tb);
clk_tb = 0;
reset_tb = 1; t_tb = 0; #10;
reset_tb = 0; t_tb = 0; #10;
t_tb = 1; #10;
t_tb = 1; #10;
t_tb = 0; #10;

$finish;
end

always #5 clk_tb = ~clk_tb;

endmodule
11.3. Output Waveforms:

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