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Examples Verilog

The document provides various examples of Verilog HDL modules for digital design, including adders, encoders, decoders, multiplexers, flip-flops, and counters. Each example includes the module's inputs, outputs, and internal logic, demonstrating different coding styles such as behavioral and structural. Additionally, references for further reading on Verilog HDL are included.

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15 views9 pages

Examples Verilog

The document provides various examples of Verilog HDL modules for digital design, including adders, encoders, decoders, multiplexers, flip-flops, and counters. Each example includes the module's inputs, outputs, and internal logic, demonstrating different coding styles such as behavioral and structural. Additionally, references for further reading on Verilog HDL are included.

Uploaded by

tazz mails
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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References

1. Verilog HDL : A Guide to Digital Design and Synthesis by Samir Palnitkar


Published by Prentice Hall, March 1996
2. Verilog HDL Synthesis, A Practical Primer by J. Bhasker ISBN 0-9650391-5-3
3. A Verilog HDL Primer by J. Bhasker Bk&Hardcover; Published by Star Galaxy
Press.ISBN: 0-9656277-4-8

Example 1.
module example1 (x1, x2, x3, f);
input x1, x2, x3;
output f;

and (g, x1, x2);


not (k,x2);
and (h, k, x3);
or (f, g, h);

endmodule

Example 2.
// Behavioral specification
module example5 (x1, x2, x3, f);
input x1, x2, x3;
output f;
reg f;

always @(x1 or x2 or x3)


if (x2 == 1)
f = x1;
else
f = x3;

endmodule

Example 3.(Adder)
module adder4 (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0,
carryout);
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;

fulladd stage0 (carryin, x0, y0, s0, c1);


fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, s2, c3);
fulladd stage3 (c3, x3, y3, s3, carryout);

endmodule

module fulladd (Cin, x, y, s, Cout);


input Cin, x, y;
output s, Cout;

assign s = x ^ y ^ Cin,
Cout = (x & y) | (x & Cin) | (y & Cin);
endmodule

Example 4. (Encoder using if)


module encoder_using_if(
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable // Enable for the encoder
);
//-----------Output Ports---------------
output [3:0] binary_out ;
//-----------Input Ports---------------
input enable ;
input [15:0] encoder_in ;
//------------Internal Variables--------
reg [3:0] binary_out ;
//-------------Code Start-----------------
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
if (encoder_in == 16'h0002) begin
binary_out = 1;
end if (encoder_in == 16'h0004) begin
binary_out = 2;
end if (encoder_in == 16'h0008) begin
binary_out = 3;
end if (encoder_in == 16'h0010) begin
binary_out = 4;
end if (encoder_in == 16'h0020) begin
binary_out = 5;
end if (encoder_in == 16'h0040) begin
binary_out = 6;
end if (encoder_in == 16'h0080) begin
binary_out = 7;
end if (encoder_in == 16'h0100) begin
binary_out = 8;
end if (encoder_in == 16'h0200) begin
binary_out = 9;
end if (encoder_in == 16'h0400) begin
binary_out = 10;
end if (encoder_in == 16'h0800) begin
binary_out = 11;
end if (encoder_in == 16'h1000) begin
binary_out = 12;
end if (encoder_in == 16'h2000) begin
binary_out = 13;
end if (encoder_in == 16'h4000) begin
binary_out = 14;
end if (encoder_in == 16'h8000) begin
binary_out = 15;
end
end
end

endmodule

Example 5. (Encoder using case)


module encoder_using_case(
binary_out , // 4 bit binary Output
encoder_in , // 16-bit Input
enable // Enable for the encoder
);
output [3:0] binary_out ;
input enable ;
input [15:0] encoder_in ;

reg [3:0] binary_out ;

always @ (enable or encoder_in)


begin
binary_out = 0;
if (enable) begin
case (encoder_in)
16'h0002 : binary_out = 1;
16'h0004 : binary_out = 2;
16'h0008 : binary_out = 3;
16'h0010 : binary_out = 4;
16'h0020 : binary_out = 5;
16'h0040 : binary_out = 6;
16'h0080 : binary_out = 7;
16'h0100 : binary_out = 8;
16'h0200 : binary_out = 9;
16'h0400 : binary_out = 10;
16'h0800 : binary_out = 11;
16'h1000 : binary_out = 12;
16'h2000 : binary_out = 13;
16'h4000 : binary_out = 14;
16'h8000 : binary_out = 15;
endcase
end
end

endmodule

Example 6 (Decoder using case)


module decoder_using_case (
binary_in , // 4 bit binary input
decoder_out , // 16-bit out
enable // Enable for the decoder
);
input [3:0] binary_in ;
input enable ;
output [15:0] decoder_out ;

reg [15:0] decoder_out ;

always @ (enable or binary_in)


begin
decoder_out = 0;
if (enable) begin
case (binary_in)
4'h0 : decoder_out = 16'h0001;
4'h1 : decoder_out = 16'h0002;
4'h2 : decoder_out = 16'h0004;
4'h3 : decoder_out = 16'h0008;
4'h4 : decoder_out = 16'h0010;
4'h5 : decoder_out = 16'h0020;
4'h6 : decoder_out = 16'h0040;
4'h7 : decoder_out = 16'h0080;
4'h8 : decoder_out = 16'h0100;
4'h9 : decoder_out = 16'h0200;
4'hA : decoder_out = 16'h0400;
4'hB : decoder_out = 16'h0800;
4'hC : decoder_out = 16'h1000;
4'hD : decoder_out = 16'h2000;
4'hE : decoder_out = 16'h4000;
4'hF : decoder_out = 16'h8000;
endcase
end
end

Example 7. (Decoder using assign)


module decoder_using_assign (
binary_in , // 4 bit binary input
decoder_out , // 16-bit out
enable // Enable for the decoder
);
input [3:0] binary_in ;
input enable ;
output [15:0] decoder_out ;

wire [15:0] decoder_out ;

assign decoder_out = (enable) ? (1 << binary_in) : 16'b0 ;

endmodule

Example 8. (Full Adder)


module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;
reg s, Cout;

always @(x or y or Cin)


{Cout, s} = x + y + Cin;

endmodule

Example 9. (ALU)
module alu(s, A, B, F);
input [2:0] s;
input [3:0] A, B;
output [3:0] F;
reg [3:0] F;

always @(s or A or B)
case (s)
0: F = 4'b0000;
1: F = B - A;
2: F = A - B;
3: F = A + B;
4: F = A ^ B;
5: F = A | B;
6: F = A & B;
7: F = 4'b1111;
endcase

endmodule

Example 10. (Comparator)


module compare (A, B, AeqB, AgtB, AltB);
input [3:0] A, B;
output AeqB, AgtB, AltB;
reg AeqB, AgtB, AltB;

always @(A or B)
begin
AeqB = 0;
AgtB = 0;
AltB = 0;
if(A == B)
AeqB = 1;
else if (A > B)
AgtB = 1;
else
AltB = 1;
end

endmodule

Example 11. (Mux)


1.
module mux_using_assign(
din_0 , // Mux first input
din_1 , // Mux Second input
sel , // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel ;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
wire mux_out;
//-------------Code Start-----------------
assign mux_out = (sel) ? din_1 : din_0;

endmodule //End Of Module mux

2. module mux_using_if(
din_0 , // Mux first input
din_1 , // Mux Second input
sel , // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel ;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
reg mux_out;
//-------------Code Starts Here---------
always @ (sel or din_0 or din_1)
begin : MUX
if (sel == 1'b0) begin
mux_out = din_0;
end else begin
mux_out = din_1 ;
end
end

endmodule //End Of Module mux

3.
module mux_using_case(
din_0 , // Mux first input
din_1 , // Mux Second input
sel , // Select input
mux_out // Mux output
);
//-----------Input Ports---------------
input din_0, din_1, sel ;
//-----------Output Ports---------------
output mux_out;
//------------Internal Variables--------
reg mux_out;
//-------------Code Starts Here---------
always @ (sel or din_0 or din_1)
begin : MUX
case(sel )
1'b0 : mux_out = din_0;
1'b1 : mux_out = din_1;
endcase
end

endmodule //End Of Module mux

4.
module mux2to1 (w0, w1, s, f);
input w0, w1, s;
output f;

assign f = s ? w1 : w0;

endmodule

Example 12. (D-flip-flop)


module dff_async_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ;

//-----------Output Ports---------------
output q;

//------------Internal Variables--------
reg q;

//-------------Code Starts Here---------


always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end

endmodule //End Of Module dff_async_reset

Example 13.
module dff_sync_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ;

//-----------Output Ports---------------
output q;

//------------Internal Variables--------
reg q;

//-------------Code Starts Here---------


always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end

endmodule //End Of Module dff_sync_reset

Example 14. (T Flip-flop)


module tff_async_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code Starts Here---------
always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= !q;
end

endmodule //End Of Module tff_async_reset


Example 15.
module tff_sync_reset (
data , // Data Input
clk , // Clock Input
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset ;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code Starts Here---------
always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= !q;
end

endmodule //End Of Module tff_async_reset

Example 16. (D-Latch)


module dlatch_reset (
data , // Data Input
en , // LatchInput
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, en, reset ;

//-----------Output Ports---------------
output q;

//------------Internal Variables--------
reg q;

//-------------Code Starts Here---------


always @ ( en or reset or data)
if (~reset) begin
q <= 1'b0;
end else if (en) begin
q <= data;
end

endmodule //End Of Module dlatch_reset

Example 17. (up Counter)


module up_counter (
out , // Output of the counter
enable , // enable for counter
clk , // clock Input
reset // reset Input
);
//----------Output Ports--------------
output [7:0] out;
//------------Input Ports--------------
input enable, clk, reset;
//------------Internal Variables--------
reg [7:0] out;
//-------------Code Starts Here-------
always @(posedge clk)
if (reset) begin
out <= 8'b0 ;
end else if (enable) begin
out <= out + 1;
end

endmodule

Example 18. (up Down Counter)


module updowncount(R, Clock, L, E, up_down, Q);
parameter n=8;
input [n-1:0] R;
input Clock, L, E, up_down;
output [n-1:0] Q;
reg [n-1:0] Q;
integer direction;

always @(posedge Clock)


begin
if (up_down)
direction = 1;
else
direction = -1;
if (L)
Q <= R;
else if (E)
Q <= Q + direction;
end

endmodule

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