YAMAHA &. Si vsssO E-VDP-III YAMAHANOTICES YAMAHA reserves the right to make changes in specifications in order to improve performance without notice, The application circuit herein are presented only as an example. No responsibility is assumed by YAMAHA for its use nor for any infringe- ments of patents or rights of others which may result from its use. And no. license is granted by implication or otherwise under any patent or patent rights of YAMAHACONTENTS OUTLINE .. FEATURES .... BLOCK DIAGRAN ........ PIN ASSIGNMENT ... PIN DESCRIPTION VIDEO MEMORY CONFIGURATION ... Po INPUT/OUTPUT ‘ACCESS OF REGISTERS R#0 to R¥ 28, R#32 to R#54 ... 10 33 ACCESS OF VRAM 7.3 ACCESS OF PALETTE 7.4 EXECUTION OF COMMAND. 7.5 STATUS PORT .. 7.6 INTERRUPT PORT .. 7.7 SYSTEM CONTROL PORT 7.8 KANJIROM [8] V9990 DISPLAY MODES .. 8.1 PATTERN DISPLAY MODE 8.2 BIT MAP DISPLAY MODE 8.3 REGISTER SETTING VALU! [9] CONTROL OF PALETTE .. 9.1 SELECTION OF DISPLAY TYPE 2 @e@SeB8e CH OI (10) pera OF EACH SCREEN MODE P1 MODE ...... 10.1.1 Display area 10.1.2 Dot clock 10.1.3 Horizontal synchronous frequency : 10.1.4 Correspondence of image space and display area ........ 2910.2 10.3 10.4 10.5 10.1.5 Allotment of screens “A” and “"B” to the front and the rear 10.1.6 Display priority order . 10.1.7 P1 image space 10.1.8 Correspondence of image space and name table 10.1.9 VRAM Pattern name table 10.1.10 Pattern No. maximum value . 10.1.11 P1.VRAM pattern generator table 10.1.12 P1 pattern generator table, bit assign .......... 10.1.13 P1 sprite . 10.1.14 P1 sprite attribute table . 10.1.15 P11 sprite generator table 10.1.16 P1.VRAM MAP P2 mode be 10.2.1. Display area 10.2.2 Dot clock . 10.2.3 Horizontal synchronous frequency - 10.2.4 Correspondence of image space and display area 10.2.5 Display priority order ..... 10.2.6 Correspondence of image space and pattern name table 10.2.7 VRAM pattern name table 10.2.8 Pattern No. maximum value -..... . 10.2.9 P2.VRAM pattern generator table ...... 35 10.2.10 P2 pattern generator table, bit assign 35 10.2.11 P2 sprite .. 10.2.12 P2 sprite attribute table 10.2.13 P2 sprite generator table 10.2.14 P2.VRAM MAP . BT mode wo. 10.3.1 Display area 10.3.2 Dot clock . - oe 10.3.3 Horizontal synchronous frequency 10.3.4 Image space 10.3.5 Number of usable screens .........:000 B2 Mode wo..seessese 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 Number of usable screens B3 mode 10.5.1 10.5.2 10.5.3 10.5.4 10.5.5 Display area Dot clock . os Horizontal synchronous frequency ... Image space ... Display area Dot clock .. Horizontal synchronous frequency Image space ... : Number of usable screensel 10.6 B4 mode ....eseccceene 10.6.1 Display area 10.6.2 Dot clock 10.6.3 Horizontal synchronous frequency 10.6.4 Image space 10.6.5 Number of usable screens 10.7 B5 mode . 10.7.1. Display area . 10.7.2 Dot clock .. = 10.7.3. Horizontal synchronous frequency 10.7.4 Image space 10.7.5 Number of usable screens 10.8 B6 mode 10.8.1. Display area 10.8.2 Dot clock . 10.8.3 Horizontal synchronous frequency - 10.8.4 Image space 10.8.5 Number of usable screens 10.9 VRAM MAP (B1~B6) 10.10 PGT bit assign (B1~B6) : 10.11 VRAM physical address (B1~B6) ..... 10.12 Cursor area bit assign (B1 ~B6) 10.13 Cursor display specifications (B1~ COMMAND 50 11.1 Command execution method .. -- 50 11.2 Parameter setting . .51 11.3. Setting of operation code - 11.4 Command data . 11.5 Outline of commands 11.5.1 LMMC (Logical Move to Memory from CPU) 57 11.5.2 LMMV (Logical Move to Memory from VDP) . . 58 11.5.3 LMCM (Logical Move to CPU from Memory) 59 11.5.4 LMMM (Logical Move to Memory from Memory) .......... 60 11.5.5 CMMC (Character Move to Memory from CPU) .. 61 11.6.6 CMMK (Character Move to Memory from Kanji) 62 11.5.7 CMMM (Character Move to Memory from Memory) ..... 64 11.5.8 BMXL (Byte Move to XY from Linear) . 66 11.5.9 BMLX (Byte Move to Linear from XY) 67 11.5.10 BMLL (Byte Move to Linear from Linear) 11.5.11 LINE 11.5.12 SRCH 11.5.13 POINT 11.56.14 PSET 11.5.15 ADVANCE12] V9990 REGISTER SPECIFICATIONS .............. cocceteeeeee 74 12.1 1/0 PORT SPECIFICATIONS oo T4 12.2 Register specifications 79 13] ELECTRICAL CHARACTERISTICS 13.1 Absolute maximum ratings .. 13.2. Recommended operating conditions 13.3 Electrical characteristics under recommended operating conditions fe 13.3.1 DC characteris ics .. 13.3.2 Terminal capacitance 13.3.3 External input clock timing .. 13.3.4 External output clock timing 13.3.5 CPU-VDP interface .......... 13.3.6 VRAM bus arbitration 13.3.7 VRAM interface 13.3.8 Kanji ROM interface 101 13.3.9 Color bus, synchronous signal output timing . 13.3.10 RGB signal AC characteristics = 101 13.3.1. RGB signal output level ...... 101 13.3.12 Horizontal synchronous signal, display data timing ..... 102 13.3.13 Vertical synchronous signal, display data timing ........ 103 13.3.14 Panel interface timing — 105 14) EXAMPLE OF SYSTEM CONFIGURATION 106 (15) EXAMPLE OF SAMPLE SOFTWARE Commands and application examples Initialization of V9990 Memory transfer .. Screen mode setting . Bit/pixel setting ....... Setting dot number in image space Initialization of color palette WAIT till Vsyne [16] V9990 EVALUATION BOARD . 16.1 V9990 evaluation board 16.2 Connectors on main board 16.3 Switches on interface board ...... [17] DISPLAY FUNCTION FOR YUV, YJK FORM DATA ... .. 107 107 109 109 109 110 110 110 112 113 113 113 2114(1) OUTLINE The V9990 is Having a high-speed @ video display processor (VDP) which features as follows, jag and animation functions, it provides various sereen wodes which can be used widely for games, aut 1 + office automation and other purposes. Also, as a monitor, it supports many types of display units such as home TV sets, CRT for personal computers and liquid crystal panels, FEATURES For this type, two pattern display modes are available as follows. + PI Display resolution 256x212, 2 screens) + P2 Display resolution 512X212) Various highly ad ced functions are available such as powerful sprite funetion and 2-sereen independent omnidirectional scroll function, For this type, four kinds of bit map display modes are available as follows. They are capable of providing display on the NTSC or PAL frequency monitor. +BI (Display resolution 256%212) + B2 Display resolution 384X240) + B3 @isplay resolution 512x212) + BA Display resolution 768X240) Cy ble of doubling the resolution in the verti I direction by using the interlace, ‘#Up to 32,768 colors/dot can be displayed. ‘*Built-in color palette (64 colors selected out of 32,768 colors) ‘* Omnidirectional suooth scrolling is possible, ‘*Superimposition and digitization are possible. ‘*Allows use of the monitor screen to the full extent in four directions as the display range by using the over-scan mode (B2, BA) in such application for the telopper. ‘Supports the high-speed hardware drawing commands such as the screen transfer, font color development and line, The hai re cursor display function is a le.<0A Specifications> For this type, two kinds of bit map display modes are available as follows. They can be displayed on the high resolution monitor. + BS Display resolution 640X400) + B6 (Display resolution 640%480) ‘#Up to 16 colors/dot ct isplayed, (Selectable out of 32,768 colors depending on the color palette) ‘* Omnidirectional suooth scrolling is possible. ‘Supports the high-speed har re drawing commands such as the screen transfer, font color development and line. ‘#The hardware cursor display function is available. ‘Built-in DA converter ‘Linear ROB ou ‘Direct connection of OG ROM such as KANJI ROM is possible. ‘Useable VRAM 6AKX4 128KX8 Dual port DRAM (The access time is 120x8, but 100nS for the BS 256KX4 mode.) ‘As the VRAM capacity, 128KB, 256KB and 512KB configurations are possible. ‘*Capable of direct access from CPU to VRAM by means of the 16 bit bus. ‘Use of the LCD panel (1 screen panel and single drive type of 2 screen panel)3] BLOCK DIAGRAM Lao sna ¥OT09 TaNVd INAS ova WO + INV WV4A aOVANALNI WVAA, i: TaNVd MEA/LOT aLnias AV1dsId WaLLITa it OLYO/OL SOWVANGINI dd naoVes «sw sc5k MODE® MODEL MODE 2 MODE? KAT Kal Kais Kau Kan Kare Kan Kaio Kas VOAB/KAS VOATIKAT VOA6/KAG VOAS/KAS VOAG/KAS VOA2/KA3 YDAD/KA2 VOAL/KAL VDAU/KAD a vop1Ko7 ¥oD6/KD6 Vop5/KD5 vopasKoe Wes ae watt 7 aINTI 126 INTO 2 u vopaykps vopayKb2 VvoDIU/KDI voDovkDa % 36 125 sDREQ 14 eVMREQ 13 Vie KOE 37 ev oRAS 1% avacas 12 cbt Bi cbs 1 Ds hug cpa UV nz cba us D2 us cpt ny bo PvOWE #0 svoTR/OE 41 4| PIN ASSIGNMENT vosc #2 sv 0S0E 8 Vas vos “6 Voss. voss 4 ua MCKIN 2 DLCLK m voss vos3 DHCLK vos? M0 eRESET 109 CB? vost voso 3 Veo 53 los FSCICBS. 107 Vp vis? Vvis6 3 106 eVRESET/CBS 105. SHRESET/CB4 oe SHCK Py 7 * 2° viss visa visa visz visi viso 6 AV IRAS 6 SVICAS 6 103 #BLANK/M 102 ®CSYNC/FLM. oy sHISYNC/LC oo Vs 9 XTAL? 98 XTALI aT Ven % a ® a 6 2 8 3 % 7 cs # a n a 0 @ a 64 Ves Low active Ves B/D 1/CB1 G/p2/cB2 R/D3/c83, AN. #¥S/D0/cB0 Vib? vibe vips vipa Va vips vipz vipt vipo Von via VIAL via2 viag Wes vias vias viat vias SEL, MBG SV 1S0E Vise V1 TR/# OE aViWe(5] PIN DESCRIPTION 1) CPU Interface = 01-0 (1/0) S-bit bidirectional data bus of CPU + MODE3-0 (1) Address for 1/0 port selection of CPU is inputted, Select PEO to PEF of YDP, + #CSR (1) CPU read signal which is chip-selected for VDP is inputted, YDP outputs di to CDI-O when this signal is active (Low). + #C98 (1) CPU write signal which is chip-selected for VDP is inputted, D7-0 data is set to VDP at the rise of this signal. + EMAIT ( pen drain output) Wait signal to CPU is output, This signal becomes active (Lox) while VDP is busy when reading o: + INTL, * INTO (0:Open drain output) These signals becoue active (Lox) when the iting from CPU is executed. terrupt condition exists in VDP, The interrupt condition can be obtained by reading PEG and cancelled by writing " to an interrupt condition corresponding to PEG. INTO is an interrupt for vertical retrace Line interval and at command end. INTL is an interrupt for display position, + #DREQ (0:Open drain output) Data request signal is output, This signal becomes active (Low) when data ready occurs while command is executed and can be cancelled by weans of PI access, +e ViREQ (1) This signal set active(Low) when CPU sakes an access to VRAM without using DP. VOP makes WAIT signal active until VRAM access becones possible, Then it wakes MBG i 1 of VRAMO and VRAMI. After that, it cancels VMBG signal and then WAIT signal, al active and releas data bus, address bus and WE sig 2) VRAM Interface + #KOE (0) Data output enable signal for Kanji ROM is output, The data bus (VOD7-0) is used by both YRAMO and kanji ROM and when this signal is active (Low), kanji ROM data bus becomes valid,+ KAIT-9 0) Address bus (AL7-9) output of Kanji ROM + VOAB-O/KAB-O (0:3 state output) Address bus output of VRAMO, When SKOE is active, kanji ROM address bus output becomes valid, = VIAB-0 (0: Address bus output of VRAMI. = VOD7-0/KD7-0 (1/0) Bidirectional data bus of VRAMO RAM port. When KOE is active, kanji ROM date state output) bus input becomes valid, + VIDI-0 (1/0) Bidirectional data bus of VRAMI RAM por = VOS7-0, VIS7-0 (1) Data bus input of VRAW, VRAMI serial port. + VORAS, #¥IRAS (0) Low address strobe signal output of VRAMO and VRAMI. + #VOCAS, s¥ICAS (0) Column address strobe signal output of VRAMO and VRAMI, + #VONE, sVINE (0:3 state output) Write strobe signal output of VRAMO and VRAMI. + #VOTR/#0B, *VITR/*0E (0) Data transfer control signal of VRAWO and VRAMI or data output enable signal of RAW port, + #VOSC, VISC (0) Serial clock signal output of VRAMO and VRAMI. + #VOSOE, *V1S0E (0) Data enable sig + # MMBC (0) When this signal is active (Lox), VDP releases VRAMO, VRAMI data bus, address 1 of VRAWO and VRAMI serial port. bus and WE signal (resulting in high impedance). + ASEL (0) Low address timing signal for VRAM when making an access to VRAM from outside. 3) CRT and Panel Interface + ¥HSYNC/LC (0) Worizontal synchronous signal output (without equivalent pulse). Panel latch clock signal is output when YDP is in panel mode.+ ®CSYNC/FLM (0) Combined synchronous signal output (with equivalent start signal is output when VDP is in panel node. + BLANK (0) This signal becones active (Low) while retrace line blanking interv AC conversion signal output when VDP is in pane! mode. = SHCK (0) Panel shift clock signal output, +R, G, B #¥S/D3-0/CB3-0 (0) YS sisi panel mode, YS signal becomes active (Low) when VDP date Linear RGB output ut or color bus output 1 output, Panel data ou becones valid when is superimposed. ne aD] + #HRESET/CBA (1/0) Internal horizontal timing is initialized when this signal falls, It ea be used for synchronization when using two ¥9990"s but cannot be used otherwise. when the horizontal cycle differs, normal operation of VDP is not assured. Color bus ov + YRESET/CBS (1/0) ut becones valid when in panel node, Internal vertical t ic is initialized when this signal falls. It is possible to synchronize VDP from outside, Color bus output becomes valid when in pane! ode. + FSC/CBE (0) NTSC subcarrier (3, 58Mllz clock) output, Color bus output becomes valid when in panel mode,= 0B7 (0) Mode PL P2 88/0 48/0 48/0 28/0 28/0 Note) B/D:Bit/Dot, ECC3-0:CC3-0 of even ai Color bus outpi Dot Clock Sil 100, 7, 10H, /SM, 14,21,25MH, 1, LOM, / Ss 14,21,,254Hi, 1, 10M, / SM 4) Clock Signal “XTALL (1), XTAL2 (0) (B7-0 data is output as follows. B7 CBE CBS CBA CBS CBZ _CBI_CBO CB Clock = [= [oes] cca | ocs | cce | oct | cco | pucix = | = [oes] cca | ccs | ccz | oct | cco | picix cr | ccs | ocs | cca | ccs | cce | ci | cco | pic.x/pLcux Becs jecce fkoci jecco pecs [occa fooci DHICL. = | = | = | = Joes | cce | oct | cco | picuxvovcux = | = poet facco | - | - [port focco | picux = | = | = [ct | cco | prcux/pucux ber dot, OCCI-0: CC3-0 of odd aunber dot Terninal for connecting 21Mllx (ACK) crystal oscillator, Use KTALL terminal shen inputting clock oscillated externally. xratt D> KR xtaL2 I+ HHS = WOKIN (1) 14M clock (MCK) is inputted. Use VDP internal register when selecting XTAL or wen, * DNCLK, DLCLK (0) Dot clock output, 1/2MCK for DICLK a 5) Others ‘RESET (1) 1/AWCK for DLCLK. WOP is initialized when this signal is active (Low). All registers (except LWT) will be *AVDD, AVSS (1) ‘Analog power + VDD, VSS (1) Digital power supply i 0” cleared, supply input for RGB.(6] VIDEO MEMORY CONFIGURATION GALX Abit VRANXAchip=128KB (Access time:120ns, but 100ns when in BG node), or 128K XBbit VRAMX2chip=256KB (Access time:120ns, but 100ns when in B6 node), oF ‘256k Abit VRAMX Achip=SIZKB (Access time: 120s, but 100ns when in BG mode) and ards) ‘Mbit kanji ROM (16X16 dots, JIS Primary and Secondary s (Access time: 1502s)7) BASIC INPUT/OUTPUT Data is inputted and output to and from the ¥9990 through the 1/0 ports (PEO to PHF). Basically, as access, both Read and Write are possible at all ports. But only Read with the STATUS port (PES) and Write only with the SYSTEM CONTROL port (P#7)and KANJI ROM LOW ORDER ADDRESS SPECIFYING ports (PH8, PEA). possibl 7.1 ACCESS OF REGISTERS R#0 to R¥28, R#¥32 to R#54 To set a value in the register, have the register No. output at REGISTER SELECT port (PHA) and then the data at REGISTER DATA port (P#3). To obtain the value from the register, have the register No. outpi read PHB. at PEA and then The register No. is specified by using the lower 6 bits of the value at P#4 and the bit 7 (USB) functions as WII (Write Increment Inhibit) and bit 6 as RIT (Read Increment Tohibit), 1 WIT is “1 + automatic increment of the register No. by writing the data to the register is prohibited, If RII is ‘I”, automatic increment of the register No, by reading the data of the register is prohibited. b7_b6 65 bd BSB PHAWrite) NUTRI] Register No. BN P#3(Read/Mrite) Register date 7.2 ACCESS OF VRAM To write a value in VRAM, set the target address to VRAM Write Base Address registers (RIO~ RA2)and have the data output at VRAM DATA port (PHO). As the bit 7 (MSB) of RAZ functions as AIL (Address Increment Inhibit), if it is ‘I, automatic address increment by writing the data is inhibited, To read the data of VRAM, set the target address to VRAM Read Base Address registers (RI3~ RES)and read in the data of VRAM DATA port (P#0). As the bit 7 (SB) of RES functions as AIL (Address Increment Inhibit), if it is ‘I, automatic the data is inhibited, dress increment by reading in ‘The address can be specified up to 19 bits (512K bytes), with lower 8 bits set to RIO (or RES). conter 8 bits to REI (or REA) and upper 3 bits to REZ (or RES). @VRAM Write br 6 oS bd SBD p#aqrite) [oToTo[ToyTo][olo|lo P#3Write) VRAM Tower address (RHO set) WwWbr 6 BS bh OS bbb P#Irite) VRAM center address (RH set) Pa#srite) [arr VRAM upper address @N set) P#O(Write) Data @VRAM Read b7 b6 65 MM obS BO Peart) [oTofo[o[ofojifi PH#Srite) VRAM lower address (RES set) PHI (rite) VRAM center address (RH set) P#sqrite) [att VRAM upper address (RES set) P #O(Read) Data 7.3. ACCESS OF PALETTE The palette data can be set or checked by setting the palette No, and RGB specification to the palette pointer (RFA) and reading or writing at the palette data port (PEI). The palette No, is specified by using the upper 6 bits of RFI4 and RGB by using the lower 2 bits QO, G=1, B-2), The lower 2 bits constitute a ternary counter which undergoes automatic increment in the order of RGB through the port access. It should be noted that how the palette setting is actually displayed also depends on the palette control register (REI3) setting. ae paawrite) [oTolofo[ijijifo P #3 (Write) Palette No. 0 | 0 ] aa sev) P #1 (Write) -[F- RED dai p#i@rite) [= [- [- GREEN data p#idritey) [= [= [= BLUE data es7.4 EXECUTION OF COMMAND With the necessary parameter set to the command registers, set the operation cod u rt (PH2) by the Por fer from CPU (or to CPU), the data is output at the command data amount required after this stage. 7.5 STATUS PORT Only by reading the status port (PES, Read Only), the status of the V9990 can be checked. 7.6 INTERRUPT PORT ‘The cause of interrupt can be determined by reading the interrupt port (P46). As the flag. is not reset automatically, should be written to the applicable bit to reset it, ‘The system control port (PE) is only for writing. It can be used to reset the systen and to select the master clock, 7.8 KANJI ROM The kanji font can be obtained in the same manner as the SX kanji ROM Por the primary standard kanji, have the upper address output at P#9 and the lower address at PHB and obtain the font data by reading in PHY 32 times. For the secondary standard kan The di use PEA and PEB in the same way. a is provided in the -der of upper left, upper right, lower left and lower right blocks (8 bytes each) of the 16X16 font. Ist tnd Boytes | Sbytes Font : 16 dots verticalx16 dots horizontal 3rd ath Bbytes | Bbytes br 6 BS bd O32 BB P#9rite) [= [= Font upper address P#sqritey (2 [— Font lover address P #9(Read) Data9990 DISPLAY MODES 8.1 PATTERN DISPLAY MODE displayed colors Mode nane PL P2 Master clock frequency | 21.9MHz 21, SMH - | Dot clock frequency | _5.4MHz _ Horizontal cycle 15,.7KHz (NTSC “15.7KHz (NTSC) | Display resolution 32X26,5 patterns 64X26,5 patterns (256x212 dots) (512x212 dots) Number of screens 2 screens I screen Pattern size Bx8 dots 8X8 dots Simultaneously 18 colors + clear color 15 colors + clear color Color palette ‘4 palettes of 16 colors out | 4 palettes of 16 colors out terns of 32768 clors of 32768 colors tern aa ~ 1 Display space 3226.5 patterns 64X26.5 patterns Image space | 64x64 patterns 128X64 patterns Number of selected | 16384 patterns (Max.) 16384 patterns (Max.) Pattern generator 2 sereens independently 1535units (VRAML28Kbyte) BOTLunits (VRAMI28Kby te) ‘S58Sunits (VRAMZSEKEy te) TU6Tunits (VRAM2S6Kbyte) ‘T6T9units (VRAMSI2Ky te) 15859units (VRAMSL2Kbyte) #) AIL items except No, Sprite Display Function + Size + Limited No, of displayed w 1 Displayed colors + Specification of display pri ity + Pattern of pattern generators are irrelevant to the VRAM capacity. 16x16 dots 125 in | sereen 16 on I Line 15 colors + clear color (for each dot) Palette can be selected for each sprite (I palette selected out of 4) Priority between sprite and pattern screen can be set for each sprite. The sprite No. order is used for priority order among sprites. Selected from among 256 patterns The pattern generators are used commonly with the pattern screen (the base address should be set at the register RAZ5.) =8.2 BIT MAP DISPLAY MODE Bit map screen display function VRAM 128Kbyte Master ]Dot | Horizontal | Display Number of Woéd clock | clock eyele| resolution| displayed | Image size ( Dimterlacg colors (aotz) | ix) | Geils) | Gorxdot) | it/aot) | (dotxdor) 16 256x256 256x512 § 512x256 ntsc 256x1024 Bi} 2s | 54] 15.7 256x212 4 512x512 (256x424) 1024x256 256x2048, 2 s12x1024 1024x512 2048x256 8 512x256 NTsc | OVER SCAN 5124512 pe} as | 72] 15.7 384x240 ‘ 1024x256 (384x480) ‘s1ax1024 2 1024x512 2048x256, 8 512x256 Ntsc 512x512 ps} 2.5 | 107 | 15,7 512x212 ‘ 1024x256 (s1axana) ‘s12x1024 2 1024x512 2048x256 ntsc | OVER SCAN 4 1024x256 Bay 4s | 14s | 15.7 768x240 1024x512 (768x480) , 2048x256 Bs| 2s | 2s | 25.3 640x400 2 1024x512 Be | 25.2 | 25.2 | 31.5 640x480 2 1024x512 —u-VRAM 256Kbyte Waster [Dot [Horizontal | Display | Wunber of elock| clock| eyele| resolution| displayed| Iuage size ( Dinterlaed colors cis) | cay | cra) | Gdorxdo) | Gitveor) | Caoexaon) 256x512 6 512x256 as6xi024 8 sinxsi2 1024x256 Ntsc 756x2048 mi} ans | sa} ast | ase 4 siaxi024 (as6xa24) o2axsi2 20481256 75634096 2 512x2048 ozaxi074 2048x512 16 S12K256 : 512x512 102x256 s1xi024 wise | ovER scan 4 lozaxsi2 pe} a3 | 12] 157 | sean 2048x256 (384x440) 512%2048 2 ronaxiord 2048x512 6 512x256 : B12xS12 024x256 siaxi02 Ntsc 4 ozaxsi2 ws} ans | i7 | 17 | sieae 20481256 Gia) 5122048 2 rozaxior4 2048x512 1 o2axsi2, ntsc | over scan 2048x256 we} as | as | ts.7 | to8xza0 : To2axio2a (as8x480) 2048x512 a o2axsi2 Bs} 2s | as | 25.3 | s4oxs00 o2axi024 2 204gxs12 4 02x52 Be} 25.2 | 25.2] ais | s4oxsso , To2axi024 2048x512VRAM 512Kbyte Mods Waster clock (atts) Dot clock (ais) Worizoatal | Display eyel atts) ( Dime G@orxdot) Wunber of displayed colors (it/dou) Inage size G@orxdot) 25 5.4 15,7 16 ‘D56K1024 512x512 1024x256 256x212 (256x424) ‘256x2048, 512x1024 1024x512 2048x256 7256x4096 51242048, roz4x1024 2048x512 25648192 512x4096 1024x2048 2048x1024 4.3 1.2 wrsc 18.7 ‘S12K512 1024x256 OVER SCAN 384x240 (384x480) 512x1024 1024x512 2048x256 ‘51242048 tozaxi024 2048x512 ‘512x4096 1024x2048 2oasx1024 25 10.7 NTSC 15.7 ‘512x512 1024x256 ‘ST2K102E 1024x512 2048x256 512x212 (s12xa24) 51252048 1024x1024 2048x512 512x409 1024x2048 2048x1024 43 M3 Tse 15.7 OVER SCAN Yo2Ax1024 2048x512 768x240 (768x480) T024x2048 2048x1024 BS 1.5 215 25.3 640x400 1O24x1024 2048x512 124x204 2048x1024 25,2 318 640x480 TOzAx1024 2048x512 T0z4x2048 2048x1024 —16—Displayed color (RGB conversion systes) PLM Number of ROB conversion systew (eh) displayed color Direct ROB Isbit/éor ° 32768 colors (YS: 1bit, G:Sbit, R:Sbit, B:Sbit) 0 | Color Palette 64 colors ov of 32768 colors Direct RGB 1 256 colors sbit/dor GG:3bit, ReSbit, B=2dIL) | 2 | YAK Decoder [19268 colors 3_| WV Decoder 19268 colors 16 colors out abit/dor 0 | Color Palette | of 32768 colors lo 4 colors out Bit/éor 0 | Color Palette of 32768 colors Cursor function + Size Number of displayed uni Displayed color + Pattern 32X32 dots ts Din 1 sereen 3 colors + BOR color on b Any form it map screen + clear color 8.3 REGISTER SETTING VALUES FOR EACH DISPLAY MODE Pn RS mn Mode ucs | ospu | pcx | xia] cirw| czsu| sur] sw | ra| eo | mL | sow rfol of of 1] af of of ol onl ol on| o mfol 1{ a] 2] af of of onl on| ol on| o nfo} 2] o| os] os} o| on] oa] om] on| on| o | we} 1] 2) 1] 3} 03) 0 | on} on| om} o1| o1| 0 w/o] 2) 1] 18) 08) 0 | on} on} o| o| | o wl} 1|] 2] 2] 23] 01) 0 | on] on| on] on| on] o Bs} o] 2] 2) 23/01] of of of of o| of 1 ws}o] 2] 2] x3] on o} of] of oj 4 =[9] CONTROL OF PALETTE For the ¥9990, there are 10 types (display types) by which the data (2 to 16 bits) obtained from VRAM is transmitted to the D/A converter with 5 bits for each RGB as follows. 1, PP Display type when the display mode is Pl or P2 2, BYUV Display type when the display uses full YUV on the bit map 3. BYUVP Di xy type when the display mode uses YUV and palette mixed on the bit map 4. BYIK Display type when the display mode uses full YJK on the bit map 5. BYJKP Display type when ode uses YJK and palette mixed ov the bit mp 6. BD16 Display type when the display mode uses 16 bit data directly on the bit map (5 bits for each ROB+Ys) 7. BD8 Display type when the display mode uses 8 bit data directly on the bit map (3, 3, 2 bits for each RGB, Ys at ALL 0) 8. BPG Display type when the display mode uses 8 bit data on the bit wap through the palette 9. BPA Display type when the display mode uses 4 bit data and offset 2 bits on the bit map through the palette. 10. BP2 Display type when the display mode uses 2 bit data and offset 4 bits on the bit mp through the palette, —18—9.1 SELECTION OF DISPLAY TYPE PALETTE CONTROL (WRITE ONLY) yl ratis[ Pim | pLmMo | vaz | PLTAIH| PLT0S | PLTO4 | PLTO3 | PLTO2 SPRITE PALETTE CONTROL (WRITE ONLY) eS mt res[ 0 ° 0 0 _[csros | cspos | csPos | csPoz BACK DROP COLOR (READ/WRITE) eS Sl rais[_o 0 | pocs | poca | pocs | BoC? | BOC! | BOCO ‘SCREEN MODE (READ/WRITE) yf rat 6[_pseui] psewo] poxwi] poxwo] xii] xtwwo] curwi | CLRMo sew | Puiu | cLRu | YAE cre fot @arw | 2 ()ByUvP ays ()BYIKP pois (708 Or (gyre (10) P2. —w-9.1.1 PP YS PALETTE wa {ca res L 63 SPAT REIS Rais por} o2 ses [{ ruts }{ pocs [ras roiyor P60} co }-oREEN sca 1] purz [} soca LH pm Pra Ly Ra as | 3 LH 1 noes Las prety R2 DAC FRED spor rer pei Hy RI data} ae pcr, Lp Pro | no Peat} Ba BLUE H HH oct HY pat as | Bs ps2 L Be T{_soco_f{ Pao Pai} Bt Pao | 0 Back drop plane Pattern plane Sprite plane = PLT3 and 2 will be as follows depending on display modes. PLT PLZ PI aode, plave “A” | mts | pto2 PI node, plane “B” 7 puTos | PLO P2 wode, 82 plus 0, 1, 4, 5th dot pitos | PLO P2 mode, 82 plus 2, 3, 6, 7th dot PLTOS PLTOA + SCS and 4 are data of sprite attribute table + POT data is data of pattern generator table “SPGT data is data of sprite generator table (used commonly with pattern generator table) 209.1.2 BYUV 7S PALETTE SELECTOR YS SPAT Ras esros. }{ pocs } pas P04 SPGO-4 FY coe LG csroa F-} Boca} PM csros. +4 Bocs L) pas PRO-A spro-4 |} 0-4 csroz +4 pocz [Par ect +4 ppc. HPAL PBO-4 SPBO-4 FY BOA |B cco +4 poco} pao CURSOR BACK DROP. WK wi 4 Yoo-4 svCo-4 vos 3 vs n vot at yro-4 }}H S¥R0-4 vos yo woe ce yoo-4 4 sypo-4 voi cl yoo co BIT MAP = CCL and CCO are data of cursor attribute table,9.1.3 BYUVP PALETTE SELECTOR Ws Ras SPAT Reis putas LY cspos }{ eocs |} pas 60-4 spco-4 LY Goa LG PLTO4 +4 cspos L{ Boca [4 PM vor +} csros +4 pocs. 1] pas PRO-4 spro-s— }] ROA 4 vos =|} cspoz +) ocr + par vos +} ccl 4 oct {Pai PBO-4 spBO-4 FY BOA FB vos _}{ cco +4 poco || pao BIT MAP CURSOR BACK DROP (HEN YD8=1) YK wor 4 Yoo-4 syco-4 vos ¥3 vos va vo a wRO-4 FY S1R0-4 v3. ‘oJ vo won ce yeo-4 YY sypo-4 vol 1 yoo co BIT MAP (WHEN. VD3=0) + CCI and COD are data of cursor atti9.1.4 BYJK PALETTE, SELECTOR PYS SPAT Rais csros }-{ ppcs PAS. PCo-4 spco-4 =F} co-4 [-o cspos +4 pce PAA cspos. +4 pcs PAS spro-4 4 «ro-s LR csroz [4 Boce PAD ect =} poet PAL PBO-4 sppo-4 = |} Bo-s LB cco $4 _Boco PAO CURSOR BACK DROP VK vor 71 yoo-4 syco-4 vos 3 vos v2 vba " YRO-4 SyRO-4 vb3 Yo voz ce YBO-4 SYBO-4 voi cl vbo co. BIT MAP + CCI and COO are data of cursor attribute table,9.1.5 BYJKP PALETTE, SELECTOR WS RH3 SPAT Ras puros }{ cspos }{ pcs | Pas PoO-4 SPoO-4 FY 60-4 FG pLtoa +4 cspoa +) poce [4 pat wor} cspos fy pocs. +} pas PRO-4 spro-4 HY Ro LR wos |} csroz +4 pocz + rar ws +{ cc H{ poct [rar PBO-4 1] Boa vor +4 cco 4 poco |} pao BIT WAP CURSOR BACK DROP. (WIEN. ¥D3=1) viK wor ry yoo-4 + s¥co-4 vos 3 wos wm vos " yRo-4 }— srro-4 v3 vo cr YBo-4 |— s¥B0-4 wl a yoo co BIT WAP (HEN vD3=0) “CCL and CCO are data of cursor attribute table, 29.1.6 BD16 PALETTE ‘SELECTOR PYS SPYS YS, SPAT RAS cspos }-y spcs | Pas PCO-4 ‘SPGO-4 ee cspod +) BDca PAA csPos pcs |] PAS PRO-4 SPRO-4 I cspoz }-j soc2 | Par cer = -4 Bpcl ++} Pal PBO-4 ‘SPBO-4 [+] Bo-4 cco }-{_Bpco PAO CURSOR BACK DROP DIS Svs vous syca vo13 syc3 voi2 sya voit syG1 vp10 syco yoo syr4 vos SyR3 vor syR2 vos syRI vos syRO v4 SYA vb syB3 voz syB2 vol SYBI yoo SYBO BIT WAP + CCI and COO are data of cursor attribute table,9.1.7 BD8 PALETTE ‘SELECTOR Ws PS SPAT. REIS csPOs BDCS 4 PAS. PCO-4 spco-4 | co-4 csro4 soce | pad csro3, socs + pas. PRO-4 spro-4 |} 0-4 csroz Bocz | Paz ect }4 sper | par PBO-4 sppo-4 [4 Bo-4 cco }{_spco_} pao CURSOR BACK DROP ‘SYS v7 syca vos sycs vos syca syci syco WHEN VDO~VD7= ALLO vba syR4 vb3 SYR3 voz syR2 vos syri vps syRO voi SyBA yoo SYBS syB2 SyBI SYBO oR + CCI and COO are data of cursor attribute table, 2% -9.1.8 BP6 PALETTE vor PS |} 1s roa Lf oa vos Pos |} 63 SPAT REIS PG2 | G2 csP0s vos Bos fy PAs PCL L- GL roo |} co [-OREEN cspo4 vo4 poce }4 pa pRa LY Ra prs L] ka csPos vs pocs }yras = pRzt-]R2 AC L-RED pri Let cseor |) v2 soce | paz RO RO pea LY Ba [BLUE cor }Y wi poct, |4rar pes L183 PB2 | B2 cco }{ woo poco }4 rao PBI} BI CURSOR «BIT MAP BACK DROP po | Bo = CCl and CCO are data of cursor attribute tal 9.1.9 BP4 PALETTE is 45 roa Lf oa ros |} ¢3 SPAT REIS RES PC2 FG? esros FY pit0s }{—ancs Tras rei [fcr Poo |} co Loreen csros |4 putoa [4 spce ft) ra Prat ea PRS RS csros vos socs [4 pas pR2 yk? aC L-RED pri Lei SPO? vD2 BDC2 — F-} PAZ PRO [—~ RO pea L wa [BLUE cc yDI f{ BDCl |; PAL PBS | B3 pz |} B2 cco f+1__Ybo -_Boco PAO PBL TBI CURSOR BIT MAP BACK DROP PBO }~{ BO + CCI and CCO are data of cursor attribute table, Note: When setting the color palette data in the BA, B5 and BG modes, we value for each corresponding pair of palette ase the si addresses 0 to 31 and 32 to 63, that is, 0 and 32, 1 and 33 and so on, 29.1.10 BP2 PALETTE Ps H—____——_¥5 pa toa Pcs | ¢3 SPAT REI3 Rais Po | cr esros }-{ PLT0s BDCS |] PAS Pci fy G1 Pco | co [-CREEN cspoa |} PLto4 soca |] Pad PR4 fy RA PRS [4 RS. cspos. [4 pitos Bocs | PA3 PR2 LY RD pac |-RED Pri f rt espoz | PLtoz pc? PAR PRO} RO pba +4 Ba [BLUE cet voi soci | Par PB3 [-y 83 pB2 [4 82 cco yoo Bpco [+ PAO PBI fy BL CURSOR BIT WAP BACK DROP PBO }-+{ BO + CCI and CCO are data of cursor attribute table, Note: When setting the color lette dai in the BA, B5 and BG modes, use the same value for each corresponding pair of palette addresses 0 to 31 and 32 to 63, that is, 0 and 32, 1 and 38 and so on,DETAILS OF EACH SCREEN MODE 10.1 P1 MODE 10.1.1 Display area 0 255 When B0-0 Impossible when BOL an 10.1.2 Dot clock MSC=O DCKM=0 = 5, 4M, 10.1.3. Horizontal synchronous frequency HSCN=0 15,7 10.1.4 Correspondence of image space and display area The display start point (by dot) in the image space can be selected freely by using the seroll control register A (REIT to 20) for the sereen “AT and the scroll control register B (RE2L to 24) for the sereen “B. 10.1.5 Allotment of screens ‘A’’ and ‘’B' The priority control register (R#27) is used, PRKL,PRKO On the right side of the X co-ordinate specified by these to the front and the rear ts, the front is ‘BY and the rear is “A”. PRYL,PRYO On the lower side of the Y co-ordinate specifi by these bits, the front is ‘B" and the rear is ‘AT. For the area where the above conditions are not met, the front is ‘A" and the rear is Br When PRII=0 and PRXO=0, and PRYI=O and PRYO-O, the front is ‘A” through the whole arca, 10203 0 (PRX) 64_128 192 256 (DOT) 1 «(AlATB[B 2 el AlA[B[B 3 12/2] 8[ BIB 0 2218/8] 8] ain PRY) (007) Gxanple) When PRKI=1, PRXO=0 and PRYI=1, PRYO=0 2910.1.6 Display priority order (Wiewed)> Sprite Front Sprite Rear Border Superiapose PRI-0 Cor’) oP (A or B) PRO-O PRO-O prite (PRO-I) is not displayed. 10.1.7 P1 image space 0 256 512086 512 25 2 51 5h Seren ‘Screen “B” 10.1.8 Correspondence of image space and name table Bach image space in screen ‘A” and screen Of which is 8X8 dots (16 colors/éot). B” consists of 4096 (64X64) patterns each unit To each one of O to 4095 patterns on screen ‘A” and screen “B", 2 bytes on the pattern name table are assigned and by neans of the value (pattern No.) to be written here, the font on the pattern generator table car be selected, 0 8 504 sll 0 8 504511 [20 [leer [a BO | BI- B63 3f— N64 a7 BA Bi27 504 =} 504 | = _ M4032, ‘M095 4032 84094 | 84095 su si —30—10.1.9 VRAM Pattern name table e000 [AO (Ow) ‘e001 [AO (HIGH) ‘oer | 44035 (HIGH) e000 | 80 (LO) ‘Teeer [84095 (HIGH) 10.1.10 Pattern No. maximum value RAM | Screen “A” | Screen B” rex | 2015 1535__| 256K | 4063, 3583 sik] 8159 7619 10.1.11 P1.VRAM pattern generator table Screen A pattern generator table oowaa | = 3t Ae rn orsoo} —__:_| crane) ATSEA~A201S | vanizax F800} vrere [G2 AVOBE | vase rt) sary LABI20~ABTED | VRAMSI2K Screen B pattern generator table ‘VRAMI28K 10000), 40400 Py eee 000) Fi504~B1535 “arFr e100 bled cco 00 gaa ~BI679 Tore 10.1.12 P1 pattern generator table, bit assign wnoro ont cor =] ef on ot i 10.1.13 P1 sprite fo~As1, LIND oy fo~sstsLiner 000 00002 a so~asi,Liner ent 482~A68, LINED ovo7F o008o VRAM256K WRAMSI2K configuration is based on 256 dots (4bits/dot) in the X direction, +The sprite size of 16X16 dots can be used up to 125 pieces. +The lower 4 bits of the palette address belong to 1 dot of the s 2 bits to 1 spri te d 64 colors (16 colors on one sprite) can be used 5: = 16543210 PCO PCL PC? PCS PCA PCS PCé PCT PCO PCL P6 PCr PCO PCI 1sB ‘AO LINEO AL Lingo ASI LINEO ‘AO LINEL ite and the upper jultancous ly.“Up to 16 sprites can be displayed on one horizontal line, (The smaller the sprite No. is, the higher priority the sprite has.) +The priority between the sprite and pattern screens (front and rear) can be specified. ) (The priority is higher when on the horizontal lin 10.1.14 P1 sprite attribute table br D6 SS aren, [30 3#t00 [S017 SOYE SOYS SOYA SOYS SOT? SOY! _SOY0] Y co-ordinate ‘reos LEE ‘3REO1 | SOP7 SOP6 SOP5 SOP4 OPS SOP2 SOPI_SOPO | Pattern No. 37602 | SOXT SOX6 SOS SOKA SOK3 S012 _SOKI SOKO] x co-ordinate == tional i SOAS SHE avin FFF “Co-ordinates space 0,0) Display area (255,211) (1023255) Both X and ¥ co-ordinate spaces roll in this size, The vertical display position is the specified ¥ co-ordinate plus “I”. Displayed color Palette Address AS A4__A3_A2 Al AO SCS[SC4] SGT data Clear color when SGT data are all + Display priority order PR1|PRO|_ Priority order ite plane o 0 | SP>A>B>BD |A :Froat 1 0 | A>SP>B>BD |B :Rear = 1 | A>B>BD BD:Back drop pla Sprite is not displayed when PRO=1. 10.1.15 P1 sprite generator table ‘*The baz js (SCBA) is specified with R#25, « ws 76 5 4.3.2 1 0 ISB 00000 rsp=s15 sHnUeo [LINED] so~S1s,L1NBO —s00000 [ — S00 SCL +007FF eaieg[EINEL] S0~S15, LINEL 0 LINEO i 00007 | sore ser Storey EINETG S0~S15,LINEIS 00008 | sco scl | $i Lines LINBO | S16~S31 LINED -soo07F | Scia Scis_| S15 LINEO #00080 ‘SCO ‘SCI ‘SO LINET 3210.1.16 P1.VRAM MAP 00000 0000 POT)SOT 00000 scr ADScT POTO)SOT onr ur ; SR ; SPOT Spat sear S00 Spat 4000 00 PT®) (0000 rer @) 1000) pcr@) se suPFie 000 7 too 7 too veeod AD veo OD FAT) near) reer) 12007 par wy RAW 128K van 256K TAPP Via 512K +The physical address of VRAM is divided at the uppermost bit of the logical addre 0: VRAMO Uppermost bit=1:VRAML Uppernost bi —2-10.2 P2 mode 10.2.1 Display area su When B0-0 Inpossible when EO=1 au 10.2.2 Dot clock SC=0 DCKM=1 : 10, Tile 10.2.3. Horizontal synchronous frequency HSCH-O = 15,7Klz 10.2.4 Correspondence of image space and display area The display start point (by dot) in the image space can be selected freely by using the scroll control register A (REIT to 20), 10.2.5 Display priority order Wiewed) > | Sprite Image plane Sprite Border Superiapose PRI-0 PRI-0 PRO-0 PRO-O + Sprite (PRO=1) is not displayed. 10.2.6 Correspondence of image space and pattern name table The image space consists of 8192 (128X128) patterns cach unit of which is 8X8 dots (16 colors/éot). To each one of 0 to 8191 patterns, 2 bytes on the pattern nane table are assinged and by weans of the value (pattern No.) to be written here, the font on the pattern generator 8 1008 1023 0. 62 | PART PI28 P2S5 504 su P8064 | PBO6S- P8190 | P8191 =e10.2.7 VRAM pattern name table e000 [PO (Low) e001 | PO (HIGH) eeer [ P8191 (HIGH) 10.2.8 Pattern No. maximum value Vea 128K | 3071 | 256K | 1167 51K | 15359 “Maximum value that can be written into the pattern generator table. 10.2.9 P2.VRAM pattern generator table Pattern generator table 000 po Fes 00800 pee—PIRT oorr sre00}|——_-_| veer P8008 PHOT | vn2sK s1800} ——___| Sane PriOA~Pri7_| veawnsex m1800 77 [Pisaa6-—P16369 | veawst2K 10.2.10 P2 pattern generator table, bit assign The bit map configuration is based on 512 dots (Abits, jot) in the X direction, oie oer] 90 Tr] roman non HB, TESA SZ LO Ist Tie ere. ono coon: [Perro] ro neo ‘00002 | Pcs] PCS ‘0000s | pce | PCT 000s | po | PCL Pr LiNEO 00700 oo7FF LINET | PO~P63,LINET LINBO | P64~P128, LINEO ooorr {Pcs | PCT P63 LINBO oo100 | pco | PCr PO LINE:10.2.11 P2 sprite = The sprite size of 16X16 dots can be used up to 125 pieces. The lover 4 bits of the palette address belong to 1 dot of the sprite and the upper 2 bits to I sprite and 64 colors (16 colors on one sprite) can be used simultancously. “Up to 16 sprites can be displayed on one horizontal line. (The smaller the sprite No. is, the higher priority the sprite has.) 10.2.12 P2 sprite attribute table br 6 SAS TBEOO, penal SP0_] 7800 [Sor7 sove sovs sora sors _sov2_sov1_sov0| ¥ co-ord ppeoglS?!_| 7e01 | Sor7 _sor6 sos soP4 sors_sor” _SOP1_SOP0 | Pattere No. tpk02 | SOX? SOX6 SOKS SOK SOX3 SOX2 SOX1 SOKO | X co-ordinate = 0X8 | Additional oo mpeos| cs SCA PRI PRO SOX9_SOx8 | Addit Tnforastion roves 4 + Co-ordinate space (0,0) Display area (511,211) £(1023,255) Both X and Y co-ordinate spaces role in this size. The vertical dil y position is the specified Y co-ordinate plus 1. ‘Displayed color Palette Address AS AAAS ADL AD scs|sc4 SGT data Clear color when SGT data are all + Display priority order PR1[PRO| Priority order | SP:Sprite plan © [ 0 [SP>A>BD__ |A=Image plane 1 0 [A>SP>BD__| Bo:Back drop plane = | 1 [a>pp | Sprite is not displayed when PRO=1. 36 —10.2.13 P2 sprite generator table ‘The base addres: (SCBA) +0000 +0000 S0~S31 LINEO #01000 #00100 LINEL #00200 +0000 LINEIS +0100 LINEO +The sa s specified with RI25. S0~S31,LINEO S0~S31,LINEL S0~S31,LINEIS $32~S63, LINEO = #00000 +0007 00008 +s000F we7 6 543210 3c ser seu | scis 3c set scld SC15 sco set #00100 's commonly used with the pattern generator table, 1sB SO LINEO SI LINED S31 LINEO $0 LINE10.2.14 P2.VRAM MAP 000 0000 0000 PGT SPT POT SPOT POT SPCT 10004 10004 10004 mE 20006 20004 20004 30006 3000 3000 i ‘STFFI 40000 40008 40000) 50000, 50006, s000q) 60000, 60000 6000 Too0d T0008 To00q TRRR TBO ‘TeB0 SPAT SPAT TO Seat 700 re 10000) PAT PAT PAT FFF THF ‘TFRF VRAM 128K VRAM 256K ‘VRAM 512K + Physical address of VRAM SPAT VRAMO PRT YRAMI10.3 B1 mode 10.3.1 Display area ° 255 When 20-0 aul o 255 When IL-1 and BO-1 aa 10.3.2 Dot clock WCS=0 DCKWEO : 5 Alls 10.3.3 Horizontal synchronous frequency HSCN-O + 15. 7Kily 10.3.4 Image space 0 256 5121024 2047 | K T % | x 256 512 1024 2048 4095 8191 3910.3.5 Number of usable screens Supposing that 1 screen consists of 256X256 dots: (coon), 16 8 4 2 ITO cunt [ 1 [1] 0] 0] Xi KIM = Number of dots in X direction in cm [1 [ol] o imuge space selected trax) | VSL1 | ¥sLO 11 = 2048 dots sim [1 [oo | 4 [8 (a6 [32 10 = 1024 dots aox [oo |i | 2 fea | 8 | t6 0 1s Bit dots3K wax [ojo |i{[z|ale o 0 256 dots cevTe) Nunber of dots in Y direction is automatically calculated fro the above 6 bits, 3 (Example) Image space when CLRMI=1,CLRMO-O VSLI=O,VSLO=1 XIMI=0,X 1M10.4 B2 mode 10.4.1 Display area With over scan applied ° 383 When B0-0 2a_] o 383 When Il-1 and BO-1 a 10.4.2 Dot clock WCS=1 DCKMEL = 7, 24H 10.4.3 Horizontal synchronous frequency HSCN-O + 15, 7KHle 10.4.4 Image space 0 512 10242047 K K 156] 512 024] oath 4095 10.4.5 Number of usable screens Supposing that 1 screen consists of 512X256 dots : (COLOR) 16 84 2 (BIT/voT) CLR TT 1] 0] 0] XI XIMWO : Nuwber of dots in X direction in cur | i] of | o image space selected (wrany | ¥sit [ Vsti I roa 2048 dots six [a | o[ 2] af 8) 6 10 = 1024 dots ack {0 [1] t[sel a] 8 o 4 512 dots wax [o [oo] of] 1] 2] 4] — Nanber of dots in ¥ direction is automatically corre) ealeulated from the above 6 bits. 3 Example) Image jee when CLRMI=1,CLRWO-O VSLI-0,VSLO=1 X1MM1=0,X1MM0=1, ee10.5 B3 mode 10.5.1 Display area 0 su When E0-0 at o su When Il-I and BO-1 a3 10.5.2 Dot clock WCS=0 DCKWE1 : 10. 7A 10.5.3. Horizontal synchronous frequency ‘HSCN=O : 15, 7KHs 10.5.4 Image space 0 siz 1074 2047 156 By Eq % tom 2047 4095 10.5.5 Number of usable screens Supposing that 1 screen consists of 512X256 dots: (coon) 16 842 BIT/DOT) CURT TT 1] 0] 0] Xt Xiwwo : Number of dots in X direction im coro | 1) of 1] 0 image space selected rang | ¥sut [ VSu 1 2048 dots sim [1 [o | 2] «| 8] 1 a) 1024 dots asx [0 [1 | i[mel af 8 o 1 512 dots wax To [ol of 1] 2] 4] — Number of dots in ¥ direction is automatically rm) ealeulated from the above 6 bits. 2 (Example) Image space when CLRMI=1,CLRMO-0 VSLI-0,VSLO=1 XIMMI=0,X1MM0=1, —2-10.6 B4 mode 10.6.1 Display area OVER SCAN 0 167 Then B0-0 2391 0 161 When II and BO-1 a 10.6.2 Dot clock WCS=1 DCKWE2 = 14, 3M 10.6.3. Horizontal synchronous frequency HSCH-O = 15.7, 10.6.4 Image space 0 1024 2047 % % 156 512 1024 2047 10.6.5 Number of usable screens Supposing that 1 screen consists of 1024X256 dots: (coon) 42 (BiT/vor) CiRMt [OT 0] XI XIMMO : Number of dots in X direction in image cinw [1] 0 space selected (wean) | VSLI ] VSL 11: 2048 dots sim | [0 8] 1 0: 1024 dots 3% aso [0 [1 [oe] 4 wax [o [o 2] Number of dots in ¥ direction is automatically calculated rm) from the above 6 bi 3K (Example) Image space when CLRMI=0,CLRMO=1 YSLI-0,VSLO=1 X1MMI=1,XIMMO=0, Note: When setting the color palette data, use the same value for each correspondi palette addresses 0 to 31 and 32 to 63, that is, 0 and 32, 1 and 33 and so 01 3 pair of10.7 BS mode 10.7.1 Display area 0 639 339 10.7.2 Dot clock WCS=0 DCKW-2 = 21. 5M 10.7.3 Horizontal synchronous frequency HSCN1 + 24, 8k, 10.7.4 Image space © 1024 2047 % % si2 loz 2047 10.7.5 Number of usable screens Supposing that 1 screen consists of 1024x256 dots: (coor) 42 BIT/DOT) Cinw [© | 0 | KIWI KIMMO = Number of dots in X direction in imate cum | 1 | 0 space selected (nang | str | vst Ion 2048 dots 512k | 1 o;2ia4 1 oO + 1024 dots 3% asex [o [1 | 1 pee ‘(128K | 0 oj] 0 1 Number of dots in Y direction is automatically calculated (BYTE) from the above 6 bits, 3% (Bxample) Image space when CLRMI=0,CLRMO=0 VSLI-O,VSLO=1 XIMMI=1, XIMMO=0, Note: When setting the color palette data, use the s ye value for each corresponding pair of palette addresses 0 to 31 and 32 to 63, that is, 0 and 32, I and 33 and so on, 410.8 B6 mode 10.8.1 Display area ° 639 ang 10.8.2 Dot clock WCS=0 DCKW=2,C25Y=1 : 25, 2MH 10.8.3 Horizontal synchronous frequency HSCN=1 = 31. Skits 10.8.4 Image space © 1024 2047 % % 51 1074 2047 10.8.5 Number of usable screens Supposing that I screen consists of 1024x256 dots: (coon) 42 (BiT/00T) CuRML | 0 | 0] KIMI XIMMO = Nunber of dots in X direction in camo [1 |o space selected (raw) | vst | VSL | 11 = 2048 dots six [1 [olala| 10 = 102d dots asex’ | 0 1 1 pK? wx [0 [0 [0 [1 | — musber of dots in ¥ direction is automatically calculated (BYTE) from the above 6 bits. 3 (Example) Image space when CLRMI=0,CLRMO=0 VSLI=0,VSLO=1 KIMMI=1,X1MM0=0. Note: When setting the color palette data, use the same value for each corresponding pair of palette addresses 0 to 31 and 32 to 63, that is, 0 and 32, 1 and 33 and so on, -6-10.9 VRAM MAP (B1~B6) 128KB 256KB 512KB 0000 0000 000 PGT 1000 LEO PGT 200 FEO PGT 400 4000 Carsor area:512B Tr600 rg R60 TF 1H Tee =VRAM (256KB) to image space correspondence when the dot Number in the X direction of the image space is 512 at 8BIT/DOT in BI node. oo sil of oy 1 ie] FF 200 FF suf sre00 | 3FB01 ‘SFPPE | SPFPP When using a cursor, 512 bytes from the upper address of VRAM are used as the data area for the cursor, Display 0 possible in this ares. (No skipping occurs during display.) s Access to the cursor data area should be done by making use of the image (7FEOO~) of fe VRAM space. By doing so, compatibility of the upper 512 bytes of the enti software between ifferent VRAM models can be retained, 10.10 PGT bit assign (B1~B6) 2BIT/DOT 4BIT/DOT DTDs DS DL US D2 DIDO D1 D6 D5 DA D3 2 DIDO 0000 [0.0 | 1,0 | 2.0 | 30 | 00000/ 0.0 1,0 ooooi] 4.0 | 5,0 | 6.0 | 7.0 | ooo! 2.0 3.0 0002 | 8.0 | 9,0 [10,0 | 11,0 | ooo2| 4.0 5,0 8BIT/DOT wBIT/DOT D1 DS DS DA DS D2 D1 DO D7 D6 D5 DA D3 m@ DIDO 00000 0,0 00000 0,0 Low 00001 10 0001] 0,0 HIGH ooo 2,0 00002 108 10.11 VRAM physical address (B1~B6) VRAMO is mapped to the address (even address) where LSB of the logical address is ‘O” and RAMI to the address where LSB is “I”, Bach physical address of YRAMO and YRAMI becones a logical address divided by 2. aa10.12 Cursor area assign (B1~B6) D7 D6 DS Dé DS Dz DI DO v6 YS v4 ¥3 v2 Vi YO ------- 11% 15 13 1 XM 10 TREO a soars) CCl CoO BOR PRO — 19 18 ‘FES — fsuat@a) TrE10 ‘7FFO0 csrorer 128) res9| 2 cskirer «azs) ‘TFFFF DI_D6 DS DA D3 D2 DI DO LINBO (4) or? 345 67 LINEI (4) 83 10 1 2 1s 4 18 16 17 18 19 20 21 22 23 Lines1(@ | \[24_ 25 26 27 28 29 30 31 —48—10.13 Cursor play specifications (B1~ B6) + Co-ordinate space (0,0) Display area Ca} (1023 ,511) Both X and Y co-ordinate spaces roll in this size, ‘The vertical display position is the specified ¥ co-ordinate plus interlace), * Displayed color Palette Address Ss oM B® em MM WO espos | csroa [csros [csroz | cci | coo PGT data=“0" or (CC1,CCO,EOR)=(“0", “0”, “0") BOR color displayed on image sereen : (CC1,CCD,BOR)=("0", ‘0",“I") Clear colo: yy control PRO="I" = Not displayed PRO-‘0" : Displayed —9- "1" (plus 2" for‘| COMMAND 11.1 Command execution method After setting the necess: willl be exeeut Y parameter regist As soon as executi set the command to the operation code register, and it a is started, the status CE is set to “I” and upon completion, it is reset to ‘O", Farthermore, the interrupt flag CE is set to “I”, Most commands are issued after the necessary registers out of the following parameters are set. Also some commands require output and input of the necessary data at and through the command date port after they are issued, 1, Source (for transfer) co-ordinate 2, Destination (for transfer) co-ordinate 3, Transfer range co-ordinates 4, Argument, logical operation and write mask 5. Font color 5011.2. Parameter setting Source (for transfer) co-ordinate address byes tk pase [Sx7_[ 8x6] SxS | Sxe_ [9x3 SZ SKI Sx0 SAT_[-SA6_[-SAS__[-SAA__[-SA3_[_SA2_|SAL_| “SAO. KAT_|-KAB[-KAS[-KAA|_KA3__| KAZ | KAI_| KAO wes a rasa [Sv7 | S¥6 | S¥5 [sya sv3_ | svz_ [svi] vo SAIS_|SAIA_[-SA13_ | SAI2_|SALT_|-SAIO_[ SAO [SAB RAIS [KALA [KAS |-KAIZ_ | KALT | KAIO | KA9 | KAS RIBS psi | sre si 88] “[-sais_[sait_|saté [KArT_[-KAI6- +There are 3 ways of setting depending on types of command as follows. 1) LMCM, LMMM, BMLX, SRCH, POINT cified with the X co-ordinate of the image co-ordinate space (by dots) rolling to ‘0 occurs when a larger value than the image size is used for setting. (When in Pl node, screon ‘A” is selected at SX9-0 and screen ‘B” at SEI.) Specified with the Y co-ordinate of the image co-ordinate space (by dots) and rolling to ‘O” occurs when a larger value than the image size is used for setting. BMXL, BMLL Specified with the address on the VRAM p (by bytes). +: Specified with the kanji ROM address (by bytes). co-ordinate * [a a YY D6 Drapes ox2_[ OKI x0 DAS [paps Tava eet (Too ToT) Rass (pr ve Dais_[_DAIA bis bw] pi | vo DALT_|-DAIO| Dag | DAB RESO byt | pyi0 [bya | bys DAIS | DAIT_ | DAIG - There are 2 ways of setting depending on types of command as follows. 1) LMMC, LMMV, LMMM, CMMC, CMMK, CMMM, BMXL. LINE, PSET, ADVN DKO-10 : Specified with the X co-ordinate of the image co-ordinate space (by dots) and to “0” occurs when a larger value than the image size is used for (When in Pl node, screen ‘A is selected at DI9-O and screen ‘B” at DYO-I1 = jed with the Y co-ordinate of the image co-ordinate space (by dots) rolling to ‘O” occurs when a larger value than the image size is used for setting.