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Model Paper - B.Tech - DLD (II-I CAD)

This document is a question paper for a Digital Logic Design exam with 5 units. Each unit contains 2 questions with one to be answered. Unit 1 covers number conversion between binary, octal, decimal. Unit 2 covers Boolean algebra theorems and logic expressions. Unit 3 covers simplifying logic functions using K-maps. Unit 4 covers designing logic circuits like full adder, 4:16 decoder, full subtractor, multiplexer. Unit 5 covers flip flops, registers, counters. Students are required to answer questions that test their knowledge of digital logic design concepts.

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122 views2 pages

Model Paper - B.Tech - DLD (II-I CAD)

This document is a question paper for a Digital Logic Design exam with 5 units. Each unit contains 2 questions with one to be answered. Unit 1 covers number conversion between binary, octal, decimal. Unit 2 covers Boolean algebra theorems and logic expressions. Unit 3 covers simplifying logic functions using K-maps. Unit 4 covers designing logic circuits like full adder, 4:16 decoder, full subtractor, multiplexer. Unit 5 covers flip flops, registers, counters. Students are required to answer questions that test their knowledge of digital logic design concepts.

Uploaded by

chikkam bala sameer
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BONAM VENKATA CHALAMAYYA ENGINEERING COLLEGE::ODALAREVU

(AUTONOMOUS)
II-B.Tech I-Semester Regular End Examinations (BR20), FEB - 2020
Digital Logic Design (CSE) Course Code: 20CS3T05
Time: 3 hours Max. Marks: 70
-------------------------------------------------------------------------------------------------------------------------------
Question Paper consists of FIVE units, each carrying 14 marks
Each unit has TWO questions; either of them should be answered
All parts of a question must be answered at one place
--------------------------------------------------------------------------------------------------------------------------------
UNIT-I
1.a) Solve the following numbers Conversion (7M)
i) (57.125)10 = ( )8 ii) (30.6875)10 = ( )2 iii) (137.75)8 = ( )10
1.b) Express the subtraction using 2’s complement method. (7M)
i) 11010-10100 ii) 11010-1101.10 iii)110-110000
(OR)
1.c) Convert the following numbers to Octal:
(i) (1011.1010)2 (ii) (BABA)16 (7M)
1.d) Perform the binary subtraction using 1’s and 2’s complement methods. (7M)
(110011)2-(1110011)2
UNIT-II
2.a) State and Prove the DeMorgan’s laws (7M)
2.b) Convert the given Boolean function into Standard Sum Of Minterms form (7M)
F= x’y + y’z + xz
(OR)
2.c) Explain the theorems and properties of Boolean algebra. (7M)
2.d) Convert the following Boolean function into standard product of maxterms form. (7M)
F = A'B+C+B'D'
UNIT-III
3.a) Solve the following expression to the simplest possible SOP and POS form (7M)
F= Σ (0,1,2,5,6) using K-Map method
3.b) Solve the following Boolean function F(A, B, C, D)= Σ (0, 6, 8, 13, 14); d(A, B, C, D)= (7M)
Σ (2, 4,10) using K-Map method in (a)SOP form (b) POS form
(OR)
3.c) Simplify the following using K- map and implement the same using NAND gates. (7M)
Y (A, B, C) = Σ (0, 2, 4, 5, 6, 7)
3.d) Simplify the following Boolean function F(A, B, C, D)= Σ (1, 3, 8, 10, 15); d(A, B, C, (7M)
D)= Σ (0, 2,9) using K-Map method in (a)SOP form (b) POS form
UNIT-IV
4.a) Design and draw a full adder which will use two half adders? (7M)
4 Write the gate level HDL description of the 4:16 decoder? (7M)
4.b)
(OR)
4.c) Design and draw a full subtractor which will use two half subtractors? (7M)
4.d) Design an 8X1 multiplexer with basic gates? (7M)
UNIT-V
5.a) Design a SR flip flop using NOR gates. Explain the operation of the SR flip (7M)
flop with the help of characteristic table?
5.b) What is a register? Discuss the applications of shift registers? (7M)
(OR)
5.c) Explain the operation of a JK flip-flop with the truth table. (7M)
5.d) Write the design steps of synchronous counters with suitable examples? (7M)
**********

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