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Csen1051 - Digital Logic Circuits

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0% found this document useful (0 votes)
12 views2 pages

Csen1051 - Digital Logic Circuits

Uploaded by

Arepally Sukumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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[Nov-23]

GITAM (Deemed to be University)


[CSEN1051]
GST/GSS/GSB/GSHS Degree Examination
III Semester
DIGITAL LOGIC CIRCUITS
(Effective for the admitted batch 2021-22 AB)
Time: 2 Hours Max. Marks: 30
-----------------------------------------------------------------------------------------------------
Instructions: All parts of the unit must be answered in one place only.
--------------------------------------------------------------------------------------- -------------
Section-A
1. Answer all Questions: (51=05)
a) Convert the following nos.
(i) (673.6)8 =(…….)16 (ii) (1938.257)10 =(…….)16
b) Prove that AB+BC+AB+BC = 1
c) Represent the following Boolean function using K-Map.
F(a,b,c,d) = ∏𝑚𝑎𝑥(0,2,4,5,6,7,8,10,13,15)
d) Why Full Adder preferred over Half Adder
e) Draw the basic memory element using NAND gates.
Section-B
Answer the following: (55=25)
UNIT-I
2. a) Subtract (436)10-(349)10 using 2’s complement method.
b) Find the sum using 1’s complement. (84)10 and (67)10
OR
3. Find the hamming code of the binary code 1101 considering the
sender sending the even parity code to receiver.
UNIT-II
4. Explain all the basic rules of Boolean algebra along with proofs.
OR
5. Convert the Boolean function xy+x'z+y' into Canonical sum of
minterms.
UNIT-III
6. Using K-map, find minimal SOP expression for the following logic
function F=  (4,5,9,13,15) + d (0,1,7,11,12)
OR
7. Minimize the following Switching function using K-map and Draw
circuit diagram using basic gates F(A, B, C, D) =  (0,4,5,7).
UNIT-IV
8. Design Half substractor & Full substractors
OR
9. Implement the following SOP using 8:1 multiplexer.
F(A, B, C, D) =(1,3,4,11,12, 13,14,15)
UNIT-V
10. Convert (a) JK-FF into D- FF (b) JK- FF into T- FF
OR
11. Design3-bit synchronous up-counter with circuit diagram.

[IIIS/123]

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