®

ISL8700A, ISL8701A, ISL8702A,

ISL8703A, ISL8704A, ISL8705A
Data Sheet October 12, 2006 FN6381.0

Adjustable Quad Sequencer Features

The ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, • Adjustable Delay to Subsequent Enable Signal
ISL8705A family of ICs provide four delay adjustable
• Adjustable Delay to Sequence Auto Start
sequenced outputs while monitoring an input voltage all with
a minimum of external components. • Adjustable Distributed Voltage Monitoring
High performance DSP, FPGA, µP and various sub-systems • Under and Overvoltage Adjustable Delay to Auto Start
require input power sequencing for proper functionality at Sequence
initial power up and the ISL870XA provides this function • I/O Options
while monitoring the distributed voltage for over and ENABLE (ISL8700A, ISL8702A, ISL8704A) and
undervoltage compliance. ENABLE# (ISL8701A, ISL8703A, ISL8705A)
These ICs operate over the +3.3V to +24V nominal voltage SEQ_EN (ISL8702A, ISL8703A) and
range. All have a user adjustable time from UV and OV SEQ_EN# (ISL8704A, ISL8705A)
voltage compliance to sequencing start via an external • Voltage Compliance Fault Output
capacitor when in auto start mode and adjustable time delay
• Pb-Free Plus Anneal Available (RoHS Compliant)
to subsequent ENABLE output signal via external resistors.
Additionally, the ISL8702A, ISL8703A, ISL8704A and Applications
ISL8705A provide I/O for sequencing on and off operation
• Power Supply Sequencing
(SEQ_EN) and for voltage window compliance reporting
(FAULT) over the +3.3V to +24V nominal voltage range. • System Timing Function
Easily daisy chained for more than 4 sequenced signals.
Pinout
Altogether, the ISL870XA provides these adjustable features ISL870XA
with a minimum of external BOM. See Figure 1 for typical (14 LD SOIC)
TOP VIEW
implementation.
Ordering Information ENABLE_D 1 14 VIN
ENABLE_C 2 13 TD
PART NUMBER PART TEMP. PACKAGE PKG.
(Note 1) MARKING RANGE (°C) (Pb-free) DWG. # ENABLE_B 3 12 TC

ISL8700AIBZ* ISL8700AIBZ -40 to +85 14 Ld SOIC M14.15 ENABLE_A 4 11 TB

OV 5 10 TIME
ISL8701AIBZ* ISL8701AIBZ -40 to +85 14 Ld SOIC M14.15
UV 6 9 SEQ_EN (NC on ISL8700A/01A)
ISL8702AIBZ* ISL8702AIBZ -40 to +85 14 Ld SOIC M14.15 GND 7 8 FAULT (NC on ISL8700A/01A)
ISL8703AIBZ* ISL8703AIBZ -40 to +85 14 Ld SOIC M14.15
ISL8701A, ISL8703A, ISL8705A PINS 1-4 ARE ENABLE# FUNCTION
ISL8704AIBZ* ISL8704AIBZ -40 to +85 14 Ld SOIC M14.15 ISL8704A, ISL8705A PIN 9 IS SEQ_EN# FUNCTION
ISL8705AIBZ* ISL8705AIBZ -40 to +85 14 Ld SOIC M14.15
ISL870XAEVAL1 Evaluation Platform 3.3-24V
*Add “-T” suffix for tape and reel.
EN
NOTES: DC/DC Vo1
Ru VIN
1. Intersil Pb-free plus anneal products employ special Pb-free material ENABLE_A
SEQ_EN * ENABLE_B
sets; molding compounds/die attach materials and 100% matte tin
ENABLE_C EN
plate termination finish, which are RoHS compliant and compatible UV ENABLE_D DC/DC Vo2
with both SnPb and Pb-free soldering operations. Intersil Pb-free
Rm
products are MSL classified at Pb-free peak reflow temperatures that OV FAULT *
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. EN
GND TB TC TD TIME DC/DC Vo3
Rl

EN
DC/DC V04

* SEQ_EN and FAULT are not available on ISL8700A and ISL8701A

FIGURE 1. ISL870XA IMPLEMENTATION

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A

Absolute Maximum Ratings Thermal Information

VIN, ENABLE(#), FAULT . . . . . . . . . . . . . . . . . . . . . . . 27V, to -0.3V Thermal Resistance (Typical, Note 2) θJA (°C/W)
TIME, TB, TC, TD, UV, OV . . . . . . . . . . . . . . . . . . . . . +6V, to -0.3V 14 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SEQ_EN(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN+0.3V, to -0.3V Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
ENABLE, ENABLE # Output Current . . . . . . . . . . . . . . . . . . . 10mA Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
Operating Conditions (SOIC Lead Tips Only)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Nominal). . . . . . . . . . . . . . . . . . 3.3V to 24V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications Nominal VIN = 3.3V to +24V, TA = TJ = -40°C to+85°C, Unless Otherwise Specified.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
UV AND OV INPUTS
UV/OV Rising Threshold VUVRvth 1.16 1.21 1.28 V
UV/OV Falling Threshold VUVFvth 1.06 1.10 1.18 V
UV/OV Hysteresis VUVhys VUVRvth - VUVFvth - 104 - mV
UV/OV Input Current IUV - 10 - nA
TIME, ENABLE/ENABLE# OUTPUTS
TIME Pin Charging Current ITIME - 2.6 - μA
TIME Pin Threshold VTIME_VTH 1.9 2.0 2.25 V
Time from VIN Valid to ENABLE_A tVINSEQpd SEQ_EN = high, CTIME = open - 30 - μs
tVINSEQpd_10 SEQ_EN = high, CTIME = 10nF - 7.7 - ms
tVINSEQpd500 SEQ_EN = high, CTIME = 500nF - 435 - ms
Time from VIN Invalid to Shutdown tshutdown UV or OV to simultaneous shutdown - - 1 μs
ENABLE Output Resistance REN IENABLE = 1mA - 100 - Ω
ENABLE Output Low Vol IENABLE = 1mA - 0.1 - V
ENABLE Pull-down Current Ipulld ENABLE = 1V 10 15 - mA
Delay to Subsequent ENABLE Turn-on/off tdel_120 RTX = 120kΩ 155 195 240 ms
tdel_3 RTX = 3kΩ 3.5 4.7 6 ms
tdel_0 RTX = 0Ω - 0.5 - ms
SEQUENCE ENABLE AND FAULT I/O
VIN Valid to FAULT Low tFLTL 15 30 50 μs
VIN Invalid to FAULT High tFLTH - 0.5 - μs
FAULT Pull-down Current FAULT = 1V 10 15 - mA
SEQ_EN Pull-up Voltage VSEQ SEQ_EN open - 2.4 - V
SEQ_EN Low Threshold Voltage VilSEQ_EN - - 0.3 V
SEQ_EN High Threshold Voltage VihSEQ_EN 1.2 - - V
Delay to ENABLE_A Deasserted tSEQ_EN_ENA SEQ_EN low to ENABLE_A low - 0.2 1 μs
BIAS
IC Supply Current IVIN_3.3V VIN = 3.3V - 191 - μA
IVIN_12V VIN = 12V - 246 400 μA
IVIN_24V VIN = 24V - 286 - μA
VIN Power On Reset VIN_POR VIN low to high - 2.3 2.8 V

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 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A

Pin Descriptions
PINS
8700A 8701A 8702A 8703A 8704A 8705A PIN NAME FUNCTION DESCRIPTION
NA 1 NA 1 NA 1 ENABLE#_D Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output
to sequence off for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
1 NA 1 NA 1 NA ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output
to sequence off for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V.
NA 2 NA 2 NA 2 ENABLE#_C Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced
off after ENABLE#_D for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
2 NA 2 NA 2 NA ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced
off after ENABLE_D for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V.
NA 3 NA 3 NA 3 ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced
off after ENABLE#_C for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
3 NA 3 NA 3 NA ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced
off after ENABLE_C for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN < 1V.
NA 4 NA 4 NA 4 ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE#_B for the ISL8701A, ISL8703A, ISL8705A. Tracks VIN upon bias.
4 NA 4 NA 4 NA ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and
sequenced off after ENABLE_B for the ISL8700A, ISL8702A, ISL8704A. Pulls low with VIN
< 1V.
5 5 5 5 5 5 OV The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
6 6 6 6 6 6 UV The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
7 7 7 7 7 7 GND IC ground.
NA NA 8 8 8 8 FAULT The VIN voltage when not within the desired UV to OV window will cause FAULT to be
released to be pulled high to a voltage equal to or less than VIN via an external resistor.
NA NA 9 9 NA NA SEQ_EN This pin provides a sequence on signal input with a high input. Internally pulled high to ~2.4V.
NA NA NA NA 9 9 SEQ_EN# This pin provides a sequence on signal input with a low input. Internally pulled high to ~2.4V.
10 10 10 10 10 10 TIME This pin provides a 2.6µA current output so that an adjustable VIN valid to sequencing on
and off start delay period is created with a capacitor to ground.
11 11 11 11 11 11 TB A resistor connected from this pin to ground determines the time delay from ENABLE_A
being active to ENABLE _B being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
12 12 12 12 12 12 TC A resistor connected from this pin to ground determines the time delay from ENABLE_B
being active to ENABLE _C being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
13 13 13 13 13 13 TD A resistor connected from this pin to ground determines the time delay from ENABLE_C
being active to ENABLE _D being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
14 14 14 14 14 14 VIN IC Bias Pin Nominally 3.3V to 24V
This pin requires a 1μF decoupling capacitor close to IC pin.

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 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A

Functional Block Diagram

VIN (2.8V MIN - 27V MAX)

VIN VREF VOLTAGE

1.17V REFERENCE

SEQ_EN VIN INTERNAL VOLTAGE

3.5V REGULATOR
UV +
eo
-
ENABLE_A
2.0V VIN POR
+ LOGIC

OV - ENABLE_B
FAULT
30μs ENABLE_C

GND
VTIME_VTH ENABLE_D
PROGRAMMABLE
VIN DELAY TIMER

2.6μA

TIME

TB TC TD

Functional Description greater than VTIME_VTH the ISL8700A, ISL8702A, ISL8704A

ENABLE_A is released to go high via an external pull-up
The ISL870XA family of ICs provides four delay adjustable
resistor or a pull-up in a DC/DC convertor enable input, for
sequenced outputs while monitoring a single distributed voltage
example. Conversely, ENABLE#_A output will be pulled low at
in the nominal range of 3.3V to 24V for both under and
this time on an ISL8701A, ISL8703A, ISL8705A. The time
overvoltage. Only when the voltage is in compliance will the
delay generated by the external capacitor is to assure
ISL870XA initiate the pre-programmed A-B-C-D sequence of
continued voltage compliance within the programmed limits, as
the ENABLE (ISL8700A, ISL8702A, ISL8704A) or ENABLE#
during this time any OV or UV condition will halt the start-up
(ISL8701A, ISL8703A, ISL8705A) outputs. Although this IC has
process. TIME cap is discharged once VTIME_VTH is met.
a bias range of 3.3V to 24V it can monitor any voltage >1.22V
via the external divider if a suitable bias voltage is otherwise Once ENABLE_A is active (either released high on the
provided. ISL8700A, ISL8702A, ISL8704A or pulled low, ISL8701A,
ISL8703A, ISL8705A) a counter is started and using the
During initial bias voltage (VIN) application the ISL8700A,
resistor on TB as a timing component a delay is generated
ISL8702A, ISL8704A ENABLE outputs are held low once
before ENABLE_B is activated. At this time, the counter is
VIN = 1V whereas the ISL8701A, ISL8703A, ISL8705A
restarted using the resistor on TC as its timing component for
ENABLE# outputs follow the rising VIN. Once VIN > the V bias
a separate timed delay until ENABLE_C is activated. This
power on reset threshold (POR) of 2.8V, VIN is constantly
process is repeated for the resistor on TD to complete the
monitored for compliance via the input voltage resistor divider
A-B-C-D sequencing order of the ENABLE or ENABLE#
and the voltages on the UV and OV pins and reported by the
outputs. At any time during sequencing if an OV or UV event
FAULT output. Internally, voltage regulators generate 3.5V and
is registered, all four ENABLE outputs will immediately return
1.17V ±5% voltage rails for internal usage once VIN > POR.
to their reset state; low for ISL8700A, ISL8702A, ISL8704A
Once UV > 1.22V and with the SEQ_EN pin high or open,
and high for ISL8701A, ISL8703A, ISL8705A. CTIME is
(SEQ_EN# must be pulled low on ISL8704A, ISL8705A) the
immediately discharged after initial ramp up thus waiting for
auto sequence of the four ENABLE (ENABLE#) outputs begins
subsequent voltage compliance to restart. Once sequencing
as the TIME pin charges its external capacitor with a 2.6µA
is complete, any subsequently registered UV or OV event will
current source. The voltage on TIME is compared to the
trigger an immediate and simultaneous reset of all ENABLE or
internal reference (VTIME_VTH) comparator input and when
ENABLE# outputs.

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 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A

On the ISL8702A, ISL8703A, ISL8704A and ISL8705A, requirement please see the next section.
enabling of on or off sequencing can also be signaled via the
1. Determine if turn-on or shutdown limits are preferred. In this
SEQ_EN or SEQ_EN# input pin once voltage compliance is
example, we will determine the resistor values based on the
met. Initially, the SEQ_EN pin should be held low and shutdown limits.
released when sequence start is desired. The SEQ# is
2. Establish lower and upper trip level: 12V ±10% or 13.2V
internally pulled high and sequencing is enabled when it is
(OV) and 10.8V (UV)
pulled low. The on sequence of the ENABLE outputs is as
3. Establish total resistor string value: 100kΩ, Ir = divider
previously described. The off sequence feature is only
current
available on the variants having the SEQ_EN or the
SEQ_EN# inputs, these being the ISL8702A, ISL8703A, 4. (Rm+Rl) x Ir = 1.1V @ UV and Rl x Ir = 1.2V @ OV
ISL8704A, ISL8705A. The sequence is D off, then C off, then 5. Rm+Rl = 1.1V/Ir @ UV = Rm+Rl = 1.1V/(10.8V/100kΩ) =
B off and finally A off. Once SEQ_EN (SEQ_EN#) is signaled 10.370kΩ
low (high), the TIME cap is charged to 2V once again. Once 6. Rl = 1.2V/Ir @ OV = Rl = 1.2V/(13.2V/100kΩ) = 9.242kΩ
this Vth is reached, ENABLE_D transitions to its reset state 7. Rm = 10.370kΩ - 9.242kΩ = 1.128kΩ
and CTIM is discharged. A delay and subsequent sequence 8. Ru = 100kΩ - 10.370kΩ = 89.630kΩ
off is then determined by TD resistor to ENABLE_C. Likewise,
9. Choose standard value resistors that most closely
a delay to ENABLE_B and then ENABLE_A turn-off is approximate these ideal values. Choosing a different total
determined by TC and TB resistor values respectively. divider resistance value may yield a more ideal ratio with
With the ISL8700A, ISL8701A a quasi down sequencing of the available resistor’s values.
ENABLE outputs can be achieved by loading the ENABLE pins In our example, with the closest standard values of
with various value capacitors to ground. When a simultaneous Ru = 90.9kΩ, Rm = 1.13kΩ and Rl = 9.31kΩ, the nominal UV
output latch off is invoked, the caps will set the falling ramp of falling and OV rising will be at 10.9V and 13.3V respectively.
the various ENABLE outputs thus adjusting the time to Vth for
Programming the ENABLE Output Delays
various DC/DC convertors or other circuitry.
The delay timing between the four sequenced ENABLE outputs
Regardless of IC variant, the FAULT signal is always valid at are programmed with four external passive components. The
operational voltages and can be used as justification for delay from a valid VIN (ISL8700A and ISL8701A) to
SEQ_EN release or even controlled with an RC timer for ENABLE_A and SEQ_EN being valid (ISL8702A, ISL8703A,
sequence on. ISL8704A, ISL8705A) to ENABLE_A is determined by the
Programming the Under and Overvoltage Limits value of the capacitor on the TIME pin to GND. The external
TIME pin capacitor is charged with a 2.6µA current source.
When choosing resistors for the divider remember to keep the
Once the voltage on TIME is charged up to the internal
current through the string bounded by power loss at the top end
reference voltage, (VTIME_VTH) the ENABLE_A output is
and noise immunity at the bottom end. For most applications,
released out of its reset state. The capacitor value for a desired
total divider resistance in the 10kΩ to1000kΩ range is
delay (±10%) to ENABLE_A once VIN and SEQ_EN where
advisable with high precision resistors being used to reduce
applicable has been satisfied is determined by:
monitoring error. Although for the ISL870XA, two dividers of two
resistors each can be employed to separately monitor the OV CTIME = tVINSEQpd/770kΩ
and UV levels for the VIN voltage. We will discuss using a
Once ENABLE_A reaches VTIME_VTH, the TIME pin is pulled
single three resistor string for monitoring the VIN voltage,
low in preparation for a sequenced off signal via SEQ_EN. At
referencing Figure 1. In the three resistor divider string with Ru
this time, the sequencing of the subsequent outputs is started.
(upper), Rm (middle) and Rl (lower), the ratios of each in
ENABLE_B is released out of reset after a programmable time,
combination to the other two is balanced to achieve the desired
then ENABLE_C, then ENABLE _D, all with their own
UV and OV trip levels. Although this IC has a bias range of 3.3V
programmed delay times.
to 24V, it can monitor any voltage >1.22V.
The ratio of the desired overvoltage trip point to the internal The subsequent delay times are programmed with a single
reference is equal to the ratio of the two upper resistors to the external resistor for each ENABLE output providing maximum
lowest (gnd connected) resistor. flexibility to the designer through the choice of the resistor value
connected from TB, TC and TD pins to GND. The resistor
The ratio of the desired undervoltage trip point to the internal values determine the charge and discharge rate of an internal
reference voltage is equal to the ratio of the uppermost (voltage capacitor comprising an RC time constant for an oscillator
connected) resistor to the lower two resistors. whose output is fed into a counter generating the timing delay
These assumptions are true for both rising (turn-on) or falling to ENABLE output sequencing.
(shutdown) voltages. The RTX value for a given delay time is defined as:
The following is a practical example worked out. For detailed
RTX = tdel/1667nF
equatons on how to perform this operation for a given supply

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 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A

An Advanced Tutorial on Setting UV and OV Levels This will give a window of 12 ±0.48V where the system is
This section discusses in additional detail the nuances of guaranteed not to be in fault and a limit of 12 ±1.5V beyond
setting the UV and OV levels, providing more insight into the which the system is guaranteed to be in fault.
ISL870XA than the earlier text. It is wise to check both these voltages, for if the latter is made to
The following equation set can alternatively be used to work out tight, the former will cease to exist. This point comes when Vtol
ideal values for a 3 resistor divider string of Ru, Rm and Rl. < Vhys/2 and results from the fact that the acceptable window
These equations assume that VREF is the center point between for the OV pin no longer aligns with the acceptable window for
VUVRvth and VUVFvth (i.e. (VUVRvth + VUVFvth)/2 = 1.17V), the UV pin. In this case, the application will have to be changed
Iload is the load current in the resistor string (i.e. VIN /(Ru + Rm such that UV and OV are provided separate resistor strings. In
+ Rl)), VIN is the nominal input voltage and Vtol is the this case, the UV and OV thresholds can be individually
acceptable voltage tolerance, such that the UV and OV controlled by adjusting the relevant divider.
thresholds are centered at VIN ± Vtol. The actual acceptable The previous example will give voltage thresholds of:
voltage window will also be affected by the hysteresis at the UV
and OV pins. This hysteresis is amplified by the resistor string with VIN rising
such that the hysteresis at the top of the string is: UVr = VIN - Vtol + Vhys/2 = 11.5V and
OVr = VIN + Vtol + Vhys/2 = 13.5V
Vhys = VUVhys x VOUT/VREF
with VIN falling
This means that the VIN ± Vtol thresholds will exhibit Ovf = VIN + Vtol - Vhys/2 = 12.5V and
hysteresis resulting in thresholds of VIN + Vtol ± Vhys/2 and UVf = VIN - Vtol - Vhys/2 = 10.5V.
VIN - Vtol ± Vhys/2.
So with a single three resistor string, the resistor values can
There is a window between the VIN rising UV threshold and be calculated as:
the VIN falling OV threshold where the input level is
guaranteed not to be detected as a fault. This window exists Rl = (VREF/Iload) (1 - Vtol/VIN)
between the limits VIN ± (Vtol - Vhys/2). There is an Rm = 2(VREF x Vtol)/(VIN x Iload)
extension of this window in each direction up to Ru = 1/Iload x (VIN - VREF (1+Vtol/VIN))
VIN ± (Vtol + Vhys/2), where the voltage may or may not be For the above example, with Vtol = 0.99V, assuming a
detected as a fault, depending on the direction from which it 100µA Iload at VIN = 12V:
is approached. These two equations may be used to
determine the required value of Vtol for a given system. For Rl = 10.7kΩ
example, if VIN is 12V, Vhys = (0.1 x 12)/1.17 = 1.03V. If VIN Rm = 1.9kΩ
must remain within 12V ± 1.5V, Vtol = 1.5 - 1.03/2 = 0.99V. Ru = 107.3kΩ

FAULT

SEQ_EN

TIME

A B C D D C B A
ENABLE OUTPUTS

FIGURE 2. ISL8702A OPERATIONAL DIAGRAM

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 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A

OVERVOLTAGE
LIMIT
tFLTH
<tFLTH tFLTL
UNDERVOLTAGE
LIMIT
tFLTL
MONITORED VOLTAGE tFLTH
RAMPING UP AND DOWN

FAULT OUTPUT

FIGURE 3. ISL8702A, ISL8703A, ISL8704A, ISL8705A FAULT OPERATIONAL DIAGRAM

Typical Performance Curves

1.208 310
1.207
290
UV/OV THRESHOLD (V)

1.206 VIN = 24V

270
1.205
1.204 VIN = 2.5V 250

IVIN (µA)
1.203 VIN = 12V 230 VIN = 12V
1.202 210
1.201
190
1.200 VIN = 2.5V
VIN = 24V
1.199 170

1.198 150
-40 -10 0 25 60 85 100 -40 -10 0 25 60 85 100
TEMP (°C) TEMP (°C)

FIGURE 4. UV/OV RISING THRESHOLD FIGURE 5. VIN CURRENT

Applications Usage Once the voltage monitoring FAULT is resolved and where
applicable, the SEQ_EN(#) is satisfied, sequencing of the
Using the ISL870XAEVAL1 Platform ENABLE_X(#) outputs begins. When sequence enabled the
The ISL870XAEVAL1 platform is the primary evaluation ENABLE_A, ENABLE_B, ENABLE_C and lastly
board for this family of sequencers. See Figure 16 for ENABLE_D are asserted in that order and when SEQ_EN is
photograph and schematic.The evaluation board is shipped disabled the order is reversed. See Figures 8 and 9
with an ISL8702A mounted in the left position and with the demonstrating the sequenced enabling and disabling of the
other device variants loose packed. In the following ENABLE outputs. The timing between ENABLE outputs is
discussion, test points names are bold on initial occurrence set by the resistor values on the TB, TC, TD pins as shown.
for identification. Figure 10 illustrates the timing from either SEQ_EN and/or
VMONITOR being valid to ENABLE_A being asserted with a
The VIN test point is the chip bias and can be biased from
10nF TIME capacitor. Figure 11 shows that ENABLE_X
3.3V to 24V. The VHI test point is for the ENABLE and
outputs are pulled low even before VIN = 1V. This is critical
FAULT pull-up voltage which are limited to a maximum of
to ensure that a false enable is not signaled. Figure 12
24V independent of VIN. The UV/OV resistor divider is set so
illustrates the SEQ_EN# input disabling and enabling the
that a nominal 12V on the VMONITOR test point is compliant
ISL8705A ENABLE# outputs. Notice the reversal in order
and with a rising OV set at 13.2V and a falling UV set at
and delay timing from ENABLE_X# to ENABLE_X#.
10.7V. These three test points (VIN,VHI and VMONITOR)
Figure 13 shows the time from SEQ_EN transition with the
are brought out separately for maximum flexibility in
voltage ramping across the TIME capacitor to TIME Vth
evaluation.
being met. This results in the immediate pull down of the
VMONITOR ramping up and down through the UV and OV TIME pin and simultaneous ENABLE_A enabling.
levels will result in the FAULT output signaling the out of
bound conditions by being released to pull high to the VHI
voltage as shown in Figures 6 and 7.

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 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A

VMON FALLING
VMON RISING

VMON > OV
VMON > OV
VMON > UV LEVEL
LEVEL VMON > UV
LEVEL
LEVEL

FAULT OUTPUT FAULT OUTPUT

FIGURE 6. VMONITOR RISING TO FAULT FIGURE 7. VMONITOR FALLING TO FAULT

RTB = 3k RTB = 3k
DELAY = 5ms DELAY = 5ms

RTC = 51k RTD = 120k

DELAY = 86ms DELAY = 196ms

RTC = 51k
DELAY = 86ms

RTD = 120k
DELAY = 196ms

FIGURE 8. ENABLE_X TO ENABLE_X ENABLING FIGURE 9. ENABLE_X TO ENABLE_X DISABLING

VIN RISING

CTIME = 10nF
DELAY = 8.5ms

ENABLE OUTPUTS TRACKS VIN TO < 0.8V

1V/DIV 10ms/DIV

FIGURE 10. VIN/SEQ_EN VALID TO ENABLE_A FIGURE 11. ENABLE AS VIN RISES

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 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A

SEQ_EN#
SEQ_EN

ENABLE_A# ENABLE_A

TIME
ENABLE_B# 0.5V/DIV

ENABLE_C#

ENABLE_D#

FIGURE 12. ISL8705A ENABLE_X# TO ENABLE_X# FIGURE 13. SEQ_EN TO ENABLE_A

VMONITOR OV

VMONITOR UV

FAULT = LOW

8µs/DIV
FIGURE 14. OV AND UV TRANSIENT IMMUNITY

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 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A

Application Recommendations
Best practices VIN decoupling is required, a 1μF capacitor is
recommended. PIN 4
Coupling from the ENABLE_X pins to the sensitive UV and GND
OV pins can cause false OV/UV events to be detected. This
is most relevant for ISL8700A, ISL8702A, ISL8704A parts
due to the ENABLEA and OV pins being adjacent. This PIN 5
coupling can be reduced by adding a ground trace between
UV and the ENABLE/FAULT signals, as shown in Figure 15.
The PCB traces on OV and UV should be kept as small as
practical and the ENABLE_X and FAULT traces should
ideally not be routed under/over the OV/UV traces on
different PCB layers unless there is a ground or power plane
in between. Other methods that can be used to eliminate this
issue are by reducing the value of the resistors in the
FIGURE 15. LAYOUT DETAIL OF GND BETWEEN PINS 4 AND 5
network connected to UV and OV (R2, R3, R5 in Figure 16)
or by adding small decoupling capacitors to OV and UV (C2
and C7 in Figure 16). Both these methods act to reduce the
AC impedance at the nodes, although the latter method acts
to filter the signals which will also cause an increase in the
time that a UV/OV fault takes to be detected.

When the ISL870XA is implemented on a hot swappable

card that is plugged into an always powered passive back
plane an RC filter is required on the VIN pin to prevent a high
dv/dt transient. With the already existing 1μF decoupling
capacitor the addition of a small series R (>50Ω) to provide a
time constant >50μs is all that is necessary.

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 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
.

PULL-UP
RESISTORS
TIMING
COMPONENTS

UV/OV SET
RESISTORS

FIGURE 16. ISL870XAEVAL1 PHOTOGRAPH AND SCHEMATIC OF LEFT CHANNEL

TABLE 1. ISL870XAEVAL1 LEFT CHANNEL COMPONENT LISTING

COMPONENT
DESIGNATOR COMPONENT FUNCTION COMPONENT DESCRIPTION

U1 ISL8702A, Quad Under/Overvoltage Sequencer Intersil, ISL8702A, Quad Under/Overvoltage Sequencer

R3 UV Resistor for Divider String 1.1kΩ 1%, 0603

R2 VMONITOR Resistor for Divider String 88.7kΩ 1%, 0603

R5 OV Resistor for Divider String 9.1kΩ 1%, 0603

C1 CTIME Sets Delay from Sequence Start to First ENABLE 0.01μF, 0603

R1 RTD Sets Delay from Third to Fourth ENABLE 120kΩ 1%, 0603

R9 RTB Sets Delay from First to Second ENABLE 3.01kΩ 1%, 0603

R7 RTC Sets Delay from Second to Third ENABLE 51kΩ 1%, 0603

R4, R6, R8, R10, ENABLE_X(#) and FAULT Pull-up Resistors 4kΩ 10%, 0402
R11

C3 Decoupling Capacitor 1μF, 0603

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 ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A

Small Outline Plastic Packages (SOIC)

N M14.15 (JEDEC MS-012-AB ISSUE C)
INDEX
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
AREA H 0.25(0.010) M B M PACKAGE
E
INCHES MILLIMETERS
-B-
SYMBOL MIN MAX MIN MAX NOTES
A 0.0532 0.0688 1.35 1.75 -
1 2 3
L
A1 0.0040 0.0098 0.10 0.25 -
SEATING PLANE B 0.013 0.020 0.33 0.51 9
-A- C 0.0075 0.0098 0.19 0.25 -
D A h x 45o
D 0.3367 0.3444 8.55 8.75 3
-C- E 0.1497 0.1574 3.80 4.00 4
α e 0.050 BSC 1.27 BSC -
e A1
C H 0.2284 0.2440 5.80 6.20 -
B 0.10(0.004) h 0.0099 0.0196 0.25 0.50 5
0.25(0.010) M C A M B S
L 0.016 0.050 0.40 1.27 6
N 14 14 7
NOTES:
α 0o 8o 0o 8o -
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95. Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

12 FN6381.0
October 12, 2006
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