Sheet 2
Boolean Algebra and Logic Gates
Eng/Aya Saad
Rules
X+0=X , X.0=0
X+1=1 , X.1=X
X+X=X , X.X=X
(X\)\ = X , X\ + X = 1 , X\.X = 0
Commutative law: X+Y = Y+X , X.Y=Y.X
Associative Law: X+(Y+Z) = (X+Y) + Z , X.(Y.Z) = (X.Y).Z
Distribution Law: X+YZ = (X+Y)(X+Z)
DeMorgan’s theorem: (X+Y+Z)\ = X\Y\Z\ , (XYZ)\ = X\+Y\+Z\
2.1 Demonstrate the validity of the following identities by means of truth tables:
(a) DeMorgan’s theorem for three variables: (x + y + z)\ = x\y\z\ and (xyz)\ = x\ + y\ + z\
(x + y + z)\ = x\y\z\ (xyz)\ = x\ + y\ + z\
(b) The distributive law: x + yz = ( x + y )( x + z )
2.2 Simplify the following Boolean expressions to a minimum number of literals Draw logic
diagrams of the circuits that implement the original and simplified expressions
(a) xy + xy' = x(y + y') = x
(b) (x + y)(x + y’) = xx + xy' + xy + yy’
= x + x(y+y’) = x + x = x
c) xyz + x'y + xyz' = xy(z + z') + x’y
= xy + x'y = y
(d) (A + B)'(A' + B')' = (A'B')(A B) = (A'B')(BA)
= A'(B'B)A = 0
(e) (a + b + c')(a'b' + c) = aa'b' + ac + ba'b' + bc + c'a'b' + c’c
= ac + bc +a'b'c'
(f) a'bc + abc' + abc + a'bc' = a'b(c + c') + ab(c + c’)
= a'b + ab = (a' + a)b = b
2.3 Simplify the following Boolean expressions to a minimum number of literals:
(a) ABC + A'B + ABC' = AB(C+C’) + A'B = B(A+A’)= B
(b) x'yz + xz = (x'y + x)z = z(x + x')(x + y) = z(x + y)
(c) (x + y)'(x' + y') = x'y'(x' + y') = x'y’
(d) xy + x(wz + wz') = x(y +wz + wz') = x(w + y)
(e) (BC' + A'D)(AB' + CD') = BC'AB' + BC'CD' + A'DAB' + A'DCD' = 0
(f) (a' + c')(a + b' + c') = a'a + a'b' + a'c' + c'a + c'b' + c'c' = a'b' + a'c' + ac' + b'c’
= c' + b'(a' + c’)
= c' + b'c' + a'b' = c’ (1+b)+ a’b’
= c’ + a’b’
2.4 Reduce the following Boolean expressions to the indicated number of literals:
(a) A'C' + ABC + AC’ to three literals
= C' + ABC = (C + C')(C' + AB) = AB + C'
(b) (x'y' + z)' + z + xy + wz to three literals
(x'y' + z)' + z + xy + wz = (x'y')'z' + z + xy + wz
Note:
=[ (x + y)z' + z] + xy + wz (z+z’)(x+y+z) = xz+yz+z+xz’+z’y
= (z + z')(z + x + y) + xy + wz = z(x+y+1) + z’(x+y)
= z + wz + x + xy + y = z + z’(x+y)
= z(1 + w) + x(1 + y) + y
=x+y+z
(c) A'B(D' + C'D) + B(A + A’CD) To one literals
= B(A'D' + A'C'D + A + A'CD)
= B(A'D' + A + A'D(C + C') = B(A + A'(D' + D)) = B(A + A') = B
(d) (A' + C)(A' + C')(A + B + C’D) To four literals
= (A’ .A’ + A’C’+A’C+ CC')(A + B + C’D)
= [A’(1+C’+C)] (A+B+C’D)
= A'(A + B + C'D)
= AA' + A'B + A'C'D = A'(B + C’D)
(e) ABC'D + A'BD + ABCD To two literals
= AB(C + C')D + A'BD = ABD + A'BD = BD
2.8 Find the complement of F = wx + yz; then show that FF’ = 0 and F + F’ = 1.
● F' = (wx + yz)' = (wx)'(yz)' = (w' + x')(y' + z’)
● FF' = wx(w' + x')(y' + z') + yz(w' + x')(y' + z') = 0
● F + F' = wx + yz + (wx + yz)' = A + A' = 1 with A = wx + yz
2.9 Find the complement of the following expressions:
(a) xy' + x’y
(b) (a + c) (a + b')(a' + b + c’)
(c) z + z'(v'w + xy)
(a) F' = (xy' + x'y)' = (xy')'(x'y)' = (x' + y)(x + y') = xy + x’y’
(b) F' = [(a + c) (a + b')(a' + b + c')]' = (a + c)' + (a + b')' + (a' + b + c')’
=a'c' + a'b + ab’c
(c) F' = [z + z'(v'w + xy)]' = z’.[z+(v+w’)(x’+y’)]
= z'(v + w’ )( x' + y')
2.11 List the truth table of the function:
(a) F = xy + xy’ + y’z (b) F = bc + a’c’
(a) F(x, y, z) = Σ (1, 4, 5, 6, 7) (b) F(a, b, c) = Σ (0, 2, 3, 7)
2.12 We can perform logical operations on strings of bits by considering each pair of
corresponding bits separately (called bitwise operation). Given two eight‐bit strings A = 10110001
and B = 10101100, evaluate the eight‐bit result after the following logical operations:
(a) AND (b) OR (c) XOR (d) NOT A (e) NOT B
A = 1011_0001
B = 1010_1100
(a) A AND B = 1010_0000
(b) A OR B = 1011_1101
(c) A XOR B = 0001_1101
(d) NOT A = 0100_1110
(e) NOT B = 0101_0011
Draw logic diagrams to implement the following Boolean expressions:
(a) y = [(u + x’) (y’ + z)]
(b) y = (u xor y)’ + x
(c) y = (u’ + x’) (y + z’)
(d) y =(u’+x’)(y+z’)
(e) y = u + yz + uxy
(f) y = u + x + x’(u + y’)
2.14 Implement the Boolean function: F =xy + x'y' + y'z
(a) With AND, OR, and inverter gates.
(b) With OR and inverter gates.
(c) With AND and inverter gates.
(d) With NAND and inverter gates.
(e) With NOR and inverter gates.
Thanks
