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LP5018, LP5024
SLVSEB8B – OCTOBER 2018 – REVISED OCTOBER 2018

LP50xx 18-, 24-Channel, 12-Bit, PWM Ultralow-Quiescent-Current, I2C RGB LED Drivers
1 Features 2 Applications
1• Operating Voltage Range: LED Lighting, Indicator Lights, and Fun Lights for:
– VCC Range: 2.7 V to 5.5 V • Smart Speaker (With Voice Assistant)
– EN, SDA, and SCL Pins Compatible With • Smart Home Appliances
1.8-V, 3.3-V, and 5-V Power Rails • Video Doorbell
– Output Maximum Voltage: 6 V • Electronic Smart Lock
• 24 Constant-Current Sinks With High Precision • Smoke and Heat Detector
– 25.5 mA Maximum per Channel With VCC in • STB and DVR
Full Range • Smart Router
– 35 mA Maximum per Channel When VCC ≥ 3.3 • Handheld Device
V
– Device-to-Device Error: ±7%; Channel-to- 3 Description
Channel Error: ±7% In smart homes and other applications that utilize
• Ultralow Quiescent Current: human-machine-interaction, high-performance RGB
– Shutdown Mode: 1 µA (Maximum) With EN LED drivers are required. LED animation effects such
as flashing, breathing, and chasing greatly improve
Low
user experience, and minimal system noise is
– Power Saving Mode: 10 µA (Typical) With EN essential.
High and All LEDs Off for > 30 ms
The LP50xx device is an 18- or 24-channel constant
• Integrated 12-Bit, 29-kHz PWM Generator for current sink LED driver. The LP50xx device includes
Each Channel: integrated color mixing and brightness control, and
– Independent Color-Mixing Register Per pre-configuration simplifies the software coding
Channel process. Integrated 12-bit, 29 kHz PWM generators
for each channel enable smooth, vivid color for LEDs,
– Independent Brightness-Control Register Per
and eliminate audible noise.
RGB LED Module
– Optional Logarithmic- or Linear-Scale Device Information(1)
Brightness Control PART NUMBER PACKAGE BODY SIZE (NOM)
– Integrated 3-Phase PWM-Shifting Scheme LP5018
VQFN (32) 4.00 mm × 4.00 mm
• 3 Programmable Banks (R, G, B) for Easy LP5024
Software Control of Each Color (1) For all available packages, see the orderable addendum at
• 2 External Hardware Address Pins Allow the end of the data sheet.
Connecting up to 4 Devices
Simplified Schematic
• Broadcast Slave Address Allows Configuring
VCC
Multiple Devices Simultaneously VMCU CVCC
VLED
• Auto-Increment Allows Writing or Reading VCC
OUT0
Consecutive Registers Within One Transmission EN

• Up to 400-kHz Fast-Mode I2C Speed SDA

OUT1

SCL
OUT2

ADDR0

MCU ADDR1 LP5024

VCAP OUT21
CVCAP

OUT22
IREF

RIREF GND OUT23

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 17
2 Applications ........................................................... 1 8.5 Programming .......................................................... 18
3 Description ............................................................. 1 8.6 Register Maps ........................................................ 22
4 Revision History..................................................... 2 9 Application and Implementation ........................ 38
9.1 Application Information............................................ 38
5 Description (continued)......................................... 3
9.2 Typical Application ................................................. 38
6 Pin Configuration and Functions ......................... 4
10 Power Supply Recommendations ..................... 41
7 Specifications......................................................... 6
7.1 Absolute Maximum Ratings ...................................... 6 11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
7.2 ESD Ratings.............................................................. 6
11.2 Layout Examples................................................... 42
7.3 Recommended Operating Conditions....................... 6
7.4 Thermal Information .................................................. 6 12 Device and Documentation Support ................. 44
7.5 Electrical Characteristics........................................... 7 12.1 Related Links ........................................................ 44
7.6 Timing Requirements ................................................ 8 12.2 Receiving Notification of Documentation Updates 44
7.7 Typical Characteristics .............................................. 9 12.3 Community Resources.......................................... 44
12.4 Trademarks ........................................................... 44
8 Detailed Description ............................................ 11
12.5 Electrostatic Discharge Caution ............................ 44
8.1 Overview ................................................................. 11
12.6 Glossary ................................................................ 44
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11 13 Mechanical, Packaging, and Orderable
Information ........................................................... 45

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2018) to Revision B Page

• Added % after 100 in Parameter for IERR_DD and IERR_CC under OUTPUT STAGE................................................................. 7
• Changed value of "KIREF = 100" to "KIREF = 105" .................................................................................................................. 16

Changes from Original (October 2018) to Revision A Page

• first release of production-data data sheet ............................................................................................................................. 1

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5 Description (continued)
The LP50xx device controls each LED output with a 12-bit PWM resolution at 29-kHz switching frequency, which
helps achieve a smooth dimming effect and eliminates audible noise. The independent color mixing and intensity
control registers make the software coding straightforward. When targeting a fade-in, fade-out type breathing
effect, the global R, G, B bank control reduces the microcontroller loading significantly. The LP50xx device also
implements a PWM phase-shifting function to help reduce the input power budget when LEDs turn on
simultaneously.
The LP50xx device implements an automatic power-saving mode to achieve ultralow quiescent current. When
channels are all off for 30 ms, the device total power consumption is down to 10 µA, which makes the LP50xx
device a potential choice for battery-powered end equipment.

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6 Pin Configuration and Functions

LP5018 RSM Package

32-Pin VQFN With Exposed Thermal Pad
Top View

ADDR1

ADDR0
VCAP

IREF

VCC
SDA
SCL
EN
32

31

30

29

28

27

26

25
OUT0 1 24 NC

OUT1 2 23 NC

OUT2 3 22 NC

OUT3 4 21 NC
Exposed Thermal Pad (GND)
OUT4 5 20 NC

OUT5 6 19 NC

OUT6 7 18 OUT17

OUT7 8 17 OUT16
10

11

12

13

14

15

16
9
OUT8

OUT9

OUT10

OUT11

OUT12

OUT13

OUT14

OUT15

Not to scale

LP5024 RSM Package

32-Pin VQFN With Exposed Thermal Pad
Top View
ADDR1

ADDR0
VCAP

IREF

VCC
SDA
SCL
EN
32

31

30

29

28

27

26

25

OUT0 1 24 OUT23

OUT1 2 23 OUT22

OUT2 3 22 OUT21

OUT3 4 Exposed Thermal Pad 21 OUT20

(GND)
OUT4 5 20 OUT19

OUT5 6 19 OUT18

OUT6 7 18 OUT17

OUT7 8 17 OUT16
10

11

12

13

14

15

16
9
OUT8

OUT9

OUT10

OUT11

OUT12

OUT13

OUT14

OUT15

Not to scale

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Pin Functions
PIN
NO. I/O DESCRIPTION
NAME
LP5018 LP5024
ADDR0 25 25 — I2C slave-address selection pin. This pin must not be left floating.
ADDR1 26 26 — I2C slave-address selection pin. This pin must not be left floating.
EN 30 30 I Chip enable input pin
IREF 31 31 — Output current-reference global-setting pin
19, 20, 21,
NC — — No internal connection
22, 23, 24
OUT0 1 1 O Current sink output 0. If not used, this pin can be left floating.
OUT1 2 2 O Current sink output 1. If not used, this pin can be left floating.
OUT2 3 3 O Current sink output 2. If not used, this pin can be left floating.
OUT3 4 4 O Current sink output 3. If not used, this pin can be left floating.
OUT4 5 5 O Current sink output 4. If not used, this pin can be left floating.
OUT5 6 6 O Current sink output 5. If not used, this pin can be left floating.
OUT6 7 7 O Current sink output 6. If not used, this pin can be left floating.
OUT7 8 8 O Current sink output 7. If not used, this pin can be left floating.
OUT8 9 9 O Current sink output 8. If not used, this pin can be left floating.
OUT9 10 10 O Current sink output 9. If not used, this pin can be left floating.
OUT10 11 11 O Current sink output 10. If not used, this pin can be left floating.
OUT11 12 12 O Current sink output 11. If not used, this pin can be left floating.
OUT12 13 13 O Current sink output 12. If not used, this pin can be left floating.
OUT13 14 14 O Current sink output 13. If not used, this pin can be left floating.
OUT14 15 15 O Current sink output 14. If not used, this pin can be left floating.
OUT15 16 16 O Current sink output 15. If not used, this pin can be left floating.
OUT16 17 17 O Current sink output 16. If not used, this pin can be left floating.
OUT17 18 18 O Current sink output 17. If not used, this pin can be left floating.
OUT18 — 19 O Current sink output 18. If not used, this pin can be left floating.
OUT19 — 20 O Current sink output 19. If not used, this pin can be left floating.
OUT20 — 21 O Current sink output 20. If not used, this pin can be left floating.
OUT21 — 22 O Current sink output 21. If not used, this pin can be left floating.
OUT22 — 23 O Current sink output 22. If not used, this pin can be left floating.
OUT23 — 24 O Current sink output 23. If not used, this pin can be left floating.
SCL 29 29 I I2C bus clock line. If not used, this pin must be connected to GND or VCC.
SDA 28 28 I/O I2C bus data line. If not used, this pin must be connected to GND or VCC.
Internal LDO output pin, this pin must be connected to a 1-µF capacitor to
VCAP 32 32 —
GND. Place the capacitor as close to the device as possible.
VCC 27 27 I Input power.
GND GND — Exposed thermal pad also serves the ground pin for the device.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage on EN, IREF, OUTx, SCL, SDA, VCC –0.3 6 V
Voltage on ADDRx –0.3 VCC+0.3 V
Voltage on VCAP –0.3 2 V
Continuous power dissipation Internally limited
Junction temperature, TJ-MAX –40 125 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1500
V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage on VCC 2.7 5.5 V
Voltage on OUTx 0 5.5 V
Voltage on ADDRx, EN, SDA, SCL 0 5.5 V
Operating ambient temperature, TA –40 85 °C

7.4 Thermal Information

LP5018 or LP5024
(1)
THERMAL METRIC RSM (QFN) UNIT
32 PINS
RθJA Junction-to-ambient thermal resistance 36.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34.8 °C/W
RθJB Junction-to-board thermal resistance 15.9 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 16 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.3 °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and ICPackage Thermal Metrics .

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7.5 Electrical Characteristics

over operating ambient temperature range (–40°C < TA<85°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VCC)
VVCC Supply voltage 2.7 5.5 V
Shutdown supply current VEN = 0 V 0.2 1
µA
Standby supply current VEN = 3.3 V, Chip_EN = 0 (bit) 6 10
IVCC Normal-mode supply current With 10-mA LED current per OUTx 5 8 mA
VEN = 3.3 V, Chip_EN = 1 (bit),
Power-save mode supply current Power_Save_EN = 1 (bit), all the 6 10 µA
LEDs off duration > tPSM
VUVR Undervoltage restart VVCC rising 2.5 V
VUVF Undervoltage shutdown VVCC falling 2 V
VUV_HYS Undervoltage shutdown hysteresis 0.2 V
OUTPUT STAGE (OUTx)
Maximum sink current VVCC in full range,
(OUT0–OUTx) (For LP5024, x = 23. Max_Current_Option = 0 (bit), PWM 25.5
For LP5018, x = 17.) = 100%
IMAX mA
Maximum sink current
VVCC ≥ 3.3 V, Max_Current_Option
(OUT0–OUTx) (For LP5024, x = 23. 35
= 1 (bit), PWM = 100%
For LP5018, x = 17.)
Internal sink current limit VVCC in full range,
(OUT0–OUTx) (For LP5024, x = 23. Max_Current_Option = 0 (bit), VIREF 35 55 80
For LP5018, x = 17.) =0V
ILIM mA
Internal sink current limit VVCC ≥ 3.3V,
(OUT0–OUTx) (For LP5024, x = 23. Max_Current_Option=1 (bit), VIREF = 40 75 120
For LP5018, x = 17.) 0V
Leakage current (OUT0–OUTx) (For
Ilkg LP5024, x = 23. For LP5018, x = PWM = 0% 0.1 1 µA
17.)
All channels' current set to 10 mA.
Device to device current error,
IERR_DD PWM = 100%. Already includes the –7% 7%
IERR_DD=(IAVE-ISET)/ISET×100%
VIREF and KIREF tolerance
All channels' current set to 10 mA.
Channel to channel current error,
IERR_CC PWM = 100%. Already includes the –7% 7%
IERR_CC=(IOUTX-IAVE)/IAVE×100%
VIREF and KIREF tolerance
VIREF IREF voltage 0.7 V
KIREF IREF ratio 105
ƒPWM PWM switching frequency 21 29 kHz
VVCC in full range,
Max_Current_Option = 0 (bit), output
current set to 20 mA, the voltage 0.25 0.35
when the LED current has dropped
VSAT Output saturation voltage 5% V
VVCC ≥ 3.3 V, Max_Current_Option
= 1 (bit), output current set to 20
0.3 0.4
mA, the voltage when the LED
current has dropped 5%
LOGIC INPUTS (EN, SCL, SDA, ADDRx)
VIL Low level input voltage 0.4 V
VIH High level input voltage 1.4 V
ILOGIC Input current –1 1 µA
VSDA SDA output low level IPULLUP = 5 mA 0.4 V
PROTECTION CIRCUITS
Thermal-shutdown junction
T(TSD) 160 °C
temperature

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Electrical Characteristics (continued)

over operating ambient temperature range (–40°C < TA<85°C) (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Thermal shutdown temperature
T(HYS) 15 °C
hysteresis

7.6 Timing Requirements

over operating ambient temperature range (-40°C < TA<85°C) (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
ƒOSC Internal oscillator frequency 15 MHz
tPSM Power save mode deglitch time 20 30 40 ms
tEN_H EN first rising edge until first I2C access 500 µs
2
tEN_L EN first falling edge until first I C reset 3 µs
ƒSCL I2C clock frequency 400 kHz
1 Hold time (repeated) START condition 0.6 µs
2 Clock low time 1.3 µs
3 Clock high time 600 ns
4 Setup time for a repeated START condition 600 ns
5 Data hold time 0 ns
6 Data setup time 100 ns
7 Rise time of SDA and SCL 20 + 0.1 Cb 300 ns
8 Fall time of SDA and SCL 15 + 0.1 Cb 300 ns
9 Setup time for STOP condition 600 ns
Bus free time between a STOP and a START
10 1.3 µs
condition
Capacitive load parameter for each bus line Load
Cb 10 200 pF
of 1 pF corresponds to one nanosecond.

Figure 1. I2C Timing Parameters

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7.7 Typical Characteristics

35 40
32.5
30 35
27.5
Output Current (mA)

30

Output Current (mA)

25
22.5
20 25
17.5
5-mA Average Current
15 20
10-mA Average Current
12.5 25-mA Average Current
10 15 35-mA Average Current
7.5
5 10
2.5
0 5
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90
RIREF(k:) RIRE
Ambient Temperature (qC) CURR
VCC = 3.3 V

Figure 2. IOUT Target vs RIREF Figure 3. Output Current vs Temperature

40 1.65

1.35
35
1.05
30
Outout Current (mA)

0.75
Accuracy (%)

25 0.45 Minimum at 5 mA Minimum at 25 mA

5-mA Average Current Maximum at 5 mA Maximum at 25 mA
20 0.15
10-mA Average Current Minimum at 10mA Minimum at 35 mA
25-mA Average Current -0.15 Maximum at 10 mA Maximum at 35 mA
15 35-mA Average Current
-0.45
10
-0.75

5 -1.05
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 -40 -20 0 20 40 60 80 90
Ambient Temperature (qC) CURR
Air Temperature (qC) C2C3
VCC = 5 V VCC = 3.3 V

Figure 4. Output Current vs Temperature Figure 5. Channel-to-Channel Current Accuracy

1.6 0.055
50-PA IREF 200-PA IREF 350-PA IREF
0.05
100-PA IREF 250-\sm}A IREF
1.2
0.045 150-PA IREF 300-PA IREF

0.8 0.04
Output Current (A)

0.035
Accuracy (%)

0.4 0.03
Minimum at 5 mA Minimum at 25 mA
Maximum at 5 mA Maximum at 25 mA 0.025
0 Minimum at 10mA Minimum at 35 mA
Maximum at 10 mA Maximum at 35 mA 0.02
-0.4 0.015
0.01
-0.8
0.005
-1.2 0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Ambient Tempeature (qC) C2C5
Output Pin Voltage (V) VSAT
VCC = 5 V VCC = 3.3 V

Figure 6. Channel-to-Channel Current Accuracy vs Figure 7. OUT Pin Voltage vs Current

Temperature

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Typical Characteristics (continued)

0.055
50-PA IREF 200-PA IREF 350-PA IREF
0.05
100-PA IREF 250-PA IREF
0.045 150-PA IREF 300-PA IREF
0.04

Output Current (A)

0.035
0.03
0.025
0.02
0.015
0.01
0.005
0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Output Pin Volatge (V) VSAT
VCC = 5 V

Figure 8. OUT Pin Voltage vs Output Current

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8 Detailed Description

8.1 Overview
The LP50xx device is an 18- or 24-channel constant-current-sink LED driver. The LP50xx device includes all
necessary power rails, an on-chip oscillator, and a two-wire serial I2C interface. The maximum constant-current
value of all channels is set by a single external resistor. Two hardware address pins allow up to four devices on
the same bus. An automatic power-saving mode is implemented to keep the total current consumption under 10
µA, which makes the LP50xx device a potential choice for battery-powered end-equipment.
The LP50xx device is optimized for RGB LEDs regarding to both live effects and software efforts. The LP50xx
device controls each LED output with 12-bit PWM resolution at 29-kHz switching frequency, which helps achieve
a smooth dimming effect and eliminates audible noise. The independent color-mixing and intensity-control
registers make the software coding straightforward. When targeting a fade-in, fade-out type breathing effect, the
global RGB bank control reduces the microcontroller loading significantly. The LP50xx device also implements a
PWM phase-shifting function to help reduce the input power budget when LEDs turn on simultaneously.

8.2 Functional Block Diagram

VCC VLED

VCC
Bandgap
OUT0

OUT1
V1P8
VCAP LDO

12 Bits OUT2
29 kHz
Oscillator
PWM
15MHz
Generators
EN

SDA OUT21
Digital
SCL Interface
Digital Control
OUT22
ADDR0

ADDR1
OUT23

IREF
IREF Setting Current

GND
Thermal Shutdown

8.3 Feature Description

8.3.1 PWM Control for Each Channel
Most traditional LED drivers are designed for the single-color LEDs, in which the high-resolution PWM generator
is used for intensity control only. However, for RGB LEDs, both the color mixing and intensity control should be
addressed to achieve the target effect. With the traditional solution, the users must handle the color mixing and
intensity control simultaneously with a single PWM register. Several undesired effects occur: the limited dimming
steps, the complex software design, and the color distortion when using a logarithmic scale control.

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Feature Description (continued)

The LP50xx device is designed with independent color mixing and intensity control, which makes the RGB LED
effects fancy and the control experience straightforward. With the inputs of the color-mixing register and the
intensity-control register, the final PWM generator output for each channel is 12-bit resolution and 29-kHz
dimming frequency, which helps achieve a smooth dimming effect and eliminates audible noise. See Figure 9.

Color-Mixing Brightness-Control PWM Generators

8 Bits Color 12 Bits / 29KHz PWM OUT0

8 Bits Color 8 Bits Brightness 12 Bits / 29KHz PWM OUT1

8 Bits Color 12 Bits / 29KHz PWM OUT2

8 Bits Color 12 Bits / 29KHz PWM OUT21

8 Bits Color 8 Bits Brightness 12 Bits / 29KHz PWM OUT22

8 Bits Color 12 Bits / 29KHz PWM OUT23

Figure 9. PWM Control Scheme for Each Channel

8.3.1.1 Independent Color Mixing Per RGB LED Module

Each output channel has its own individual 8-bit color-setting register (OUTx_COLOR). The device allows every
RGB LED module to achieve >16 million (256 × 256 × 256) color-mixing.

8.3.1.2 Independent Intensity Control Per RGB LED Module

When color is fixed, the independent intensity-control is used to achieve accurate and flexible dimming control for
every RGB LED module.

8.3.1.2.1 Intensity-Control Register Configuration

Every three consecutive output channels are assigned to their respective intensity-control register
(LEDx_BRIGHTNESS). For example, OUT0, OUT1, and OUT2 are assigned to LED0_BRIGHTNESS, so it is
recommended to connect the RGB LEDs in the sequence as shown in Table 1. The LP50xx device allows 256-
step intensity control for each RGB LED module, which helps achieve a smooth dimming effect.
Keeping FFh (default value) in the LED0_BRIGHTNESS register results in 100% dimming duty cycle. With this
setting, users can just configure the color mixing register by channel to achieve the target dimming effect in a
single-color LED application.

8.3.1.2.2 Logarithmic- or Linear-Scale Intensity Control

For human-eye-friendly visual performance, a logarithmic-scale dimming curve is usually implemented in LED
drivers. However, for RGB LEDs, if using a single register to achieve both color mixing and intensity control,
color distortion can be observed easily when using a logarithmic scale. The LP50xx device, with independent
color-mixing and intensity-control registers, implements the logarithmic scale dimming control inside the intensity
control function, which solves the color distortion issue effectively. See Figure 10. Also, the LP50xx device allows
users to configure the dimming scale either logarithmically or linearly through the global Log_Scale_EN register.
If a special dimming curve is desired, using the linear scale with software correction is the most flexible
approach. See Figure 11.

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Feature Description (continued)

Brightness Control

8 Bits Brightness

Linear OR Logarithmic

Log_Scale_EN

8 Bits Brightness

Linear OR Logarithmic

Figure 10. Logarithmic- or Linear-Scale Intensity Control

Linear Scale Dimming Curve Logarithmic Scale Dimming Curve

100 % 100 %

80 % 80 %
PWM Output Duty

PWM Output Duty

60 % 60 %

40 % 40 %

20 % 20 %

0% 0%
0 32 64 96 128 160 192 224 255 0 32 64 96 128 160 192 224 255
LEDx_BRIGHTNESS Register Input LEDx_BRIGHTNESS Register Input

Figure 11. Logarithmic vs Linear Dimming Curve

8.3.1.3 12-Bit, 29-kHz PWM Generator Per Channel

8.3.1.3.1 PWM Generator

With the inputs of the color mixing and the intensity control, the final output PWM duty cycle is defined as the
product obtained by multiplying the color-mixing register value by the related intensity-control register value. The
final output PWM duty cycle has 12 bits of control accuracy, which is achieved by a 9 bits of pure PWM
resolution and 3 bits of digital dithering control. For 3-bit dithering, every eighth pulse is made 1 LSB longer to
increase the average value by 1 / 8th. The LP50xx device allows users to enable or disable the dithering function
through the PWM_Dithering_EN register. When enabled (default), the output PWM duty-cycle accuracy is 12
bits. When disabled, the output PWM duty-cycle accuracy is 9 bits.
To eliminate the audible noise due to the PWM switching, the LP50xx device sets the PWM switching frequency
at 29-kHz, above the 20-kHz human hearing range.

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Feature Description (continued)

8.3.1.4 PWM Phase-Shifting
A PWM phase-shifting scheme allows delaying the time when each LED driver is active. When the LED drivers
are not activated simultaneously, the peak load current from the pre-stage power supply is significantly
decreased. The scheme also reduces input-current ripple and ceramic-capacitor audible ringing. LED drivers are
grouped into three different phases.
• Phase 1—the rising edge of the PWM pulse is fixed. The falling edge of the pulse is changed when the duty
cycle changes. Phase 1 is applied to LED0, LED3, …, LED21.
• Phase 2—the middle point of the PWM pulse is fixed. The pulse spreads in both directions when the PWM
duty cycle is increased. Phase 2 is applied to LED1, LED4, …, LED22.
• Phase 3—the falling edge of the PWM pulse is fixed. The rising edge of the pulse is changed when the duty
cycle changes. Phase 3 is applied to LED2, LED5, …, LED23.
Cycle Time

LED0
LED3
Phase 1
LED[3h (n-1)]

LED1
LED4
Phase 2
LED[3h (n-1)+1]

LED2
LED5
Phase 3
LED[3h (n-1)+2]

Phase 1
Phase 2
Phase 3

Figure 12. PWM Phase-Shifting

8.3.2 LED Bank Control

For most LED-animation effects, like blinking and breathing, all the RGB LEDs have the same lighting pattern.
Instead of controlling the individual LED separately, which occupies the microcontroller resources heavily, the
LP50xx device provides an easy coding approach, the LED bank control.
Each channel can be configured as either independent control or bank control through the LEDx_Bank_EN
register. When LEDx_Bank_EN = 0 (default), the LED is controlled independently by the related color-mixing and
intensity-control registers. When LEDx_Bank_EN = 1, the LP50xx device drives the LEDs in LED bank-control
mode. The LED bank has its own independent PWM control scheme, which is the same structure as the PWM
scheme of each channel. See PWM Control for Each Channel for more details. When a channel is configured in
LED bank-control mode, the related color mixing and intensity control is governed by the bank control registers
(BANK_A_COLOR, BANK_B_COLOR, BANK_C_COLOR, and BANK_BRIGHTNESS) regardless of the inputs
on its own color-mixing and intensity-control registers.

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Feature Description (continued)

Bank Color-Mixing Bank Brightness-Control Bank PWM Generators

Bank A: 8 Bits Color 12 Bits / 29kHz PWM

Bank B: 8 Bits Color 8 Bits Brightness 12 Bits / 29kHz PWM

Bank C: 8 Bits Color 12 Bits / 29kHz PWM

Figure 13. Bank PWM Control Scheme

Table 1. Bank Number and LED Number Assignment

OUT NUMBER BANK Number RGB LED MODULE NUMBER
OUT0 Bank A
OUT1 Bank B LED0
OUT2 Bank C
OUT3 Bank A
OUT4 Bank B LED1
OUT5 Bank C
OUT6 Bank A
OUT7 Bank B LED2
OUT8 Bank C
OUT9 Bank A
OUT10 Bank B LED3
OUT11 Bank C
OUT12 Bank A
OUT13 Bank B LED4
OUT14 Bank C
OUT15 Bank A
OUT16 Bank B LED5
OUT17 Bank C
OUT18 (LP5024 only) Bank A
OUT19 (LP5024 only) Bank B LED6
OUT20 (LP5024 only) Bank C
OUT21 (LP5024 only) Bank A
OUT22 (LP5024 only) Bank B LED7
OUT23 (LP5024 only) Bank C

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With the bank control configuration, the LP50xx device enables users to achieve smooth and live LED effects
globally with an ultrasimple software effort. Figure 14 shows an example using LED0 as an independent RGB
indicator and others with group breathing effect.

Bank A
CH3/6/9/12/15/18/21

Independent Bank B
Ch0/1/2 CH4/7/10/13/16/19/22

Bank C
CH5/8/11/14/17/20/23

Figure 14. Bank PWM Control Example

8.3.3 Current Range Setting

The constant-current value (ISET) of all 24 channels is set by a single external resistor, RIREF. The value of RIREF
can be calculated by Equation 1.
VIREF
RIREF =KIREF ×
ISET
where:
• KIREF = 105
• VIREF = 0.7 V (1)
With the IREF pin floating, the output current is close to zero. With the IREF pin shorted to GND, the LP50xx
device provides internal current-limit protection, and the output-channel maximum current is limited to ILIM.
The LP50xx device supports two levels of maximum output current, IMAX.
• When VCC is in the range from 2.7 V to 5.5 V, and the Max_Current_Option (bit) = 0, IMAX = 25.5 mA.
• When VCC is in the range from 3.3 V to 5.5 V, and the Max_Current_Option (bit) = 1, IMAX = 35 mA.

8.3.4 Automatic Power-Save Mode

When all the LED outputs are inactive, the LP50xx device is able to enter power-save mode automatically, thus
lowering idle-current consumption down to 10 μA (typical). Automatic power-save mode is enabled when register
bit Power_Save_EN = 1 (default) and all the LEDs are off for a duration of >30 ms. Almost all analog blocks are
powered down in power-save mode. If any I2C command to the device occurs, the LP50xx device returns to
NORMAL mode.

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8.3.5 Protection Features

8.3.5.1 Thermal Shutdown

The LP50xx device implements a thermal shutdown mechanism to protect the device from damage due to
overheating. When the junction temperature rises to 160°C (typical), the device switches into shutdown mode.
The LP50xx device releases thermal shutdown when the junction temperature of the device is reduced to 145°C
(typical).

8.3.5.2 UVLO
The LP50xx device has an internal comparator that monitors the voltage at VCC. When VCC is below VUVF, reset
is active and the LP50xx device is in the INITIALIZATION state.

8.4 Device Functional Modes

VCC Power Up

EN = L
SHUTDOWN From all states

EN = H

RESET = FF or UVLO = H
INITIALIZATION From all states

STANDBY

Chip_EN = 0 Chip_EN = 1

I2C Command TSD=H

THERMAL
POWER SAVE NORMAL
SHUTDOWN
TSD=L
Power_Save_EN =1 and
All LEDs off > 30ms

Figure 15. Functional Modes

• INITIALIZATION: The device enters into INITIALIZATION mode when EN = H. In this mode, all the registers
are reset. Entry can also be from any state, if the RESET (register) = FFh or UVLO is active.
• NORMAL: The device enters the NORMAL mode when Chip_EN (register) = 1. ICC is 10 mA (typ.).
• POWER SAVE: The device automatically enters the POWER SAVE mode when Power_Save_EN (register) =
1 and all the LEDs are off for a duration of >30 ms. In POWER SAVE mode, analog blocks are disabled to
minimize power consumption, but the registers retain the data and keep it available via I2C. ICC is 10 µA (typ.).
In case of any I2C command to this device, it returns to the NORMAL mode.
• SHUTDOWN: The device enters into SHUTDOWN mode from all states on VCC power up or when EN = L.
ICC is < 1 µA (max).
• STANDBY: The device enters the STANDBY mode when Chip_EN (register) = 0. In this mode, all the OUTx
pins are shut down, but the registers retain the data and keep it available via I2C. STANDBY is the low-
power-consumption mode, when all circuit functions are disabled. ICC is 10 µA (typ.).
• THERMAL SHUTDOWN: The device automatically enters the THERMAL SHUTDOWN mode when the

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Device Functional Modes (continued)

junction temperature exceeds 160°C (typical). In this mode, all the OUTx outputs are shut down. If the
junction temperature decreases below 145°C (typical), the device returns to the NORMAL mode.

8.5 Programming
8.5.1 I2C Interface
The I2C-compatible two-wire serial interface provides access to the programmable functions and registers on the
device. This protocol uses a two-wire interface for bidirectional communications between the devices connected
to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL). Every device on
the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates
or receives the serial clock, SCL. The SCL and SDA lines should each have a pullup resistor placed somewhere
on the line and remain HIGH even when the bus is idle.

8.5.1.1 Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state
of the data line can only be changed when the clock signal is LOW.

Figure 16. Data Validity

8.5.1.2 Start and Stop Conditions

START and STOP conditions classify the beginning and the end of the data transfer session. A START condition
is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. A STOP condition is
defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates
START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP
condition. During data transmission, the bus master can generate repeated START conditions. First START and
repeated START conditions are functionally equivalent.

Figure 17. Start and Stop Conditions

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Programming (continued)
8.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most-significant bit (MSB) being transferred first.
Each byte of data must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by
the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls
down the SDA line during the ninth clock pulse, signifying an acknowledge. The device generates an
acknowledge after each byte has been received.
There is one exception to the acknowledge-after-every-byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1
indicates a READ. The second byte selects the register to which the data is written. The third byte contains data
to write to the selected register.

Figure 18. Acknowledge and Not Acknowledge on I2C Bus

8.5.1.4 I2C Slave Addressing

The device slave address is defined by connecting GND or VCC to the ADDR0 and ADDR1 pins. A total of four
independent slave addresses can be realized by combinations when GND or VCC is connected to the ADDR0
and ADDR1 pins (see Table 2 and Table 3).
The device responds to a broadcast slave address regardless of the setting of the ADDR0 and ADDR1 pins.
Global writes to the broadcast address can be used for configuring all devices simultaneously. The device
supports global read using a broadcast address; however, the data read is only valid if all devices on the I2C bus
contain the same value in the addressed register.

Table 2. Slave-Address Combinations

SLAVE ADDRESS
ADDR1 ADDR0
INDEPENDENT BROADCAST
GND GND 010 1000
GND VCC 010 1001
011 1100
VCC GND 010 1010
VCC VCC 010 1011

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Table 3. Chip Address

SLAVE ADDRESS R/W
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Independent 0 1 0 1 0 ADDR1 ADDR0 1 or 0
Broadcast 0 1 1 1 1 0 0 1 or 0

8.5.1.5 Control-Register Write Cycle

• The master device generates a start condition.
• The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).
• The slave device sends an acknowledge signal if the slave address is correct.
• The master device sends the control register address (8 bits).
• The slave device sends an acknowledge signal.
• The master device sends the data byte to be written to the addressed register.
• The slave device sends an acknowledge signal.
• If the master device sends further data bytes, the control register address of the slave is incremented by 1
after the acknowledge signal. To reduce program load time, the device supports address auto incrementation.
The register address is incremented after each 8 data bits.
• The write cycle ends when the master device creates a stop condition.

Figure 19. Write Cycle

8.5.1.6 Control-Register Read Cycle

• The master device generates a start condition.
• The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).
• The slave device sends an acknowledge signal if the slave address is correct.
• The master device sends the control register address (8 bits).
• The slave device sends an acknowledge signal.
• The master device generates a repeated-start condition.
• The master device sends the slave address (7 bits) and the data direction bit (R/W = 1).
• The slave device sends an acknowledge signal if the slave address is correct.
• The slave device sends the data byte from the addressed register.
• If the master device sends an acknowledge signal, the control-register address is incremented by 1. The
slave device sends the data byte from the addressed register. To reduce program load time, the device
supports address auto incrementation. The register address is incremented after each 8 data bits.
• The read cycle ends when the master device does not generate an acknowledge signal after a data byte and
generates a stop condition.

Figure 20. Read Cycle

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8.5.1.7 Auto-Increment Feature

The auto-increment feature allows writing or reading several consecutive registers within one transmission. For
example, when an 8-bit word is sent to the device, the internal address index counter is incremented by 1, and
the next register is written. The auto-increment feature is enabled by default and can be disabled by setting the
Auto_Incr_EN bit = 0 in the DEVICE_CONFIG1 register. The auto-increment feature is applied for the full register
address from 0h to FFh.

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8.6 Register Maps

Table 4 lists the memory-mapped registers of the device.

Table 4. Register Maps

REGISTER DEF-
ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0
NAME AULT
DEVICE_
00h R/W RESERVED Chip_EN RESERVED 00h
CONFIG0
DEVICE_ Power_Save_ PWM_ Max_Current_
01h R/W RESERVED Log_Scale_EN Auto_Incr_EN LED_Global Off 3Ch
CONFIG1 EN Dithering_EN Option
LED7_Bank_EN LED6_Bank_EN
LED_CONFIG0 02h R/W (Only for (Only for LED5_Bank_EN LED4_Bank_EN LED3_Bank_EN LED2_Bank_EN LED1_Bank_EN LED0_Bank_EN 00h
LP5024) LP5024)
BANK_
03h R/W Bank_Brightness FFh
BRIGHTNESS
BANK_A_
04h R/W Bank_A_Color 00h
COLOR
BANK_B_
05h R/W Bank_B_Color 00h
COLOR
BANK_C_
06h R/W Bank_C_Color 00h
COLOR
LED0_
07h R/W LED0_Brightness FFh
BRIGHTNESS
LED1_
08h R/W LED1_Brightness FFh
BRIGHTNESS
LED2_
09h R/W LED2_Brightness FFh
BRIGHTNESS
LED3_
0Ah R/W LED3_Brightness FFh
BRIGHTNESS
LED4_
0Bh R/W LED4_Brightness FFh
BRIGHTNESS
LED5_
0Ch R/W LED5_Brightness FFh
BRIGHTNESS
LED6_ LED6_Brightness
0Dh R/W FFh
BRIGHTNESS (Only for LP5024)
LED7_ LED7_Brightness
0Eh R/W FFh
BRIGHTNESS (Only for LP5024)
OUT0_COLOR 0Fh R/W OUT0_Color 00h
OUT1_COLOR 10h R/W OUT1_Color 00h
OUT2_COLOR 11h R/W OUT2_Color 00h
OUT3_COLOR 12h R/W OUT3_Color 00h

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Register Maps (continued)

Table 4. Register Maps (continued)
REGISTER DEF-
ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0
NAME AULT
OUT4_COLOR 13h R/W OUT4_Color 00h
OUT5_COLOR 14h R/W OUT5_Color 00h
OUT6_COLOR 15h R/W OUT6_Color 00h
OUT7_COLOR 16h R/W OUT7_Color 00h
OUT8_COLOR 17h R/W OUT8_Color 00h
OUT9_COLOR 18h R/W OUT9_Color 00h
OUT10_COLOR 19h R/W OUT10_Color 00h
OUT11_COLOR 1Ah R/W OUT11_Color 00h
OUT12_COLOR 1Bh R/W OUT12_Color 00h
OUT13_COLOR 1Ch R/W OUT13_Color 00h
OUT14_COLOR 1Dh R/W OUT14_Color 00h
OUT15_COLOR 1Eh R/W OUT15_Color 00h
OUT16_COLOR 1Fh R/W OUT16_Color 00h
OUT17_COLOR 20h R/W OUT17_Color 00h
OUT18_Color
OUT18_COLOR 21h R/W 00h
(Only for LP5024)
OUT19_Color
OUT19_COLOR 22h R/W 00h
(Only for LP5024)
OUT20_Color
OUT20_COLOR 23h R/W 00h
(Only for LP5024)
OUT21_Color
OUT21_COLOR 24h R/W 00h
(Only for LP5024)
OUT22_Color
OUT22_COLOR 25h R/W 00h
(Only for LP5024)
OUT23_Color
OUT23_COLOR 26h R/W 00h
(Only for LP5024)
RESET 27h W Reset 00h

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Table 5. Access Type Codes

ACCESS TYPE CODE DESCRIPTION
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default
value

8.6.1 DEVICE_CONFIG0 (Address = 0h) [reset = 0h]

DEVICE_CONFIG0 is shown in Figure 21 and described in Table 6.
Return to Table 4.
Figure 21. DEVICE_CONFIG0 Register
7 6 5 4 3 2 1 0
RESERVED Chip_EN RESERVED
R/W-0h R/W-0h R/W-0h

Table 6. DEVICE_CONFIG0 Register Field Descriptions

Bit Field Type Reset Description
7 RESERVED R/W 0h Reserved
6 Chip_EN R/W 0h 1 = LP50xx enabled
0 = LP50xx not enabled
5–0 RESERVED R/W 0h Reserved

8.6.2 DEVICE_CONFIG1 (Address = 1h) [reset = 3Ch]

DEVICE_CONFIG1 is shown in Figure 22 and described in Table 7.
Return to Table 4.
Figure 22. DEVICE_CONFIG1 Register
7 6 5 4 3 2 1 0
RESERVED Log_Scale_EN Power_Save_E Auto_Incr_EN PWM_Dithering Optional_Headr LED_Global Off
N _EN oom
R/W-0h R/W-1h R/W-1h R/W-1h R/W-1h R/W-0h R/W-0h

Table 7. DEVICE_CONFIG1 Register Field Descriptions

Bit Field Type Reset Description
7–6 RESERVED R/W 0h Reserved
5 Log_Scale_EN R/W 1h 1 = Logarithmic scale dimming curve enabled
0 = Linear scale dimming curve enabled
4 Power_Save_EN R/W 1h 1 = Automatic power-saving mode enabled
0 = Automatic power-saving mode not enabled
3 Auto_Incr_EN R/W 1h 1 = Automatic increment mode enabled
0 = Automatic increment mode not enabled
2 PWM_Dithering_EN R/W 1h 1 = PWM dithering mode enabled
0 = PWM dithering mode not enabled
1 Max_Current_Option R/W 0h 1 = Output maximum current IMAX = 35 mA.
0 = Output maximum current IMAX = 25.5 mA.
0 LED_Global Off R/W 0h 1 = Shut down all LEDs
0 = Normal operation

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8.6.3 LED_CONFIG0 (Address = 2h) [reset = 00h]

LED_CONFIG0 is shown in Figure 23 and described in Table 8.
Return to Table 4.
Figure 23. LED_CONFIG0 Register
7 6 5 4 3 2 1 0
LED7_Bank_E LED6_Bank_E LED5_Bank_E LED4_Bank_E LED3_Bank_E LED2_Bank_E LED1_Bank_E LED0_Bank_E
N N N N N N N N
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h

Table 8. LED_CONFIG0 Register Field Descriptions

Bit Field Type Reset Description
7 LED7_Bank_EN R/W 0h 1 = LED7 bank control mode enabled
0 = LED7 independent control mode enabled
6 LED6_Bank_EN R/W 0h 1 = LED6 bank control mode enabled
0 = LED6 independent control mode enabled
5 LED5_Bank_EN R/W 0h 1 = LED5 bank control mode enabled
0 = LED5 independent control mode enabled
4 LED4_Bank_EN R/W 0h 1 = LED4 bank control mode enabled
0 = LED4 independent control mode enabled
3 LED3_Bank_EN R/W 0h 1 = LED3 bank control mode enabled
0 = LED3 Independent control mode enabled
2 LED2_Bank_EN R/W 0h 1 = LED2 bank control mode enabled
0 = LED2 independent control mode enabled
1 LED1_Bank_EN R/W 0h 1 = LED1 bank control mode enabled
0 = LED1 independent control mode enabled
0 LED0_Bank_EN R/W 0h 1 = LED0 bank control mode enabled
0 = LED0 independent control mode enabled

8.6.4 BANK_BRIGHTNESS (Address = 3h) [reset = FFh]

BANK_BRIGHTNESS is shown in Figure 24 and described in Table 9.
Return to Table 4.
Figure 24. BANK_BRIGHTNESS Register
7 6 5 4 3 2 1 0
Bank_Brightness
R/W-FFh

Table 9. BANK_BRIGHTNESS Register Field Descriptions

Bit Field Type Reset Description
7–0 Bank_Brightness R/W FFh FFh = 100% of full brightness
...
80h = 50% of full brightness
...
00h = 0% of full brightness

8.6.5 BANK_A_COLOR (Address = 4h) [reset = 00h]

BANK_A_COLOR is shown in Figure 25 and described in Table 10.
Return to Table 4.

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Figure 25. BANK_A_COLOR Register

7 6 5 4 3 2 1 0
Bank_A_Color
R/W-0h

Table 10. BANK_A_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 Bank_A_Color R/W 0h FFh = The color mixing percentage is 100%.
...
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.

8.6.6 BANK_B_COLOR (Address = 5h) [reset = 00h]

BANK_B_COLOR is shown in Figure 26 and described in Table 11.
Return to Table 4.
Figure 26. BANK_B_COLOR Register
7 6 5 4 3 2 1 0
Bank_B_Color
R/W-0h

Table 11. BANK_B_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 Bank_B_Color R/W 0h FFh = The color mixing percentage is 100%.
...
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.

8.6.7 BANK_C_COLOR (Address = 6h) [reset = 00h]

BANK_C_COLOR is shown in Figure 27 and described in Table 12.
Return to Table 4.
Figure 27. BANK_C_COLOR Register
7 6 5 4 3 2 1 0
Bank_C_Color
R/W-0h

Table 12. BANK_C_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 Bank_C_Color R/W 0h FFh = The color mixing percentage is 100%.
...
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.

8.6.8 LED0_BRIGHTNESS (Address = 7h) [reset = FFh]

LED0_BRIGHTNESS is shown in Figure 28 and described in Table 13.
Return to Table 4.

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Figure 28. LED0_BRIGHTNESS Register

7 6 5 4 3 2 1 0
LED0_Brightness
R/W-FFh

Table 13. LED0_BRIGHTNESS Register Field Descriptions

Bit Field Type Reset Description
7–0 LED0_Brightness R/W FFh FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity

8.6.9 LED1_BRIGHTNESS (Address = 8h) [reset = FFh]

LED1_BRIGHTNESS is shown in Figure 29 and described in Table 14.
Return to Table 4.
Figure 29. LED1_BRIGHTNESS Register
7 6 5 4 3 2 1 0
LED1_Brightness
R/W-FFh

Table 14. LED1_BRIGHTNESS Register Field Descriptions

Bit Field Type Reset Description
7–0 LED1_Brightness R/W FFh FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity

8.6.10 LED2_BRIGHTNESS (Address = 9h) [reset = FFh]

LED2_BRIGHTNESS is shown in Figure 30 and described in Table 15.
Return to Table 4.
Figure 30. LED2_BRIGHTNESS Register
7 6 5 4 3 2 1 0
LED2_Brightness
R/W-FFh

Table 15. LED2_BRIGHTNESS Register Field Descriptions

Bit Field Type Reset Description
7–0 LED2_Brightness R/W FFh FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity

8.6.11 LED3_BRIGHTNESS (Address = 0Ah) [reset = FFh]

LED3_BRIGHTNESS is shown in Figure 31 and described in Table 16.
Return to Table 4.

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Figure 31. LED3_BRIGHTNESS Register

7 6 5 4 3 2 1 0
LED3_Brightness
R/W-FFh

Table 16. LED3_BRIGHTNESS Register Field Descriptions

Bit Field Type Reset Description
7–0 LED3_Brightness R/W FFh FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity

8.6.12 LED4_BRIGHTNESS (Address = 0Bh) [reset = FFh]

LED4_BRIGHTNESS is shown in Figure 32 and described in Table 17.
Return to Table 4.
Figure 32. LED4_BRIGHTNESS Register
7 6 5 4 3 2 1 0
LED4_Brightness
R/W-FFh

Table 17. LED4_BRIGHTNESS Register Field Descriptions

Bit Field Type Reset Description
7–0 LED4_Brightness R/W FFh FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity

8.6.13 LED5_BRIGHTNESS (Address = 0Ch) [reset = FFh]

LED5_BRIGHTNESS is shown in Figure 33 and described in Table 18.
Return to Table 4.
Figure 33. LED5_BRIGHTNESS Register
7 6 5 4 3 2 1 0
LED5_Brightness
R/W-FFh

Table 18. LED5_BRIGHTNESS Register Field Descriptions

Bit Field Type Reset Description
7–0 LED5_Brightness R/W FFh FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity

8.6.14 LED6_BRIGHTNESS (Address = 0Dh) [reset = FFh]

LED6_BRIGHTNESS is shown in Figure 34 and described in Table 19.
Return to Table 4.

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Figure 34. LED6_BRIGHTNESS Register

7 6 5 4 3 2 1 0
LED6_Brightness
R/W-FFh

Table 19. LED6_BRIGHTNESS Register Field Descriptions

Bit Field Type Reset Description
7–0 LED6_Brightness R/W FFh FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity

8.6.15 LED7_BRIGHTNESS (Address = 0Eh) [reset = FFh]

LED7_BRIGHTNESS is shown in Figure 35 and described in Table 20.
Return to Table 4.
Figure 35. LED7_BRIGHTNESS Register
7 6 5 4 3 2 1 0
LED7_Brightness
R/W-FFh

Table 20. LED7_BRIGHTNESS Register Field Descriptions

Bit Field Type Reset Description
7–0 LED7_Brightness R/W FFh FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity

8.6.16 OUT0_COLOR (Address = 0Fh) [reset = 00h]

OUT0_COLOR is shown in Figure 36 and described in Table 21.
Return to Table 4.
Figure 36. OUT0_COLOR Register
7 6 5 4 3 2 1 0
OUT0_Color
R/W-00h

Table 21. OUT0_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT0_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.17 OUT1_COLOR (Address = 10h) [reset = 00h]

OUT1_COLOR is shown in Figure 37 and described in Table 22.
Return to Table 4.

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Figure 37. OUT1_COLOR Register

7 6 5 4 3 2 1 0
OUT1_Color
R/W-00h

Table 22. OUT1_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT1_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.18 OUT2_COLOR (Address = 11h) [reset = 00h]

OUT2_COLOR is shown in Figure 38 and described in Table 23.
Return to Table 4.
Figure 38. OUT2_COLOR Register
7 6 5 4 3 2 1 0
OUT2_Color
R/W-00h

Table 23. OUT2_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT2_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.19 OUT3_COLOR (Address = 12h) [reset = 00h]

OUT3_COLOR is shown in Figure 39 and described in Table 24.
Return to Table 4.
Figure 39. OUT3_COLOR Register
7 6 5 4 3 2 1 0
OUT3_Color
R/W-00h

Table 24. OUT3_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT3_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.20 OUT4_COLOR (Address = 13h) [reset = 00h]

OUT4_COLOR is shown in Figure 40 and described in Table 25.
Return to Table 4.

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Figure 40. OUT4_COLOR Register

7 6 5 4 3 2 1 0
OUT4_Color
R/W-00h

Table 25. OUT4_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT4_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.21 OUT5_COLOR (Address = 14h) [reset = 00h]

OUT5_COLOR is shown in Figure 41 and described in Table 26.
Return to Table 4.
Figure 41. OUT5_COLOR Register
7 6 5 4 3 2 1 0
OUT5_Color
R/W-00h

Table 26. OUT5_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT5_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.22 OUT6_COLOR (Address = 15h) [reset = 00h]

OUT6_COLOR is shown in Figure 42 and described in Table 27.
Return to Table 4.
Figure 42. OUT6_COLOR Register
7 6 5 4 3 2 1 0
OUT6_Color
R/W-00h

Table 27. OUT6_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT6_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.23 OUT7_COLOR (Address = 16h) [reset = 00h]

OUT7_COLOR is shown in Figure 43 and described in Table 28.
Return to Table 4.

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Figure 43. OUT7_COLOR Register

7 6 5 4 3 2 1 0
OUT7_Color
R/W-00h

Table 28. OUT7_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT7_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.24 OUT8_COLOR (Address = 17h) [reset = 00h]

OUT8_COLOR is shown in Figure 44 and described in Table 29.
Return to Table 4.
Figure 44. OUT8_COLOR Register
7 6 5 4 3 2 1 0
OUT8_Color
R/W-00h

Table 29. OUT8_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT8_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.25 OUT9_COLOR (Address = 18h) [reset = 00h]

OUT9_COLOR is shown in Figure 45 and described in Table 30.
Return to Table 4.
Figure 45. OUT9_COLOR Register
7 6 5 4 3 2 1 0
OUT9_Color
R/W-00h

Table 30. OUT9_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT9_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.26 OUT10_COLOR (Address = 19h) [reset = 00h]

OUT10_COLOR is shown in Figure 46 and described in Table 31.
Return to Table 4.

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Figure 46. OUT10_COLOR Register

7 6 5 4 3 2 1 0
OUT10_Color
R/W-00h

Table 31. OUT10_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT10_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.27 OUT11_COLOR (Address = 1Ah) [reset = 00h]

OUT11_COLOR is shown in Figure 47 and described in Table 32.
Return to Table 4.
Figure 47. OUT11_COLOR Register
7 6 5 4 3 2 1 0
OUT11_Color
R/W-00h

Table 32. OUT11_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT11_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.28 OUT12_COLOR (Address = 1Bh) [reset = 00h]

OUT12_COLOR is shown in Figure 48 and described in Table 33.
Return to Table 4.
Figure 48. OUT12_COLOR Register
7 6 5 4 3 2 1 0
OUT12_Color
R/W-00h

Table 33. OUT12_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT12_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.29 OUT13_COLOR (Address = 1Ch) [reset = 00h]

OUT13_COLOR is shown in Figure 49 and described in Table 34.
Return to Table 4.

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Figure 49. OUT13_COLOR Register

7 6 5 4 3 2 1 0
OUT13_Color
R/W-00h

Table 34. OUT13_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT13_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.30 OUT14_COLOR (Address = 1Dh) [reset = 00h]

OUT14_COLOR is shown in Figure 50 and described in Table 35.
Return to Table 4.
Figure 50. OUT14_COLOR Register
7 6 5 4 3 2 1 0
OUT14_Color
R/W-00h

Table 35. OUT14_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT14_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.31 OUT15_COLOR (Address = 1Eh) [reset = 00h]

OUT15_COLOR is shown in Figure 51 and described in Table 36.
Return to Table 4.
Figure 51. OUT15_COLOR Register
7 6 5 4 3 2 1 0
OUT15_Color
R/W-00h

Table 36. OUT15_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT15_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.32 OUT16_COLOR (Address = 1Fh) [reset = 00h]

OUT16_COLOR is shown in Figure 52 and described in Table 37.
Return to Table 4.

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Figure 52. OUT16_COLOR Register

7 6 5 4 3 2 1 0
OUT16_Color
R/W-00h

Table 37. OUT16_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT16_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.33 OUT17_COLOR (Address = 20h) [reset = 00h]

OUT17_COLOR is shown in Figure 53 and described in Table 38.
Return to Table 4.
Figure 53. OUT17_COLOR Register
7 6 5 4 3 2 1 0
OUT17_Color
R/W-00h

Table 38. OUT17_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT17_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.34 OUT18_COLOR (Address = 21h) [reset = 00h]

OUT18_COLOR is shown in Figure 54 and described in Table 39.
Return to Table 4.
Figure 54. OUT18_COLOR Register
7 6 5 4 3 2 1 0
OUT18_Color
R/W-00h

Table 39. OUT18_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT18_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.35 OUT19_COLOR (Address = 22h) [reset = 00h]

OUT19_COLOR is shown in Figure 55 and described in Table 40.
Return to Table 4.

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Figure 55. OUT19_COLOR Register

7 6 5 4 3 2 1 0
OUT19_Color
R/W-00h

Table 40. OUT19_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT19_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.36 OUT20_COLOR (Address = 23h) [reset = 00h]

OUT20_COLOR is shown in Figure 56 and described in Table 41.
Return to Table 4.
Figure 56. OUT20_COLOR Register
7 6 5 4 3 2 1 0
OUT20_Color
R/W-00h

Table 41. OUT20_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT20_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.37 OUT21_COLOR (Address = 24h) [reset = 00h]

OUT21_COLOR is shown in Figure 57 and described in Table 42.
Return to Table 4.
Figure 57. OUT21_COLOR Register
7 6 5 4 3 2 1 0
OUT21_Color
R/W-00h

Table 42. OUT21_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT21_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.38 OUT22_COLOR (Address = 25h) [reset = 00h]

OUT22_COLOR is shown in Figure 58 and described in Table 43.
Return to Table 4.

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Figure 58. OUT22_COLOR Register

7 6 5 4 3 2 1 0
OUT22_Color
R/W-00h

Table 43. OUT22_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT22_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.39 OUT23_COLOR (Address = 26h) [reset = 00h]

OUT23_COLOR is shown in Figure 59 and described in Table 44.
Return to Table 4.
Figure 59. OUT23_COLOR Register
7 6 5 4 3 2 1 0
OUT23_Color
R/W-00h

Table 44. OUT23_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 OUT23_Color R/W 00h FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.

8.6.40 RESET (Address = 27h) [reset = 00h]

RESET is shown in Figure 60 and described in Table 45.
Return to Table 4.
Figure 60. RESET Register
7 6 5 4 3 2 1 0
Reset
W-00h

Table 45. OUT14_COLOR Register Field Descriptions

Bit Field Type Reset Description
7–0 Reset W 00h FFh = Reset all the registers to default value.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LP50xx device is an 18- or 24-channel constant-current-sink LED driver. The LP50xx device improves the
user experience in color mixing and intensity control, for both live effects and coding effort. The optimized
performance for RGB LEDs makes it a good choice for human-machine interaction applications.

9.2 Typical Application

The LP50xx design supports up to four devices in parallel with different configurations on the ADDR0 and
ADDR1 pins.

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Typical Application (continued)

VMCU VCC CVCC

VLED

VCC
RPULLUP RPULLUP OUT0

EN

OUT1
SDA

SCL
OUT2

ADDR0

MCU ADDR1 LP5024

VCAP OUT21

CVCAP
OUT22
IREF
RIREF
GND OUT23

VCC CVCC
VLED

VCC
OUT0

EN

OUT1
SDA

SCL
OUT2

ADDR0

ADDR1 LP5024

VCAP OUT21
CVCAP

OUT22
IREF

RIREF OUT23
GND

Figure 61. Driving Dual LP5024 Application Example

9.2.1 Design Requirements

Set the LED current to 15 mA using the RIREF resistor.

9.2.2 Detailed Design Procedure

LP50xx scales up the reference current (IREF) set by the external resistor (RIREF) to sink the output current (IOUT)
at each output port. The following formula can be used to calculate the external resistor (RIREF):

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Typical Application (continued)

VIREF
RIREF =KIREF ×
ISET (2)
The SCL and SDA lines must each have a pullup resistor placed somewhere on the line (the pullup resistors are
normally located on the bus master). In typical applications, values of 1.8 kΩ to 4.7 kΩ are used.
VCAP is internal LDO output pin. This pin must be connected through a 1-µF capacitor to GND. Place the
capacitor as close to the device as possible.
TI recommends having a 1-µF capacitor between VCC and GND to ensure proper operation. Place the capacitor
as close to the device as possible.

9.2.3 Application Curves

The test condition for is that the testing is under bank control, using the following register values: 0x02 (0xFF),
0x04 (0xA0), 0x05 (0xA0), 0x06 (0xA0).
The test condition for is that the testing is under bank control, using the following register values: 0x02 (0xFF),
0x04 (0x10), 0x05 (0x10), 0x06 (0x10).

Figure 62. Current Waveform of OUT0, OUT1, OUT2 and Figure 63. Current Waveform of OUT0, OUT1, OUT2 and
OUT3 OUT3

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10 Power Supply Recommendations

The device is designed to operate from a VVCC input-voltage supply range between 2.7 V and 5.5 V. This input
supply must be well-regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even in a load-transition condition (start-up or rapid intensity change). The resistance of the input
supply rail must be low enough that the input-current transient does not cause a drop below a 2.7-V level in the
LP50xx VVCC supply voltage.

11 Layout

11.1 Layout Guidelines

To prevent thermal shutdown, the junction temperature, TJ, must be less than T(TSD). If the voltage drop across
the output channels is high, the device power dissipation can be large. The LP50xx device has very good
thermal performance because of the thermal pad design; however, the PCB layout is also very important to
ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is
essential for the long-term reliability of the device.
Use the following guidelines when designing the device layout:
• Place the CVCAP, CVCCand RIREF as close to the device as possible. Also, TI recommends to put the ground
plane as Figure 64 and Figure 65.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat
flow path from the package to the ambient is through copper on the PCB. Maximum copper density is
extremely important when no heat sinks are attached to the PCB on the other side from the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• Use either plated-shut or plugged and capped vias for all the thermal vias on both sides of the board to
prevent solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.

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11.2 Layout Examples

GND GND

ADDR0
ADDR1
VCAP

IREF

SDA

VCC
SCL
EN
32

31

30

29

28

27

26

25
To LED OUT0 1 24

To LED OUT1 2 23

To LED OUT2 3 22

To LED OUT3 4 21
GND
To LED OUT4 5 20

To LED OUT5 6 19

To LED OUT6 7 18 OUT17 To LED

To LED OUT7 8 17 OUT16 To LED

10

11

12

13

14

15

16
9
To LED OUT8

To LED OUT9

To LED OUT10

To LED OUT11

To LED OUT12

To LED OUT13

To LED OUT14

To LED OUT15

GND GND

Figure 64. LP5018 Layout Example

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Layout Examples (continued)

GND GND

ADDR0
ADDR1
VCAP

IREF

SDA

VCC
SCL
EN
32

31

30

29

28

27

26

25
To LED OUT0 1 24 OUT23 To LED

To LED OUT1 2 23 OUT22 To LED

To LED OUT2 3 22 OUT21 To LED

To LED OUT3 4 21 OUT20 To LED

GND
To LED OUT4 5 20 OUT19 To LED

To LED OUT5 6 19 OUT18 To LED

To LED OUT6 7 18 OUT17 To LED

To LED OUT7 8 17 OUT16 To LED

10

11

12

13

14

15

16
9
To LED OUT8

To LED OUT9

To LED OUT10

To LED OUT11

To LED OUT12

To LED OUT13

To LED OUT14

To LED OUT15

GND GND

Figure 65. LP5024 Layout Example

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12 Device and Documentation Support

12.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.

Table 46. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
LP5018 Click here Click here Click here Click here Click here
LP5024 Click here Click here Click here Click here Click here

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LP5018RSMR ACTIVE VQFN RSM 32 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 125 LP
5018
LP5024RSMR ACTIVE VQFN RSM 32 3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR -40 to 85 LP
5024

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 31-May-2021

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jul-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP5018RSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
LP5024RSMR VQFN RSM 32 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 13-Jul-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LP5018RSMR VQFN RSM 32 3000 367.0 367.0 35.0
LP5024RSMR VQFN RSM 32 3000 367.0 367.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RSM 32 VQFN - 1 mm max height
4 x 4, 0.4 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224982/A

www.ti.com
 PACKAGE OUTLINE
RSM0032B SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4.1 B
A 0.45
3.9
0.25

0.25
0.15
PIN 1 INDEX AREA DETAIL
OPTIONAL TERMINAL
4.1 TYPICAL
3.9

(0.1)

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS
1 MAX C

SEATING PLANE
0.05
0.08 C
0.00 2.8 0.05

2X 2.8
(0.2) TYP
4X (0.45)
9 16
28X 0.4
8 SEE SIDE WALL
17 DETAIL

EXPOSED
THERMAL PAD

2X SYMM
33
2.8

24 0.25
1 32X
SEE TERMINAL 0.15
DETAIL 0.1 C A B
PIN 1 ID 32 25 0.05
SYMM
(OPTIONAL) 0.45
32X
0.25

4219108/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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 EXAMPLE BOARD LAYOUT
RSM0032B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 2.8)

SYMM
32 25

32X (0.55)

1
32X (0.2) 24

( 0.2) TYP (1.15)

VIA

SYMM 33
(3.85)

28X (0.4)

8 17

(R0.05)
TYP

9 16
(1.15)

(3.85)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

METAL SOLDER MASK

EXPOSED METAL OPENING
EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK

NON SOLDER MASK

DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

4219108/B 08/2019
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RSM0032B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(0.715)
4X ( 1.23)
32 25 (R0.05) TYP

32X (0.55)

1
32X (0.2) 24

(0.715)
SYMM 33
(3.85)

28X (0.4)

8 17

METAL
TYP 9 16
SYMM

(3.85)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 33:

77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4219108/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

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