Testability of VLSI

Lecture 1: Introduction to VLSI Testing

By Dr. Sanjay Vidhyadharan

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Why Testing is Important?

1994
Prof. Thomas Nicely reports bug in Pentium
Restoring Division
Logic error not caught until > 1M units shipped
Recall cost $450M (!!!)

1997-2000
All major micro-processor manufacturers adopt
formal verification.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Requirement of Testing

Verification Testing
➢ Verifies correctness of design. ➢ Verifies correctness of manufactured hardware.
➢ Performed by simulation, hardware ➢ Test generation: software process executed
emulation, or formal methods. once during design
➢ Performed prior to manufacturing. ➢ Test application: electrical tests applied to
➢ Responsible for quality of design. hardware on every manufactured device.
➢ No limit on number of test points/test ➢ Responsible for quality of devices.
vectors ➢ Limited on number of test points/test vectors
based on the I/O pins

➢ Manufacturing Defects : IC processing/ packaging (Nano Scale Devices ↑↑ Defects)

➢ PCB assembly and wiring errors
➢ Environment, Temperature, Humidity, Vibration
➢ Power supply fluctuations
➢ Wear and Tear : friction, corrosion

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 ASIC Design Flow
Specifications

Not Logic
Verification.
Testing is done for
faults in
fabrication.

GDS-II
Testing
Technology specific
Power, Performance
and Area (PPA) Goal 4

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification
Formal verification
➢ Used in different Pre-fabrication stages in ASIC project
➢ Two Types
1.Formal Equivalence Checking
2.Formal Property Checking

➢ Formal Equivalence Checking

1.RTL vs Pre-Routed Netlist
2.Pre-Routed Netlist vs Post Routed Netlist
3.Netlist Vs ECO-Netlist (functional engineering change order (ECO) for optimization)

Cadence (Conformal LEC) and Synopsys (Formality).

RTL to gate-level netlist conversion is done using our synthesis tool called Genus.
Synthesized netlist can be imported using Cadence Composer

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification

➢ Formal Equivalence Checking

1.RTL vs Pre-Routed Netlist

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification

➢ Formal Equivalence Checking

1.Pre-Routed Netlist vs Post Routed Netlist

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification

➢ Formal Equivalence Checking

F= AC+BC
Binary Decision Making
Assign F = (A&C)|(B & C)
A
0 1
1
B C
1
0 0
1
0

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification

➢ Two Types of Simulation

➢ Exhaustive
➢ Selective

➢ Formal Property Checking/Model Checking.

Increased Complexity of modern-day chips makes exhaustive simulation impractical
Formal Verification is done at abstract model, Need to have
System Model (Behavior Model using Verilog. VHDL or Software d sing C++)
Specifications (Property)
Verification Method

System Verilog, Cadence Jasper

Tool takes the DUT and Assertion file as inputs

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification

➢ Formal Property Checking/Model Checking.

rst_n

r0 gnt0

gnt1
r1

ClK

r0 g0

r1 g1

g1

g0 g1

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification

➢ Formal Property Checking/Model Checking.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification

➢ Formal Property Checking/Model Checking.

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification

➢ Formal Property Checking/Model Checking.

14

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Formal Verification

➢ Formal Property Checking/Model Checking.

Correctness of design checked by rigorous mathematical procedures
It does not require test benches or stimuli and turnaround time is very less
Boolean equivalence, Binary decision diagram (BDD)
System Verilog, Cadence Jasper
Tool takes the DUT and Assertion file as inputs

15

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Functional Verification

1.Static Verification

➢ Against some predefined rules

➢ Verify your design at an early stage, without any stimulus
➢ Reduce the verification effort at the RTL level.

2.Functional Simulation

➢ Verifying the functional behavior

➢ Timing delays of the internal logic or interconnects are not considered

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Timing Analysis

Static Timing Analysis

Does Static delay requirements without any input or output vectors

Dynamic Timing Analysis

Verifies functionality by applying input vectors and checking for correct output vectors

17

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 VLSI Production Flow

DFTT

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1 18

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Testing

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1

19

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Types of Testing
1. Characterization (Verification)
➢ Verify that the design is correct, and the device will meet all specifications.
➢ Functional tests are run, and comprehensive AC and DC measurements are made.
➢ Probing of internal nodes of the chip can be done on all PVT corners
➢ Silicon debug/ Basic DC/AC tests (VOL, VOH, tpd etc post fab is also called
characterization.
2. Production (Testing)
➢ Quality check on produced chips
➢ The vectors may not cover all possible functions and data patterns but must have a
high coverage of modeled faults.
➢ The main driver is cost, since every device must be tested. Test time (and
therefore cost) must be absolutely minimized.
3. Burn-in
➢ Testing, either continuously or periodically, over a long period of time.
➢ Accelerated Life test
4. Incoming Inspection
➢ Inspection on the purchased devices before integrating them into the system. Depending
upon the context, this testing can be either similar to production testing, or more
comprehensive than production testing, or even tuned to the specific systems application
20

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Types of Testing

1. Wafer sort or probe

Wafer Sort is a process where a die is tested electrically while still in wafer form.
Wafer Sort process done with the presence of equipment called wafer prober and Tester.

21

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Types of Testing

2. Parametric Tests
➢ DC parametric tests include shorts test, opens test, maximum current test, leakage test,
output drive current test, and threshold levels test.
➢ AC parametric tests include propagation delay test, setup and hold test, functional
speed test, access time test, refresh and pause time test, and rise and fall time test.

3. Functional Tests.
➢ These consist of the input vectors and the corresponding responses. They check for proper
operation of a verified design by testing the internal chip nodes.
➢ Functional tests cover a very high percentage of modeled (e.g., stuck type) faults in logic
circuits and their generation is the main topic of this course.

22

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Automatic Test Equipment

Advantest Model T6682 ATE

➢ The instrument electronics 0.35 VLSI chips.

➢ 1024 channels, so it can independently control and
observe 1024 chip pins simultaneously.
➢ Test speed is either 250 MHz, 500 MHz, or 1 GHz.
➢ Drive busses between –2.5 V to 6.0 V,
➢ Can drive small amplitude 200 mV signals.
clock/strobe timing accuracy is 870ps

23

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Automatic Test Equipment

24

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Shmoo Plot

VCCQ is the I/O supply of the emc interface

https://www.semiconductoronline.com/doc/shmooplot-0001
25

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics

Tradeoff : Quality level vs. Cost

1. Fixed Costs (FC): These are the costs of things that are necessary but do not change with
use. Example machinery. Fixed cost per product reduces with increase in product output.

2. Variable Costs (VC): These costs increase with production output. E.g., Labor, raw
material energy etc. Variable cost per product may remain constant reduces with increase in
product output.

3. Total Costs (TC): Sum of FC and VC

4. Average Cost : These are obtained by dividing the total costs by the number of units
produced.

26

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics

If aging factor is taken into

account, the average
cost might be as shown by
the rising curve (shown as
real), called a bathtub
curve.

27

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics

Production output Q (x) where x is inputs

The average product, or the product per unit of input, is called the technological
efficiency. We maximize this efficiency by setting:

28

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics

Maximizing technological efficiency.

29

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics
Economic Efficiency. Engineers are good at optimizing the technological efficiency, but
often ignore the total cost of the product. Economic efficiency is related to the total cost of
production, which includes both fixed and variable costs

Maximum economic efficiency 30

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics

The Law of Diminishing Returns: If one input of production is increased keeping

other inputs constant, then the output may increase, eventually reaching a point
beyond which increasing the input will cause progressively less increase in output.
31

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics

Increasing Returns to Scale. The case of mass production is worth considering.

Production often increases faster than the increase of inputs, which is called increasing
returns to scale. Some of the reasons are:

(1) Technological factors and

(2) Specialization.

In the long run, however, the law of diminishing returns prevails.

32

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics

Benefit-Cost Analysis
Benefits include income from sale of products or services, savings in cost and
time, etc. Costs refer to the costs of labor, machinery, energy, finances, risks, etc.
All items are normally quantified and expressed in the same units (e.g., dollars.)
We then define the benefit-cost ratio as follows:

For buying a car, the benefits could include convenient transportation to work or school and
saving time.

33

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics

Testing can be 50 to 60% of their equipment manufacturing cost

Test hardware onto the chip enable at speed testing
“Any attempt to observe a system will perturb the system behavior.”
Techniques such as scan design, BIST, and boundary scan simplify the test problem of
electronic systems.

The Rule of Ten

It is widely accepted in the electronics industry that chips must be tested before they are
assembled onto printed circuit boards (PCBs), which, in turn, must be tested before they are
assembled into systems. This is because experience has shown that the rule of ten holds. If a
chip fault is not caught by chip testing, then finding the fault costs 10 times as much at the
PCB level as at the chip level. Similarly, if a board fault is not caught by PCB testing, then
finding the fault costs 10 times as much at the system level as at the board level.

34

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics

Yield The process yield of a manufacturing process is defined as the fraction (or
percentage) of acceptable parts among all parts that are fabricated.

The term wafer yield is sometimes used to refer to the average number of good
chips produced per wafer.

35

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Economics

A good testing procedure can reject all (or most) defective parts. Testing, however, cannot
improve the process yield. There are two ways of improving the process
yield:

(1) Diagnosis and Repair. The parts that are found defective after test are diagnosed for
specific failures which are then repaired. Although the yield is improved, this procedure
increases the cost of manufacturing. The reason is that we first allow the process to make
errors which are then corrected. A more economical procedure is to eliminate the source
errors. (Fault Tolerant Design).

(2) Process Diagnosis and Correction. The defects found in the failed parts are
traced to specific causes, which may be defective material, faulty machines,
incorrect human procedures, etc. Once the cause is eliminated, the yield
improves. Process diagnosis is the preferred method of yield improvement.

36

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Data Analysis

Defects versus faults.

Process variations, such as impurities in wafer material and chemicals, dust particles on
masks or in the projection system, mask misalignment, incorrect temperature control, etc.,
can produce defects on wafers. The term defect generally refers to a physical imperfection
in the processed wafer

The term fault is used to refer to electrical, Boolean, or The term fault is used to refer to
electrical, Boolean, or functional malfunctions functional malfunctions.

In general, a physical defect in a chip can produce multiple faults. Thus, the spatial
distribution of faults on a wafer is also clustered, sometimes even more so than the defects.

37

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Test Quality

Defect level is measured as Defect per Million (DPM)

< 200 DPM is acceptable for most IC

>1,000 DPM is very bad for most IC

System DPM
Chip DPM X Number of chips in the system

E.g.
If system has 10 Chips and Chip has DPM of 1000 (0.1% IC is defective)
System DPM = 1%
If 1 Million system is manufactured 10,000 will be defective

Defect Level (DL)

 Fraction of bad IC passing the test (test escapes)

38

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Models to Predict DPM

Brown & Williams (IBM, 1981), Binomial distribution

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=2
39

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Models to Predict DL
Brown & Williams (IBM, 1981), Binomial distribution

𝑑
𝐹𝐶 = , 𝑤ℎ𝑒𝑟𝑒 𝑑 𝑖𝑠 𝑓𝑎𝑢𝑙𝑡𝑠 𝑑𝑒𝑡𝑒𝑐𝑡𝑒𝑑 𝑎𝑛𝑑 𝑡 𝑖𝑠 𝑡𝑜𝑡𝑎𝑙 𝑓𝑎𝑢𝑙𝑡𝑠
𝑡

𝑌𝑒𝑖𝑙𝑑 = 𝑃𝑟𝑜𝑏𝑎𝑏𝑖𝑙𝑖𝑡𝑦 𝑡ℎ𝑎𝑡 𝐼𝐶 𝑖𝑠 𝑔𝑜𝑜𝑑 = (1 − 𝑞)𝑡

Where each fault occurrence probability is q (uniform independent)

𝑑
𝑡 1− 𝑡
𝐹𝑟𝑎𝑐𝑡𝑖𝑜𝑛 𝑜𝑓 𝐺𝑜𝑜𝑑 𝐼𝐶 𝑝𝑎𝑠𝑠𝑖𝑛𝑔 𝑡𝑒𝑠𝑡 = (1 − 𝑞)𝑡−𝑑 = (1 − 𝑞) = 𝑌 (1−𝐹𝐶)

𝐹𝑟𝑎𝑐𝑡𝑖𝑜𝑛 𝑜𝑓 𝐵𝑎𝑑 𝐼𝐶 𝑝𝑎𝑠𝑠𝑖𝑛𝑔 𝑡𝑒𝑠𝑡 (𝐷𝐿) = 1 − 𝑌 (1−𝐹𝐶)

In the Williams-Brown model, dies are assumed to have equal faults to model the impact
of actual defects.

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=2
40

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Models to Predict DL
Agarwal Model, Poisson distribution

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=2
41

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Yield Estimation

https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=2
42

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI Circuits”,
Michael L. Bushnell and Vishwani D. Agrawal, Kluwer Academic Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

Lab. of Dependable Systems Graduate Institute of Electronics Engineering.
National Taiwan University
https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-
SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1

43

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

 Thankyou

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION