Testability of VLSI

Lecture 5: Fault Simulation

By Dr. Sanjay Vidhyadharan

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 Fault Simulation

Netlist

Fault Statistics
Collapsed fault list Fault Simulator
A0, A1, B0…

Automatic Test pattern generation

Text Vectors

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 Fault Simulation

Steps Involved in Automatic Test pattern generation

1. Fault Sensitization : Driving a node with a stuck at fault with

complementary signal by appropriately selecting the input vector.

2. Fault Propagation : Affect of the fault needs to be propagated to one

of the primary outputs.

3. Line Justification : Determination of the values at primary inputs so that fault

sensitization and propagation are successful.

SPJ is a lengthy process needs to be done for fault separately, but we can get 100% fault
coverage of detectable faults.

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 Fault Simulation
Random Test Pattern Generation
100

90

80

70
% Fault Coverage

60

50

40

30

20

10

0
0 20 40 60 80 100 120 140 160 180 200

Number of Random Test vectors

RTP is a very fast process, detects multiple faults in each run, but we may not get 100%
fault coverage of detectable faults.
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 Algorithms for Fault Simulation

Serial Fault Simulation

The block C( ) is the fault-free circuit and blocks C(f1) through C(fn) are copies of the same
circuit with faults f1 through fn . The same vectors are applied to all blocks and the outputs
of the faulty circuits are compared in the comparators shown as Comp. Event Driven can
save time as one circuit to other not much change
When fault fn is detected for the first time by vector 35, the simulation of block C(fn) is
suspended beyond that vector. This procedure, known as fault dropping, considerably speeds
up the fault simulation process .
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 Algorithms for Fault Simulation

Serial Fault Simulation

Fault dropping considerably speeds up the fault simulation process . Max time for Algorithm
is M(n+1), M is max total test vectors of each block, n is number of faults. While testing only n
vectors max required, Algorithm finds those n vectors. Could be less than n as multiple faults
can be detected by a same vector.
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 Inserting Faults

MZ M0
Fault Free 1 0
S-a-1 X 1
S-a-0 0 0

𝒁′ = 𝒁&𝑴𝒁 |𝑴𝟎

Each faut site to be modeled as above and in test bench values of MZ and M0 are be set
for different runs

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 Serial Fault Simulation

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 Serial Fault Simulation

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 Serial Fault Simulation

Advantages:
Easy to implement
Ability to handle a wide range of fault models (stuck-at, delay, Br, …)
Very fast combinational simulation

Disadvantages:
Many simulation runs required
CPU time prohibitive for VLSI circuits

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 Parallel Fault Simulation
The idea of parallel fault simulation is to use the bit-parallelism of logical operations in a digital
computer. For a 32-bit machine word, an integer consists of a 32-bit binary vector. A logical
AND or OR operation involving two words performs simultaneous AND or OR operations on all
respective pairs of bits.

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 Parallel Fault Simulation
N W2 s-a-0 W4 s-a-1 W1 s-a-0

1 1 1 1
1 W5 1 0 1 0
s-a-0 s-a-0
1
W1 1 0 1 0
1 1 1 0 1 0 1 0 W6
O2
s-a-1
W4 0 0 1 0
1 1 1 0 0 0 1 1

Max Number of Simulations Required

= Mn/(w-1) w is CPU word size,
We can assume the parallel process is faster than serial by approx. w times.

https://www.youtube.com/watch?v=eLUhlph4VCQ
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 Parallel Fault Simulation

Advantages:
A large number of faults are detected by each pattern when simulating the
beginning of test sequence.

„ isadvantages:
D
Only applicable to the unit or zero delay models
Faults cannot be dropped unless all (w-1) faults are detected

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 Deductive Fault Simulation

All signal values in each faulty circuit are deduced from the fault-free
circuit values and the circuit structure. Since the circuit structure is the same
for all faulty circuits, all deductions are carried out simultaneously. Thus, a
deductive fault simulator processes all faults in a single pass of true-value
simulation augmented with the deductive procedures. This gives the deductive
simulators a tremendous speed, but only when the modeling conditions can be
satisfied.

https://www.youtube.com/watch?v=zTLI2i69tKQ
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 Deductive Fault Simulation

Lc=[a1, c1] Ld=[a1, c1, d1]

La=[a1]
a d 0/1
0

1 c 0/1
e 0/1
b
Lb=[b0] Le=[a1, c1, e1]

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1

https://www.youtube.com/watch?v=zTLI2i69tKQ
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 Deductive Fault Simulation

Lc=[b1, c1] Ld=[b1, c1, d1]

La=[a0]
a d 0/1
1

0 c 0/1
e 0/1
b
Lb=[b1] Le=[b1, c1, e1]

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 0 0 (𝐿𝑏 ∩ 𝐿𝑎) ∪ 𝑐1

https://www.youtube.com/watch?v=zTLI2i69tKQ
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 Deductive Fault Simulation
Lc=[La.Lb,c1] Ld=[La.Lb, c1, d1]
La=[a1]
a d 0/1
0

0 c 0/1
e 0/1
b
Lb=[b1] Le=[La.Lb ,c1, e1]

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 0 0 (𝐿𝑏 ∩ 𝐿𝑎) ∪ 𝑐1
AND 0 0 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1

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 Deductive Fault Simulation
Lc=[a0, b0,c0] Ld=[a0, b0, c0, d0]
La=[a0]
a d 1/0
1

1 c 1/0
e 1/0
b
Lb=[b0] Le=[a0, bo, co, d0]

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 0 0 (𝐿𝑏 ∩ 𝐿𝑎) ∪ 𝑐1
AND 0 0 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 1 1 (𝐿𝑎 ∪ 𝐿𝑏) ∪ 𝑐0

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 Deductive Fault Simulation
Lc=[a0, b0,c0] Ld=[a0, b0, c0, d0]
La=[a0]
a d 1/0
1

1 c 1/0
e 1/0
b
Lb=[b0] Le=[a0, bo, co, d0]

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 a1, c1
AND 1 0 0 b1, c1
AND 0 0 0 c1
AND 1 1 1 a0, b0, c0

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 Deductive Fault Simulation
La=[a1]
a
0 Lc=[a1, b1,c1]

0 c 0/1
b
Lb=[a1]

La=[a1] La=[a1, c0]

0 a c 1/0
1 c 0/1
La=[a0] La=[a0, c1]

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 Deductive Fault Simulation

Lb=[a1, b0]
La=[a1] Lc=[b0, c1]
0
b 1/0
c 0/1
La=[a1]
0

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 0 0 (𝐿𝑏 ∩ 𝐿𝑎) ∪ 𝑐1
AND 0 0 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 1 1 (𝐿𝑎 ∪ 𝐿𝑏) ∪ 𝑐0

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 Deductive Fault Simulation

Lb=[a0, b1]
La=[a0] Lc=[ao,b1, c1]
1
b 0/1
c 0/1
La=[a0]
1

Inputs Output
Gate Type a b c O/P Fault List
AND 0 1 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 0 0 (𝐿𝑏 ∩ 𝐿𝑎) ∪ 𝑐1
AND 0 0 0 (𝐿𝑎 ∩ 𝐿𝑏) ∪ 𝑐1
AND 1 1 1 (𝐿𝑎 ∪ 𝐿𝑏) ∪ 𝑐0

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 Deductive Fault Simulation

Single Vector Simulation will give what are the faults which can
be detected and what should be the correct expected result.
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 Deductive Fault Simulation

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 Deductive Fault Simulation

Advantages:
Very efficient
Simulate all faults in one pass

Disadvantages:
Not easy to handle unknowns
Only for zero-delay timing model Potential
memory management problem

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 Concurrent Fault Simulation
It can handle various types of circuit models, faults, signal states, and timing models. It
basically extends the event-driven simulation method to the simulation of faults in the
most efficient way and faster. Data from previous simulation is retained.

✓ ✓ ✓ ✓

Also gives information of Faults not detected.

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 Concurrent Fault Simulation

Simulate only differential parts of whole circuit

Event-driven simulation with fault-free and faulty circuits simulated altogether
Concurrent fault list for each gate
Consist of a set of bad gates
Fault index & associated gate I/O values
Initially only contains local faults
Fault propagate from previous stage

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 Concurrent Fault Simulation

Good event
Events that happen in good circuit
Affect both good gates and bad gates
Bad event
Events that occur in the faulty circuit of corresponding fault
Affect only bad gates
Diverge
Addition of new bad gates
Converge
Removal of bad gates whose I/O signals are the same as corresponding good gates

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 Concurrent Fault Simulation

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 Concurrent Fault Simulation

Not Computed
data from previous
simulation retained

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 Concurrent Fault Simulation

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 Concurrent Fault Simulation

Advantages
Efficient
Faults can be simulated in any modeling style or detail supported in true-
value simulation (offers most flexibility.)
Faster than other methods

Disadvantages
Potential memory problem
Size of the concurrent fault list changes at run time

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 Comparison of Fault Simulation Techniques

Speed
Serial fault simulation: slowest
Parallel fault simulation: O(n3), n: num of gates
Deductive fault simulation: O(n2)
Concurrent fault is faster than deductive fault simulation
Memory usage
Serial fault simulation, parallel fault simulation: no problem
Deductive fault simulation: dynamic allocate memory and hard to predict size
Concurrent fault simulation: more severe than deductive fault simulation

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 Roth's TEST-DETECT Algorithm
The circuit is simulated for a vector in the true-value mode. This determines the states of all
lines. Next, faults are analyzed one at a time to determine which faults are detected by the
presently simulated vector. The analysis is based on Roth’s D-calculus that allows a composite
representation of a signal in the fault-free and faulty circuits.

In Roth’s D-calculus D = (1,0) and D’=(0,1). D algebra will be covered in subsequent classes.

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 References

1. “Essentials of Electronic Testing, for Digital, Memory and Mixed-Signal VLSI

Circuits”, Michael L. Bushnell and Vishwani D. Agrawal, – Kluwer Academic
Publishers (2000).

2. Video lectures by Professor James Chien-Mo Li

Lab. of Dependable Systems Graduate Institute of Electronics Engineering
National Taiwan University
https://www.youtube.com/watch?v=yfcoKOUV5DM&list=PLvd8d-
SyI7hjk_Ci0zpTqImAtpEjdK5JF&index=1

3. NPTEL Lectures
https://www.youtube.com/watch?v=M8VEEaYwlQ&list=PLbMVogVj5nJTClnafWQ9F
K2nt3cGG8kCF&index=31

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 Thankyou

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