The National Higher School of Artificial Intelligence 2023/2024
Digital systems First Year
Solution
Assignment 03
Exercise 01
A 4-bit binary number is represented as A3A2A1A0, where A0 is the LSB. Design a logic circuit that will
produce a HIGH output whenever the binary number is greater than 0010 and less than 1000.
Solution :
A3 A2 A1 A0 F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0
F= A3A2A1A0 + A3A2A1A0 + A3A2A1A0 + A3A2A1A0 + A3A2A1A0
P = Ʃm(3,4,5,6,7)
00 01 11 10
00 1
01 1 1 1 1
11
10
F= A3A2+ A3A1A0 = A3 (A2+ A1A0)
The National Higher School of Artificial Intelligence 2023/2024
Digital systems First Year
Solution
Exercise 02
Let the circuit shown below:
a. Determine the input conditions needed to produce x = 1.
b. Write the Boolean expression of x and simplify it.
Solution :
a. A = 0, B = C = 1
b. X = (A + B) (B + C)’ C
= (A’B + AB’) (BC + B’C’) C
= (A’B + AB’) BC
= A’BC
Exercise 03
a. Design a combinatorial circuit that detects the parity of a 4-bits sequence coded on the inputs A,
B, C and D. The output P = F(A,B,C,D) is equal to 0 if the number of 1’s is even (Ex : 011) and 1
otherwise (Ex:010).
b. Implement this circuit by using (16 x 1) Mux
Solution:
A B C D P
0 0 0 0 0 00 01 11 10
0 0 0 1 1 00 1 1
0 0 1 0 1 01 1 1
0 0 1 1 0
11 1 1
0 1 0 0 1
0 1 0 1 0 10 1 1
0 1 1 0 0
0 1 1 1 1 P = Ʃm(1,2,4,7,8,11,13,14)
1 0 0 0 1
1 0 0 1 0 P=A+ B + C + D
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
The National Higher School of Artificial Intelligence 2023/2024
Digital systems First Year
Solution
Exercise 04
a. Design the logic circuit that compute the two's complement of a 3 bit binary number.
b. Express the logic diagram of this circuit by using half adders circuits.
c. Express the logic diagram of this circuit by using 8x1 Muxes.
d. Express the logic diagram of this circuit by using 1x8 Demuxes.
Solution :
A B C X Y Z
0 0 0 0 0 0
0 0 1 1 1 1
0 1 0 1 1 0
0 1 1 1 0 1
1 0 0 1 0 0
1 0 1 0 1 1
1 1 0 0 1 0
1 1 1 0 0 1
X = A’B’C + A’BC’ + A’BC + AB’C’ 00 01 11 10
X = A’C + A’B + AB’C’ = A’(B+C) + AB’C’ 0 1 1 1
= A’(B+C) + A(B+C)’ = A + (B + C) 1 1
Y = A’B’C + A’BC’ + AB’C + ABC’ 00 01 11 10
0 1 1
Y = B’C + BC’= B + C
1 1 1
Z = A’B’C + A’BC’ + A’BC + AB’C’ 00 01 11 10
Z=C 0 1 1
1 1 1
The National Higher School of Artificial Intelligence 2023/2024
Digital systems First Year
Solution
The National Higher School of Artificial Intelligence 2023/2024
Digital systems First Year
Solution
Exercise 05
Consider the Boolean function : x = ab’ + b’c + a’bc’ . Implement this function by using :
a. A 3x8 decoder plus whatever logic gates.
b. An 8-input multiplexer.
c. A multiplexer (2:1) and logic gates including xor gate. (Hint : use input a as the mux control
input)
d. A multiplexers (4:1) and logic gates. (Hint : use input b and c as the mux control inputs)
Solution :
a. By using a 3x8 decoder :
x = ab’ + b’c + a’bc’ = ab’ (c + c’) + (a + a’) b’c + a’bc’ = ab’c + ab’c’ + ab’c + a’b’c + a’bc’
x = ab’c + ab’c’ + a’b’c + a’bc’
101 100 001 010
x = Ʃm(1,2,4,5)
b. By using An 8-input multiplexer
The National Higher School of Artificial Intelligence 2023/2024
Digital systems First Year
Solution
c. By using An Multiplexer (2:1) and logic gates including xor gate.
Methode 01 : Boolean algebra
x = ab’ + b’c + a’bc’ = ab’ + (a + a’) b’c + a’bc’
= ab’+ ab’c + a’b’c + a’bc’
= a (b’ + b’c) + a’ (b’c + bc’)
= ab’ + a’ (b + c)
Methode 02 : (Hint)
x = ab’ + b’c + a’bc’ = x = Ʃm(1,2,4,5)
Mux(2:1) have two data inputs (I0 and I1) with one select input (in this case : a).
In order to implement the circuit of x, we need to find the relationship between b, c and I0, I1. In other
words, we need to express the multiplexer data inputs (I0 and I1) by combining the b and c variables.
00 (b’c’) 01 (b’c) 10 (bc’) 11 (bc) I0 = b’c + bc’ = b xor c
0 (a’) I0 0 1 2 3
1 (a) I1 4 5 6 7 I1 = b’c’ + b’c = b’
Note : the order of a (msb), b and c (lsb) variables is very important in the table above.
For example, if c is the select input of mux, then I0 = c’ and I1 = c. In this case, we need to express I0 and
I1 by combining the a and b variables.
00 (a’b’) 01 (a’b) 10 (ab’) 11 (ab) I0 = a’b + ab’ = a xor b
0 (c’) I0 0 2 4 6
1 (c) I1 1 3 5 7 I1 = a’b’ + a’b = a’
abc = 101
d. A multiplexers (4:1) and logic gates. (Hint : use input b and c as the mux control inputs)
0 (a’) 1 (a) I0 = a
00 (b’c’) I0 0 4
I1 = a’ + a = 1
01 (b’c) I1 1 5
10 (bc’) I2 2 6 I2 = a’
11 (bc) I3 3 7 I1 = 0
The National Higher School of Artificial Intelligence 2023/2024
Digital systems First Year
Solution
Exercise 06
What is the function of this circuit :
A’ B’ A xnor B A xor B
0 0
1 y
1
2
AB A xnor B
1
3
C
A B
y = C’(A xor B) + C (A xnor B) = C’(A + B) + C (A + B)’
y=A+ B+ C
The function of this circuit is : Sum of Full adder
Exercise 07
a. Design the combinational circuit that converts a 3-bit binary number to its gray code.
b. Implement this circuit by using Decoder 3x8 and Or gates.
c. Implement this circuit by using two Decoders 2x4 and Or and Not gates.
Solution :
a. Design the circuit :
B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
G2 = B2 B1‘ B0‘ + B2 B1‘ B0 + B2 B1 B0‘ + B2 B1 B0 00 01 11 10
G2 = B2 0
1 1 1 1 1
The National Higher School of Artificial Intelligence 2023/2024
Digital systems First Year
Solution
G1 = B2‘ B1 B0‘ + B2‘ B1 B0 + B2 B1’ B0‘ + B2 B1’ B0
00 01 11 10
G1 = B2‘ B1 + B2 B1’ 0 1 1
1 1 1
G1 = B2 xor B1
00 01 11 10
G0 = B2‘ B1‘ B0 + B2‘ B1 B0‘ + B2 B1’ B0 + B2 B1 B0’
0 1 1
G0 = B1‘ B0 + B1 B0’ 1 1 1
G0 = B1 xor B0
Logic diagram :
b. By using Decoder 3x8 and Or gates.
You can implement this circuit by using only one decoder (3x8) (the best circuit):
The National Higher School of Artificial Intelligence 2023/2024
Digital systems First Year
Solution
c. By using two Decoders 2x4 and Or and not gates.
In the above implementation, only one decoder 2x4 is activated at a time via an activation signal
(Enabled) called E.
If E = 1, the decoder is enabled
Else (E=0), the decoder is disabled (all its outputs are at 0)
In this implementation, we only use decoders (one decoder (1x2) and two decoders (2x4)) and OR
gates.
