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BRAM and Distributed RAM

Block RAM in Xilinx FPGAs consists of two columns of memory that can be configured as different widths and depths. It functions as dual-port memory with separate read and write ports. Multiple blocks can be cascaded. Distributed RAM utilizes LUTs for smaller single-port or dual-port memory. There are three methods to incorporate memory in designs: HDL instantiation using templates, the Core Generator, or behavioral HDL inference templates for single-port, dual-port, or ROM with synchronous or asynchronous read ports.

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114 views11 pages

BRAM and Distributed RAM

Block RAM in Xilinx FPGAs consists of two columns of memory that can be configured as different widths and depths. It functions as dual-port memory with separate read and write ports. Multiple blocks can be cascaded. Distributed RAM utilizes LUTs for smaller single-port or dual-port memory. There are three methods to incorporate memory in designs: HDL instantiation using templates, the Core Generator, or behavioral HDL inference templates for single-port, dual-port, or ROM with synchronous or asynchronous read ports.

Uploaded by

Umer Mushtaq
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Block Ram and Distributed

Ram in Xilinx FPGA


Block RAM:
• Xilinx FPGA Consist of 2 columns of memory
called Block RAM or BRAM.
• It is a Dual port memory with separate
Read/Write port.
• It can be configured as different data width
16Kx1, 8Kx8, 4Kx4 and so on.
• BRAM can be excellent for FIFO
implementation.
• Multiple blocks can be cascaded to create still
larger memory.
• The block RAM functions as dual or single-port
memory.
• The maximum data path width of the block
RAM is 18 bits.
Distributed RAM:
• CLB LUT configurable as Distributed RAM
• A LUT equals 16×1 RAM
• Implements Single and Dual Ports
• Cascade LUTs to increase RAM size
• Synchronous write
• Synchronous/Asynchronous read
SPARTAN3 Resources
METHOD TO INCORPORATE MEMORY MODULES
• Three methods to incorporate an embedded memory module into a design
• HDL instantiation
• The instantiation code for many Xilinx components can be obtained directly from ISE by
selecting Edit + Language Templates.
• The Core Generator program
• The behavioral HDL inference template
HDL Templates for Memory Inference
• Single-port RAM
• Single-port RAM with asynchronous
read
• Asynchronous read can be realized
only by the distributed RAM
• this configuration recommended only
for applications that require small
storage
HDL Templates for Memory Inference Cont..
• Single-port RAM
• Single-port RAM with synchronous
read
• Synchronous read can be realized
by the Block RAM
• 4K-by-8 single-port block RAM is
inferred, and two block RAMS are
used to realize the circuit
HDL Templates for Memory Inference Cont..
• Dual-port RAM
• Dual-port RAM with asynchronous
read
• Asynchronous read can be realized only
by the distributed RAM
• this configuration recommended only
for applications that require small
storage
HDL Templates for Memory Inference Cont..
• Dual-port RAM
• Dual-port RAM with synchronous read
• Synchronous read can be realized by
the Block RAM.
HDL Templates for Memory Inference Cont..
• ROM with Asynchronous Read
• Asynchronous read can be realized
only by the distributed RAM
HDL Templates for
Memory Inference Cont..
• ROM with Synchronous Read
• Synchronous read can be realized
by the Block RAM

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