Computer Science Division

Electrical Engineering and Computer Science Department

University of California, Berkeley
Berkeley, CA 94720

Computer Science 150 R. H. Katz

Fall 1992

Course Information
Components and Design Techniques for Digital Systems

Catalog Description:
Design of Boolean logic and finite state machines. Standard SSI, MSI, and LSI parts. Drawing standards,
dependency notation. Implementation with different logic families, mainly TTL and MOS sticks. Synchro-
nous system design, ALU, memory, tri-state, and open-collector busses. Functional blocks in microproces-
sors. Discussion of a typical example of a microcomputer. Simple I/O, switches, LED displays, A/D, D/A.

Course Synopsis:
The course covers the basic building blocks and design methods used in the construction of synchronous
digital systems, most notably, digital computers. A variety of different representations of digital systems
will be described, including truth table, switch/stick diagram, logic gate, timing diagram, transistor dia-
gram, state diagram, ASM (algorithmic state machine) chart, block diagram, etc. We focus on two alterna-
tive implementation technologies, TTL and MOS, with an eye towards pointing out the different design
approaches that each of these demand. Families of highly integrated programmable logic, as well as the
more conventional discrete gate logic, will be covered. Digital computer building blocks will serve as
hardware case studies throughout the course.
The course will include extensive software tutorials to introduce students to the fundamentals of computer-
based digital design tools, as well as a traditional “hands-on” hardware laboratory including a substantial
final project. Students will receive software course accounts on UCB Volga (DECServer 5400, 64 MByte
RAM, 2.4 GByte Disk, Ultrix 4.0, Terminals in Cory and Davis) and will have access to IBM PC-ATs in
123 Cory Hall and the hardware laboratory 204 B Cory.

Course Prerequisites:
Basic Knowledge of Electronics (e.g., EECS 40); Boolean Algebra; Assembly Language Programmer’s
View of a Computer (co-registration in CS 60B is OK).

Course Grading:
Lecture Portion (60%):
Homework + Software Tutorials: 20% (6 - 10 hours per week)
Midterms (2): 20% (10% each)
Final: 20%
Laboratory Portion (40%):
Hardware Labs 0-7: 15%
Hardware Final Project: 25%

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Course Texts:
Required Materials:
1. R. H. Katz, Contemporary Logic Design, Book Manuscript, 1992. Available at Copy Central on Ban-
croft as CS150 Volume I.
2. Texas Instruments, Inc., The TTL Data Book, Volume 2.
3. Computer Science 150 Laboratory Manual, Available at Copy Central on Bancroft as CS150 Volume II.

Recommended Materials:
4. Lecture Slides for CS 150, Available at Copy Central on Bancroft as CS150 Volume III.

Lecture, Laboratory, and Discussion Section Schedule:

Lecture: MWF 2:00 – 3:00 PM, 22 Warren Hall
Laboratory Lecture: F 4 – 5 PM, 145 Dwinelle

Hardware Laboratory Sections (all in 204B Cory Hall):

11 M 8 – 11 AM (Ephrem Wu)
12 M 6 – 9 PM (Mike Dahlin)
13 Tu 8 – 11 AM (Rajeev Ranjan/Dan Engels)
14 Tu 11 – 2 PM (Sven Meier)
15 Tu 2 – 5 PM (Wendy Heffner)
16 Tu 6 – 9 PM (Srini Seshan)
17 W 8 – 11 AM (Ephrem Wu/Wendy Heffner)
18 W 6 – 9 PM (Stylianos Perissakis)
19 Th 8 – 11 AM (Dan Engels)
20 Th 11 – 2 PM (Sven Meier)
21 Th 2 – 5 PM (Rajeev Ranjan)
22 Th 6 – 9 PM (Dan Engels/Stylianos Perissakis) MAKE-UP/OPEN LAB
23 M 11 – 2 PM (John McWilliams)
24 W 11 – 2 PM (Stylianos Perissakis/John McWilliams)
25 F 8 – 11 AM (Wendy Heffner/Ephrem Wu) MAKE-UP/OPEN LAB
26 F 11 – 2 PM (Rajeev Ranjan/John McWilliams) MAKE-UP/OPEN LAB

Discussion Sections:
103 F 9 – 10 AM 81 Evans (To Be Determined)
104 F 10 – 11 AM 385 Le Conte (To Be Determined)
105 F 11 – noon 5 Evans (To Be Determined)
106 F noon – 1 PM 81 Evans (To Be Determined)

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Instructors:
Professor: Randy H. Katz, 531 Evans Hall, randy@sprite, 642-8778, Office Hours: M 1–2, W 3-4
TAs: Mike Dahlin (dahlin@sprite), Srini Seshan (ss@sprite), Co-head TAs; Daniel Engels (dragon@cory),
Wendy Heffner (wendyh@cory), John McWilliams (johnmc@cory), Sven Meier (smeier@cory),
Stylianos Perissakis (sper@cory), Rajeev Ranjan (rajeev@cory), Ephrem Wu (ephrem@cory).
Readers:

Tentative Lecture Lesson Plan

Week #1
Wednesday, 8/26:
Course Introduction and Overview;
Quick Tour through Design Process, Representations, and Technologies;
Friday, 8/28:
AND, OR, NAND, NOR, XOR, XNOR;
Motivation for Logic Simplification;
Laws of Boolean Algebra and Switch Equivalents;
Lab Lecture #1: Discussion of Hardware Laboratory #0
Monday, 8/31:
Two Level Canonical Forms;
Positive vs. Negative Logic;
Readings: Katz/pp. 1–64.
Week #2
Wednesday, 9/2:
Two Level Simplification;
Boolean Cubes and Karnaugh Maps;
Friday, 9/4:
Design Examples;
5 and 6 Variable Karnaugh Maps;
Lab Lecture #2: Discussion of Hardware Laboratory #1
Monday, 9/7:
Labor Day Holiday;
Hardware Lab #0: Schematic Entry and Logic Simulation with Viewdraw-LCA
Readings: Katz/pp. 65–92.

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Week #3
Wednesday, 9/7:
Quine-McCluskey Method;
ESPRESSO Method;
Friday, 9/11:
Multi-level Logic;
NAND-NAND and NOR-NOR forms;
Lab Lecture #3: Discussion of Hardware Laboratory #2
Monday, 9/14:
And-Or-Invert Gates; Multi-level Logic Synthesis with MIS;
Tri-states and Open Collector Gates;
Hardware Lab #1: CS 150 Lab Test Equipment
Software Tutorial #1: Logic Minimization with ESPRESSO
Readings: Katz/pp. 111–136, 194–200.
Week #4
Wednesday, 9/16:
Time Response in Networks;
Combinational Hazards;
Friday, 9/18:
Combinational Logic Word Problems;
Lab Lecture #4: Discussion of Hardware Laboratory #3
Monday, 9/21:
Circuits with State; Set-up and Hold Time;Simple Cross Coupled Gates: R-S Latch;
Latches vs. Flip-flops;
Timing Specifications;
Hardware Lab #2: Digital ICs, LEDs, Propagation Delay, and Hazards
Software Tutorial #2: Multi-Level Optimization with MIS
Readings: Katz/pp. 92–101, 148–152, 137–147, 206–222, 275–285.
Week #5
Wednesday, 9/23:
More Complex Sequential Circuits: RS-FF, D-FF, JK-FF, M/S-FF;
Timing Methodologies: Cascaded Flip-flops + Set-up and Hold Times;
Friday, 9/25:
MIDTERM I: Combinational Logic Design
Lab Lecture #5: Discussion of Hardware Laboratory #4
Monday, 9/28:
PALs and PLAs;
Hardware Lab #3: Circuits with Feedback
Readings: Katz/pp. 153–154, 285–294, 163–173, 294–300.

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Week #6
Wednesday, 9/30:
Design Examples;
Multiplexers/Selectors and Decoders;
Friday, 10/2:
Storage Registers, Register Files, Shift Registers, RAM;
Realizing Circuits with Different Kinds of Flip-flops;
Lab Lecture #6: Discussion of Hardware Laboratory #5
Monday, 10/5:
Counter Design Procedure;
Implementation with Different Flip-flop Types;
Hardware Lab #4: Basic Latches and Clocking
Readings: Katz/pp. 173–205, 301-303, 312–314, 325–349.
Week #7
Wednesday, 10/5:
Alternative State Machine Representations: State Diagrams, ASM Charts,
Hardware Description Languages;
Friday, 10/9:
State Machines; Basic Design Procedure; Parity Checker Example;
Lab Lecture #7: Discussion of Hardware Lab #6
Monday, 10/12:
Moore and Mealy Machines: Implementation Examples;
Hardware Lab #5: Registers, RAMs, and Busses
Readings: Katz/pp. 355–370, 381–410.
Week #8
Wednesday, 10/14:
Mapping Word Problems into State Diagrams: String Recognizer, Complex Counter,
Friday, 10/16:
Mapping Word Problems into State Diagrams: Traffic Light Controller, Digital Combination Lock;
Lab Lecture #8: Discussion of Hardware Lab #7
Monday, 10/19:
Choice of Flip-flops; Implementation Strategies: ROM-based, PAL-based;
Hardware Lab #6: Programmable Gate Arrays (Part I)
Readings: Katz/pp. 411–430, 338–345, 471–488.

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Week #9
Wednesday, 10/21:
Implementation Strategies: Counters, EPLDs;
Friday, 10/23:
Implementation Strategies: FPGAs, Xilinx LCAs;
Lab Lecture #8: Final Project
Monday, 10/26:
Finite State Machine Optimization: State Reduction Techniques
Hardware Laboratory #7: Programmable Gate Arrays (Part II)
Readings: Katz/pp. 495–544, 447–459.
Week #10
Wednesday, 10/28:
Finite State Machine Optimization: State Assignment Techniques and Tools;
Friday, 10/30:
MIDTERM II: Finite State Machine Design and Implementation
Lab Lecture #9: Final Project
Monday, 11/2:
Structure of a Computer; Interplay of Control and Datapath;
Software Tutorial #3: State Assignment Tools
LAB Project: Checkpoint #1, Preliminary State Diagram and Datapath Design
Readings: Katz/pp. 460–485, 553–565;
Week #11
Wednesday, 11/4:
Overview of Computer Hardware Organization and Register Transfer;
Friday, 11/6:
Block Diagram/Register Transfer View; Memory Interface;
Monday, 11/9:
Bussing Strategies; Influence on Control; State Diagram and Datapath for a Simple CPU;
LAB Project: Checkpoint #2, Detailed Datapath Design
Readings: Katz/pp. 566–588.
Week #12
Wednesday, 11/11:
Derivation and Timing of Register Transfer/Microoperations;
Friday, 11/13:
Controller Implementation: Classical Moore and Mealy Machines;
Monday, 11/16:
Controller Implementation: Pure and Hybrid Jump Counters;
LAB Project: Checkpoint #3, Detailed Controller Design
Demonstration of Operational Datapath
Readings: Katz/pp. 601–621.

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Week #13
Wednesday, 11/18:
Controller Implementation: Branch Sequencers and Microprogramming;
Friday, 11/20:
Datapath Implementation: Number Systems
Monday, 11/23:
Datapath Implementation: Simple Arithmetic Circuits;
Carry Lookahead Logic and ALUs;
LAB Project: Checkpoint #4, Testing Plan, Timing Diagrams
Demonstration of Operational Controller
Readings: Katz/pp. 622–637, 223–255.
Week #14
Wednesday, 11/25:
Datapath Implementation: Multipliers;
Friday, 11/27:
Thanksgivings Day Holiday;
Monday, 11/30:
Self-starting Counters; Asynchronous vs. Synchronous Counters;
LAB Project: Integration of Datapath and Controller
Readings: Katz/pp. 256–267, 340–354.
Week #15
Wednesday, 12/2:
Timing Methodologies: Narrow Width Clocking vs. Multiphase;
Problems of Clock Skew;
Friday, 12/4:
Asynchronous Inputs and Speed-Independent Circuits;
Monday, 12/7:
Course Review;
LAB Project: Demonstration of Working System
Readings: Katz/pp. 294–300, 304–311.

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