COE 301

Tentative Lecture/Lab Breakdown

Week Lectures Lab

Part I: Assembly Language Programming
Introduction to computer organization, high-level, assembly, and
1 machine languages. Components of a computer system.
No Lab

Memory Hierarchy, Fetch-Execute Cycle. Technology Lab 1/2: Introduction to MIPS Assembly Language Programming (MARS)
Improvements. Introduction to assembly language programming,
 Information about the lab
instructions, registers, assembly language statements, directives,
2  MARS tutorial: Editor, Assembler, Debugger
text, data, and stack segments. Defining data, arrays, and strings.
 Register and Memory
Memory alignment, byte ordering, and symbol table. System calls,
console input, and output.  Introduction to system calls. Hello world program
Lab 3: Integer Arithmetic
Integer storage sizes, review of binary addition and subtraction,
carry and overflow.  Integer addition & subtraction
MIPS instruction set architecture, instruction formats, R-type  Shift and rotate
3 integer arithmetic, logic, and shift instructions, immediate  Bitwise logic instructions
operands, I-type arithmetic and logic instructions, pseudo-  Convert character to integer
instructions.  Simple loop: e.g. count the number of 1’s in a register.
 Tracing program execution and breakpoints
Lab 4: Flow Control and 1D arrays (Quiz 1)
MIPS Integer multiply and divide instructions.  Defining data, strings, and arrays
Control flow, branch and jump instructions, translating if-else  Viewing variables in memory
4 statements and logical expressions. Compare instructions and  1D-Array traversal
conditional-move instructions.  Searching an array
 Finding min and max
 Generate a sequence of random numbers and save in an array.
Arrays, allocating arrays statically in the data segment and
Lab 5: 2D Arrays and Files
dynamically on the heap, computing the memory addresses of
5 array elements.  Indexing 2D arrays
Load and store instructions.  Pointers versus indexing
 Loops and use of pointers to traverse arrays.  Reading a text file
Addressing modes, jump, and branch limits.  Application: reading an image from a file and dealing with images

Defining functions (procedures) in assembly language, function

calls, and return instructions. Passing arguments by value and by Lab 6: Procedure and Stack (Quiz 2)
reference in registers, and the return address register.
The stack segment, allocating and freeing stack frames, leaf versus  Stack pointer and frame pointer
non-leaf functions, and preserving registers across function calls.  Writing procedures
6
Allocating and referencing a local array on the stack. Bubble Sort  Application: Sorting procedure
example and its translation into assembly code. Recursive  Application: recursive function
functions, translating recursive functions into assembly language.
Lab 8: Floating-Point Part 1
Floating point representation, IEEE 754 standard, de-normalized  Coprocessor 1
7
numbers, zero, infinity, NaN.  Floating-point registers
FP comparison, FP addition, FP multiplication. Rounding and  Floating-point instructions
accurate arithmetic.  Example: matrix multiplication

Lab 8: Floating-Point Part 2 (Quiz 3)

MIPS floating-point instructions: load/store, arithmetic, data
8 movement, convert, compare, branch, FP system calls. Floating-  Special functions: exp(x), sin(x) using Taylor Series
point programs. Example on Matrix Multiplication.  Dichotomy, Integrals …
 A brief introduction to Exceptions and I/O with an example (Lab 7)
Part II: CPU Design
Lab 10: Introducing the Logisim Tool
Designing a processor, register transfer level, datapath  Review logic design
9 components, clocking methodology, single-cycle datapath,  Design Adder/Subtractor
implementing a register file, and multifunction ALU.  Design Shifter
 Completing the ALU
 Testing the ALU
 Lab 11: Building the Main Datapath Components (Quiz 4)
 Multiported Register File
Control signals and control unit, ALU control, single-cycle delay  Instruction and data memories
10 analysis, and clock cycle.  Building the datapath
 Connecting Register File to ALU
 Testing components
Lab 12: Single Cycle Datapath
CPU performance and metrics, CPI of a multi-cycle processor,
performance equation, performance comparison of a single-cycle  Complete single-cycle datapath
11 versus a multi-cycle processor.  Next PC logic
Amdahl’s law, energy, and power consumption, benchmarks, and  Control logic
performance of recent processors.  Clocking
 Testing the complete datapath
Lab 13: Pipelined CPU Design with Data Forwarding (Quiz 5)
Pipelining versus serial execution, timing diagrams, MIPS 5-stage
 Pipelined datapath
12 pipeline, pipelined datapath, pipelined control, pipeline
 Pipelined control: Hazards, …etc.
performance
 Testing components
Lab 14: Pipelined CPU Design with Stall Capability
Pipeline hazards: structural, data, and control hazards, load delay,
 Pipelined Next PC logic
13 hazard detection, stall and forwarding unit, delayed branching, and
 Clocking
branch prediction.
 Testing the pipelined datapath

Main memory organization, SRAM vs DRAM storage cells, Lab 15: Project Submission
DRAM refresh cycles, latency and bandwidth, trends in DRAMs,
memory hierarchy, cache memory, and locality of reference.  Completing project
14 Cache memory organization: direct-mapped, fully-associative, and  Submitting report + presentation
set-associative caches, handling cache miss, write policy, write  Presenting work + Demo
buffer, and replacement policy.  Questions & answers

Cache performance, memory stall cycles, and average memory Lab 15: Project Submission
15 access time. Introduction to multi-level caches, and multi-level
cache performance.  Final Quiz (Quiz 6)