SECTION A COURSE OUTCOME 1 MAXIMUM: 20MARKS

A1 Fiqure A1.1 shows the architecture of 8085, which employs group of general purpose and specific
purpose register to perform a specificoperation. Architecture represented below employs a role in
various automatedapplications. Refer the diagram to answer the questions given below.
Address Bus

1)The 8085
microprocessor
has a 16-bit 8085 Memory Input
address bus, Output Real
which means it MPU World
can address 2^16
= 64 KB(max D;
) (kilobytes) of Daa Bus
Do
memory, not 128
KB Control Bus

Figure A1.1 Architecture of 8085

() Select the wrong statement about 8085 microprocessor from the following and Justify
8085 is an 8-bit processor since its data length and data bus width is eight bits
It has 40 pins and uses +5V for power
It can address upto 128 KB of memory, since it has 16 bits of addressing capability.
(iv) 8085 microprocessor includes ALU unit, Registers, Timing and control unit
(4 Marks -[U/G,2)
() Choose the appropriate answer for the following
()
(0)
Address Bus Unidirectional (Unidirectional/Bidireçtional)
Control Bus Bidirectional (Unidirectonal/Bidirectional)
(ii) Data BuS
Bidirectional (Unidirectional/Bidiredional)
(3 Marks -(U/C,2)

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 store the address of the nex
counter is a 16-bit register used to
(i) Assertion(A): Program
instruction to be executed microprocessor
Lines are available in 8085
Reason(R): There are 16 Address
T30 TUTITeMI MAMMA IAAIMAa
Solutions: WanA ol bsintllAnoitulitanl auomornotuA nA)
AOMAMAYHTA2 explanation of A
(R) are correct andR is the correct
() Both Assertion (A)and Reason is not the correct explanation of A
Both Assertion (A)and Reason (R) are cotrec ubut R
(n) Both Assertion (A) and Reason (R)false
(iv) Assertion (A) is True but Reason (R) is false
(v) Assertion (A) is false but Reason (R) is true,oOAIIM S S0teIS
212 1g ta3 Marks -[UIG, 2])
A
rotatory solar panel system is designed using 8085 microprocessors. Itconsists of servomotor, 8255
Cand LCD. The servomotor should rotate from 0to 180 degree based on the sun \ight direction.
rotations that is 90 (first rotation) and 180 (second rotation), For this condition, the accumulator value
as to be rotated to make the servomotor to rotate. The block diagram is shown for the above system
Jith needed memory, /O ports and control signals, Answer the following based on the figure A2.1

INTA
cnenoo t0ga9 noteouO 9rit to 3 bns Anoitbod
RST 6.5 TRAP
INTR |RST 5.5TRST Z. 61 u0 ovdnPens iqrnsils nso enabul2
SID SOD

Interrupt control Serial /O

control

A MOITOBE
8-bit internal data bus

(8) (8) (8) (8)

AcCumulator temp. reg. instruction (8) (8)
-flops B reg
register C reg.
(8) (8)
D reg. E rag
Arithmatk
(8). 8)
instruction Hreg.
Logic Unit decoder register
(ALU) and i(16)
machine stack polnter aray
(8)
Gycle (16)
encoding program counter
incrementer/
decremen
(16
Grementer
Power S +5V address latch
supply GND Timing and control
CIlk
Gen Control Status DMA (8)
Reset: address buffer (8)
CIkOut 'address buffer
RD WR ALE S, S, IOM HLDA Reset out
Ready Hold Reset in A15-Ag
address bus AD, -ADo
address/data bus
Figure A1.1 Rotatory solar panel system
design with 8085
Identify the missing words in the microprocessor
following table
Name of the
registers Symbol No.of bits
Function
Accumulator A It perform arithmetic,
logical, /O &
General purpose
register B, C, D, E, H&L LOAD/STORE operation
General purpose registers
Program counter PC

Stack pointer SP
Hald tRacteltt
16 bit
It holds the address of top most item in
the stack.
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 (5 Marks -[U/C,2])
() From the figure A2.1, Flag registers having five 1-bit flip-flops are provided below.
(Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), Carry (C)
Arrange the bits position of the flag registers in the below table.
D2 D1 DO
D7 D6 D5 D4 D3

P CY
s z AC
(3 Marks - [U/C,2])
from the following which set to 1 when there is
(ii) By observing the scenario A1.1, Predict the flag odd number of one bit?
even number of one bits in result and to 0 when there is
(a) Sign (S),
(b) Zero (Z),
(c) Auxiliary Carry (AC),
Parity (P) (2 Marks -[U/C,2])
phone. If suddenly the phone bell rings, music
Consider a person is listening to music in his mobile get disconnected. Once the call gets
played. in the mobile phone will be paused until the call
called Interrupt. It has been
disconnected, the music player resume playing the song. This is questions
represented in the below diagram. Based on the scenario answer the following

INSTRUCTIONi i) * It means Interrupting

ÍNSTRUCTION2
the normal execution of
ii) TRAP Normal the
Progam
RST 7.5 Flow INS RUCTKON3 microprocessor.
RST 6.5 INST RUCTKONE4 Inte rrupt
Routine
RST 5.5
Inte rupt
INTR Occured NSTRUCEO * When microprocessor
INTA Interrupt Acknowledge
INSTRUCT IONS receives interrupt
signal, it
Normal INSTRUCTIONO
Program
discontinues whatever it
Flow INSTRUCTON z was executing.
INST RUGTON8

Figure A1.3Interrupt handling

) From the scenario A1.3, identify, what wil happen to execution of instruction if an nterrupt exist
while the processor is executing a program?
(2 Marks - [UC,2])
() Interpret the number of maskable interrupts are available in the 8085 microprocessor. (Refer
Figure A1.2)
(2 Marks - [U/C,21)
(m) From the scenario A1.3, Select the correct statement about TRAP from the following.
Non maskable, highest priority &hardware interrupt
(ü) Maskable, lowest priority &hardware interrupt
(0) Non maskable, highest priority &Software interrupt
(v) Maskable, lowest priority &Software interrupt
(2 Marks --[U/G,21)
Assume the instruction code 0110 1101(6D H) is stored in the memory location 4500H.
Rearrange the folowing sequence of events when the instruction code is fetched by the 8085
mícroprOcessor.
D -> B -> A -> C
A The instruction stored in the memory location is
placed on the data bus and Is
transferred the instruction decoder of the microprocessor
to
B The control unit sends the memory read control signal (MEMR,
output buffer of the memory chip. active low) to enable the
C. The instruction is decoded and
executed according to the binary pattern of the

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 on the
instruction
places the 16-bit address 4500H of the memory location
The program can
address bus. (4 Marks -[An/C,2])
COURSE OUTCOME 2
MAXIMUM:20 MARKS
SEC TION B
8085Microprocessor, which was designed by Intel in
B1 8086 Microprocessor is an enhanced version of given below in Figure B1.1.
1976. The Architecture of 8086 microprocessor has

MEHORY
tAFACO

ISTAUcTION
STAEAM
6YTE
OVEUE

ONTAOL
SYSTEM

AM

CH C AAITHMETIC
D LOGIC UNIT

0PsAANOS
FLAGS

Figure B1.1 Architecture of 8086 microprocessor

From Scenario B1.1, Predict the incorrect statement regarding 8086 from the following and
rewrite the correct statement. correct :prefetch queue that can
hold up to 6 bytes of instructions
() () It uses two stages of pipelining to enhance instruction execution
(i) It is available in 3 versions based on the frequency of operation efficiency
(jüy Fetch stage can prefetch up to 6 bytes of instruction
(iv) It has 512 vectored interrupts
(3
From the Figure B1.1, compare 8086 microprocessor with 8085 microprocessor Marks
-
(i) in terms [U/C,2])
of their
size, address bus, memory &pipelining.
google google panni parthen..........
(5 Marks
By observing Figure B1.1, we know that 8085 does not have an instruction queue, - [An/C,21)
whereas
(i)
8086 has an instruction queue. Illustrate how the instruction queue is helpful to increase the
execution speed.
B2
(2 Marks- [An/C,2])
In an autonomous flight control system, the microprocessor 8086 (Master) is to be communicated with
other two microprocessor (smart sensor - Slaves) to drive the flight to a desired path. Master will
control the flight wings spoil position. Slave 1 will sense the speed of the flight and slave 2 will sense
the position and orientation of flight.

iii) The instruction queue in the 8086 microprocessor allows for the prefetching and
buffering of multiple instructions. This enables overlapping of instruction fetch and
execution, reducing idle time, minimizing the impact of memory access latency, and
overall increasing execution speed by providing a continuous flow of instructions to the
CPU

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 PILOT Auto Pilot Control Surface
Command

Transducers
Feedback
FLIGHT cONTROL
COMPUTERS

Pilot/AP Input
flight control system
Figure B2.1 An autonomous application shown in figure B1.2. Justify your
Predict the suitable mode of operation for the
answer. (2 Marks -[An/C,2)
the system shown in the
ensure slave processors Connected in
ii ldentify the output pin enabled to of the bus.
figure B1.2 willnot gain the control Lock (2 Marks - [An/C,2])
autonomous flight
table containing different kind of interrupt Occurs in an
Consider the below Match the following List Iwith List ll.
controlsystem shown in figure B1.2.

List I List Il
d
A) Stack
overflow
Software interrupt
) nternal interrupt a
(B) |Timer
|nvalid uExternal interrupt b
(C lopcode
Machine check c
pSuperior call |(Vinterrupt
(4 Marks-[An/C,2)
the
bits of the starting address for each of
ii) Segment registers used to hold the upper 16segment registers.
segments. Replace the number blocks with the

CODE

1
code DATAS1
2
data
3
stack
4
extra
Segment Registers DATASZ

STAÇK

MEMORY

Figure B2.2 Segment registers in 8086

(2 Marks -[An/C,2)J

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 microprocessor has given in the figure B3. 1.
Fn ontguraton of S086
Voc (5P) iv) The maximum amount of
Vss (GND) AD15 memory that can be interfaced
AD14 39 with the 8086 microprocessor is
39 A16/S3 determined by its 20-bit address
AD13
S7 A1754 bus. The 8086 has a 20-bit
AD12
36 A18/55 address bus, which means it can
AD11
35 A19/S6 address 2^20 memory locations.
ii) AD10 Each memory location
https://www.g AD9 EHE/S7 corresponds to one byte of data.
eeksforgeeks. ADS 33 MNAK which is equivalent to 1 MB.
org/general-pu AD7 RD
rpose-register ADS 9808 RQiGTO HOLD
s-8086-microp
rocessor/ ADS RQGT1 HLDA
ADA LOCK WR
ADS MIO
AD2 DTR
AD1 DEN
ADO 6 QSO ALE
NAM 17 INTA
INTR 18 TEST
CLK 19 READY
Vss (GND) D20 i) MN/M(BAR)X is low
21 RESET
Figure B3.1 Pin configuration of 8086
From the fgure B3.1,paraphrase the condition for 8086 to work as
multiproOcessor. Why?
( Construct the register organzation of the 8086 from fgure B3.1 (2 Marks- [An/G,2)
( Outine the stensivoed when PUSH BX is executed by the (3 Marks-[An/C,2)
8086 shown in figure B3.1
Compute how much of menory in tems of bytes can be (3 Marks -[An/C,2])
interfaced with the 8086. Why?
SECTIONG COURSE QUTCOME 3
(2 Marks -[An/C,21)
MAXIMUM: 10 MARKS
Assume that deta to be stored has kept in Stack of 80S6
estack stucture microprocessor. Below Fig. C.1.1 represents
STACK
i) Stack Pointer (SP)
HSn Push Operation
Pop Operation
stack Segment (SS) and
SS:SP6 Stack Offset (BP)
Stack Frame
SS:SP4 write about this
SS:SP-2
SS:SP 1 byte 1byte
16 bits

Figure C1.1. Stack Structure

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 the stack.
llustrate the method used by 8086 microprocessor in (2 Marks -[U/C,2])_
0) Fromthe figureC1.1, the
function of PUSH and POP instruction after
C1.1, contrast the
() Wth the help of fiqure the stack pointer (SP). (3 Marks-[An/C,2)
execution of instruction by
in 8086
Refer B3.2
operands in the ADD and SUB instructions
two memory
It is pOssible to use
microprocessor. Analyze your answer. (3 Marks - [An/C,2])
during the execution of INC and DEC instruction in
affected
Interpret whether the cary flag will
the 8086. (2 Marks - [U/C,2])
Refer C1.1
contains 3000H& stack pointer contains 8434 H. Compute
Consider the stack segment register
the following
) Physical address of the top of the stack in 8086 microprocessor. be inserted
stack pointer contains the value 0000H, Identify number of elements can
()If the
into stack. (3 Marks - [An/C,2)
Assume the following assembly code:
MOV AX 1234 H
PUSH AX
initialy stack pointer (SP) = FC78H
Using the above code predict the following after the PUSH operation is done.
Value of AX =
Stack pointer (address) =
(2 Marks-[An/C,2)
***End of Question Paper***