‘St Parameters No. 1 Instruction cycle 2 Instruction execution 3 Memories 4 Onchip/or chip memories 5 Program flow control 6 Pipelining 7 Operand Fetch 8 Address and data bus multiplexing, 9 Computational units, 10 Onchip address and data bus 21 Addressing, modes 12 Application DSP processor Instructions are executed in single cycle of the clock Parallel execution is possible. Separate data and program memory. Program and Data memories are present on chip extendable off chip. Program sequencer and instruction register take care of program flow Pipelining is implicate through instruction register and instruction cache. Multiple operands can be fetched simultaneously. Address and data bus are not multiplexed. They are separate ‘on chip as well as off chip. Three separate computational units: ALU, MAC and shifter. Separate address and data bus for program and data memory. Direct and indirect addressing, modes. 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