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My Lecture 5

This document provides an overview of the hardware specifications of the 8088/8086 microprocessors. It discusses the various pins and signals of the chips, including clock, reset, ready, test, interrupt requests and acknowledges. It describes the bus cycles for opcode fetch, memory read and write, and I/O read and write. It also covers the maximum mode pins for DMA requests and grants, lock signal, status pins connected to the 8288 bus controller, and instruction queue status pins. The document is intended for a course on microprocessor programming and interfacing using an 8088/8086.

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Kashif Khan
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30 views11 pages

My Lecture 5

This document provides an overview of the hardware specifications of the 8088/8086 microprocessors. It discusses the various pins and signals of the chips, including clock, reset, ready, test, interrupt requests and acknowledges. It describes the bus cycles for opcode fetch, memory read and write, and I/O read and write. It also covers the maximum mode pins for DMA requests and grants, lock signal, status pins connected to the 8288 bus controller, and instruction queue status pins. The document is intended for a course on microprocessor programming and interfacing using an 8088/8086.

Uploaded by

Kashif Khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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HARDWARE SPECIFICATION OF

8088/8086

COURSE CODE: CS-430


COURSE TITLE: MICROPROCESSOR PROGRAMMING AND INTERFACING
PREPARED BY: DR. SYED AQEEL HAIDER

NED
REVIEW OF PREVIOUS LECTURE

• CLK (8088/8086) • M/IO (8086) • SSO (8088)


• RESET (8088/8086) • MN/MX (8088/8086) • BHE (8086)
• READY (8088/8086) • INTR (8088/8086) • S6 – S3 (8088) / S7 – S3
• TEST (8088/8086) • INTA (8088/8086) (8086)

• RD (8088/8086) • NMI (8088/8086)


• WR (8088/8086) • HOLD (8088/8086)
• IO/M (8088) • HLDA (8088/8086)
OPCODE FETCH/ MEMORY READ BUS CYCLES

NED
MEMORY WRITE BUS CYCLES

NED
I/O READ BUS CYCLES
I/O WRITE BUS CYCLES

NED
8088/8086 MAXIMUM MODE PINS

• RQ/GT0 & RQ/GT1 – DMA Request/Grant Signals, Bidirectional Signals for both DMA Request
and Grant/Acknowledge
• LOCK – It is an output pin, used to lock peripherals off the system, it is activated by placing LOCK:
prefix on any instruction.
e.g. LOCK: MOV [0250h], AX; when this instruction is executed then LOCK signal will be at logic 0
to lock other peripheral and coprocessors from using buses.

NED
8088/8086 MAXIMUM MODE PINS
• S2, S1 and S0 – Shows status of 8088/8086 in maximum mode, connected to 8288 Bus Controller
for regeneration of the essential signals

NED
8288 BUS CONTROLLER
IC + FUNCTIONAL DIAGRAM

NED
8088/8086 MAXIMUM MODE PINS
• QS1 and QS0 – Instruction Queue Status Signals

• 8088 is having Instruction Queue of 4 bytes while 8086 is having Instruction Queue of 6 bytes.
• Machine Language Instructions are prefetched and stored in this queue to reduce program
execution time.

NED
THANK YOU
NED

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