Chapter 5: Sequential Circuits

Le Ly Minh Duy, Ph.D

Email: [email protected]
https://sites.google.com/view/ly-minh-duyle

Department of Computer and Communication Engineering

Faculty of Electrical and Electronics Engineering, HCMUTE

Original slides composed by Dr. Truong Ngoc Son – Modified by Dr. Le Ly Minh Duy
Department of Computer and Communication Engineering
RS Latch

2 Sequential Circuits
 RS Latch
• Verilog HDL
module RS_LATCH(
input wire R, S, CLK,
output reg Q, Qb
);
always @(R, S, CLK) begin
if/*((CLK==1)&&(S==0)&&(R==1))*/({CLK,S,R}
==3'b101) begin Q=0; Qb=1; end
else if ((CLK==1)&&(S==1)&&(R==0)) begin
Q=1; Qb=0; end
end
endmodule
3 Sequential Circuits
D Latch

4 Sequential Circuits
 D Latch
• Verilog HDL

LATCH

5 Sequential Circuits
D Flip-Flop

6 Sequential Circuits
 D Flip-Flop
• The difference between a latch and a flip-flop is
– A latch is asynchronous, and the outputs can change as
soon as the inputs do (or at least after a small
propagation delay)
– A flip-flop is edge-triggered and only changes state
when a control signal goes from high to low or low to
high

FLIP-FLOP

7 Sequential Circuits
8 Verilog HDL Basics
Comparison of D storage elements.

9 Sequential Circuits
T Flip-Flop

10 Sequential Circuits
 T Flip-Flop

module T_FF(
input wire t, clk,
output reg q, qb );
initial
begin
q=1 ;
qb=0;
end

always @( posedge clk)

if (t) begin
q = ~q ;
qb = !qb;
end
endmodule

11 Sequential Circuits
 JK Flip Flop
Input Output
Pre CLR CLK J K Q QD
0 0 x x x 1 1
0 1 x x x 1 0
1 0 x x x 0 1
1 1 0 x x Qo QDo
1 1 0 0 Qo QDo
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 NOT Q NOT QD

12 Sequential Circuits
 JK Flip Flop
• Verilog HDL

13 Sequential Circuits
Shift Register (Serial-In Serial Out)

14 Combinational circuit
 Shift Register
• Instance shift register using D-FF.
module DFF(
input wire d,clk,
output reg q );
always @(posedge clk)
q=d;
endmodule
// Serial input - serial output using DFF
module SISO(
input wire in, clk,
output wire out) ;
// signal declaration
wire q1,q2,q3 ;
//module instance
DFF ff1 (in,clk,q1);
DFF ff2 (q1,clk,q2);
DFF ff3 (q2,clk,q3);
DFF ff4 (q3,clk,out);
endmodule
15 Sequential Circuits
 Module instance review
• Modules can be instantiated from within other modules.
When a module is instantiated, connections to the ports
of the module must be specified.
• There are two ways to make port connections.
– Connection by name, in which variables connected to each of
module inputs or outputs are specified in a set of parenthesis
following the name of the ports. In this method order of
connections is not significant.
– Ordered connection. In this method the order of the ports must
match the order appearing in the instantiated module.

16 Sequential Circuits
 Module instance review
• Connection by name
module dff (
input wire clk, d,
output reg q );
always @(posedge clk) q = d;
endmodule

module top (
input wire d_in, clk,
output wire q_out);

wire n1;
dff Inst_1 (.d(d_in), .q(n1), .clk(clk));
dff Inst_2 (.clk(clk), .d(n1), .q(q_out));
endmodule

17 Sequential Circuits
 Module instance review
• Connection by order
module dff (
input wire clk, d,
output reg q );
always @(posedge clk) q = d;
endmodule

module top (
input wire d_in, clk,
output wire q_out);
wire n1;

dff Inst_1 (clk, d_in, n1);

dff Inst_2 (clk, n1, q_out);
endmodule

18 Sequential Circuits
Thanasis Oikonomou 19 Sequential Circuits
 Shift Register – Serial input, parallel
outputs
• Instance the shift register using D-FF

20 Sequential Circuits
 Shift Register – Serial input parallel
outputs
module DFF(
input wire d,clk,
output reg q );
always @(posedge clk)
q=d;
endmodule
// Serial input - parallel output using DFF
module SIPO(
input wire in, clk,
output wire [3:0] q) ;
// signal declaration

//module instance
DFF ff1 (in,clk,q[0]);
DFF ff2 (q[0],clk,q[1]);
DFF ff3 (q[1],clk,q[2]);
DFF ff4 (q[2],clk,q[3]);
endmodule

21 Sequential Circuits
Counter

22 Sequential Circuits
Asynchronous Counter (not same clock)

23 Combinational circuit
 Counter
• Instance counter with T-FF

24 Sequential Circuits
 Synchronous counter (same clock source)

Thanasis Oikonomou 25 Sequential Circuits

 UP Counter4b (behavioral)
module
…
clk
rst OUT
UP_CNT4b always @ (posedge clk)
SS begin
if (rst==1’b1)
out = 4’b0;
else
SS=0: stop, SS=1: count if (SS==1’b1)
out = out + 1’b1;
else
out = out;
end

endmodule
26
 UP/DOWN Counter4b (behavioral)

clk
rst OUT
CNT4b module
SS …
UD

always @ (posedge clk)

SS=0: stop, SS=1: count if (rst==1’b1)
UD=0: down, UD=1: up out = 4’b0;
else
….

endmodule

27
 clk module CNT4b (clk,… OUT);

rst OUT input clk, rst, SS, MODE;

input [3:0] MIN, MAX;
CNT4b output reg [3:0] OUT;
SS
MODE always @(posedge clk)
begin
if (rst)
OUT=MIN;
MIN MAX else
if (SS==1’b1)
- SS=1: enable, SS=0: stop if (MODE==1’b1 && OUT<MAX)
- MODE=1: UP/ 0: DOWN OUT = OUT + 1’b1;
- MIN<= counter <= MAX else if (MODE==1’b0 && OUT>MIN)
OUT = OUT – 1’b1;
else OUT = OUT;
else
OUT = OUT;
end

endmodule
 Homework
• Design a circuit to control 8 LEDs
– Light LEDS sequentially from (1) left to right then (2)
turn 8 LEDs off sequentially from left to right (one-by-
one).
– The frequency is adjusted by two switches
– The input clock is 50Mhz

• Left-to-right clk

• Right-to-left reset LED[7:0]

• Center-to-2side
• 2side-to-center
29 Verilog HDL Basics
 LED_SANG_DICH_TSP (input clk,
input reset, output reg [7:0] LED)
clk state LED[7] LED[6] LED[5] LED[4] LED[3] LED[2] LED[1] LED[0]

posedge 1 1 0 0 0 0 0 0 0

posedge 2 0 1 0 0 0 0 0 0

posedge 3 0 0 1 0 0 0 0 0

posedge 4 0 0 0 1 0 0 0 0

posedge 5 0 0 0 0 1 0 0 0

posedge 6 0 0 0 0 0 1 0 0

posedge 7 0 0 0 0 0 0 1 0

posedge 8 0 0 0 0 0 0 0 1

posedge 9 0 0 0 0 0 0 0 0

posedge 1 1 0 0 0 0 0 0 0

(a) Sau đó tắt hết (b) sau đó tắt hết và lặp lại Verilog HDL Basics
module DICH8LED_TSP(clk, reset, LED8);
input clk, reset;
output reg [7:0] LED8;

always @(posedge clk)

if(reset)
LED8 = 8’b1000_0000;
else
LED8 = LED8 >> 1;
endmodule

31 Verilog HDL Basics

module DICH8LED_TSP_REPEAT(clk, reset,
LED8);
input clk, reset;
output reg [7:0] LED8;
always @(posedge clk)
if (reset)
LED8 = 8’b1000_0000;
else
if (LED8 == 8’b0000_0000)
LED8 = 8’b1000_0000;
else LED8 = LED8 >> 1;
endmodule 32 Verilog HDL Basics
 LED_SANG_DICH_PST (input clk,
input reset, output reg [7:0] LED)
clk state LED[7] LED[6] LED[5] LED[4] LED[3] LED[2] LED[1] LED[0]

posedge 1 0 0 0 0 0 0 0 1

posedge 2 0 0 0 0 0 0 1 0

posedge 3 0 0 0 0 0 1 0 0

posedge 4 0 0 0 0 1 0 0 0

posedge 5 0 0 0 1 0 0 0 0

posedge 6 0 0 1 0 0 0 0 0

posedge 7 0 1 0 0 0 0 0 0

posedge 8 1 0 0 0 0 0 0 0

posedge 9 0 0 0 0 0 0 0 0

posedge 1 0 0 0 0 0 0 0 1

(a) Sau đó tắt hết (b) sau đó tắt hết và lặp lại Verilog HDL Basics
 LED_SANG_DICH_TTR (input clk,
input reset, output reg [7:0] LED)
clk state LED[7] LED[6] LED[5] LED[4] LED[3] LED[2] LED[1] LED[0]

posedge 1 0 0 0 1 1 0 0 0

posedge 2 0 0 1 0 0 1 0 0

posedge 3 0 1 0 0 0 0 1 0

posedge 4 1 0 0 0 0 0 0 1

posedge 5 0 0 0 0 0 0 0 0

posedge 1 0 0 0 1 1 0 0 0

(a) Sau đó tắt hết (b) sau đó tắt hết và lặp lại Verilog HDL Basics
module DICH8LED_TTR(clk, reset, LED8);
input clk, reset;
output reg [7:0] LED8;

always @(posedge clk)

if(reset)
LED8 = 8’b0001_1000;
else
LED8[7:4] = LED8[7:4] << 1;
LED8[3:0] = LED8[3:0] >> 1;
endmodule
35 Verilog HDL Basics
module DICH8LED_TTR_REPEAT(clk, reset, LED8);
input clk, reset;
output reg [7:0] LED8;
always @(posedge clk)
if (reset)
LED8 = 8’b0001_1000;
else if (LED8==8’b0000_0000)
LED8 = 8’b0001_1000;
else
LED8[7:4] = LED8[7:4] << 1;
LED8[3:0] = LED8[3:0] >> 1;
endmodule
Or
LED8 = {LED8[6:4],1’b0, 1’b0, LED8[3:1]};
 LED_SANG_DICH_TNV (input clk,
input reset, output reg [7:0] LED)
clk state LED[7] LED[6] LED[5] LED[4] LED[3] LED[2] LED[1] LED[0]

posedge 1 1 0 0 0 0 0 0 1

posedge 2 0 1 0 0 0 0 1 0

posedge 3 0 0 1 0 0 1 0 0

posedge 4 0 0 0 1 1 0 0 0

posedge 5 0 0 0 0 0 0 0 0

posedge 1 0 0 0 0 0 0 0 0

(a) Sau đó tắt hết (b) sau đó tắt hết và lặp lại Verilog HDL Basics
 LED_SANG_DAN_TSP (input clk,
input reset, output reg [7:0] LED)
clk state LED[7] LED[6] LED[5] LED[4] LED[3] LED[2] LED[1] LED[0]

posedge 1 1 0 0 0 0 0 0 0

posedge 2 1 1 0 0 0 0 0 0

posedge 3 1 1 1 0 0 0 0 0

posedge 4 1 1 1 1 0 0 0 0

posedge 5 1 1 1 1 1 0 0 0

posedge 6 1 1 1 1 1 1 0 0

posedge 7 1 1 1 1 1 1 1 0

posedge 8 1 1 1 1 1 1 1 1

posedge 9 0 0 0 0 0 0 0 0

posedge 1 1 0 0 0 0 0 0 0

(a) Sau đó tắt hết (b) sau đó tắt hết và lặp lại Verilog HDL Basics
module SANGDAN_8LED_TSP(clk, reset, LED8);
input clk, reset;
output reg [7:0] LED8;
always @(posedge clk)
if(reset)
LED8 = 8’b1000_0000;
else if (LED8==8’hFF)
LED8 = 8’b0000_0000;
else if (LED8!=8’h00)
LED8 = LED8 >> 1; LED8[7] = 1’b1;
// LED8 = LED8 | LED8>>1;
// LED8 = 8’b10000000 + LED8>>1;
endmodule
Verilog HDL Basics
module SANGDAN_8LED_TSP_REPEAT(clk, reset,
LED8);
input clk, reset;
output reg [7:0] LED8;
always @(posedge clk)
if(reset)
LED8 = 8’b1000_0000;
else if (LED8==8’hFF)
LED8 = 8’b0000_0000;
else
LED8 = LED8 >> 1;
LED8[7] = 1’b1;
endmodule

40 Verilog HDL Basics

 LED_SANG_DAN_PST (input clk,
input reset, output reg [7:0] LED)
clk state LED[7] LED[6] LED[5] LED[4] LED[3] LED[2] LED[1] LED[0]

posedge 1 0 0 0 0 0 0 0 1

posedge 2 0 0 0 0 0 0 1 1

posedge 3 0 0 0 0 0 1 1 1

posedge 4 0 0 0 0 1 1 1 1

posedge 5 0 0 0 1 1 1 1 1

posedge 6 0 0 1 1 1 1 1 1

posedge 7 0 1 1 1 1 1 1 1

posedge 8 1 1 1 1 1 1 1 1

posedge 9 0 0 0 0 0 0 0 0

posedge 1 0 0 0 0 0 0 0 1

(a) Sau đó tắt hết (b) sau đó tắt hết và lặp lại Verilog HDL Basics
 LED_SANG_DAN_TTR (input clk,
input reset, output reg [7:0] LED)
clk state LED[7] LED[6] LED[5] LED[4] LED[3] LED[2] LED[1] LED[0]

posedge 1 0 0 0 1 1 0 0 0

posedge 2 0 0 1 1 1 1 0 0

posedge 3 0 1 1 1 1 1 1 0

posedge 4 1 1 1 1 1 1 1 1

posedge 5 0 0 0 0 0 0 0 0

posedge 1 0 0 0 1 1 0 0 0

(a) Sau đó tắt hết (b) sau đó tắt hết và lặp lại Verilog HDL Basics
 LED_SANG_DICH_TSP_PST (input
clk, input reset, input SS, input
MODE, output reg [7:0] LED)
clk state LED[7] LED[6] LED[5] LED[4] LED[3] LED[2] LED[1] LED[0]

posedge 1 1 0 0 0 0 0 0 0

posedge 2 0 1 0 0 0 0 0 0

posedge 3 0 0 1 0 0 0 0 0

posedge 4 0 0 0 1 0 0 0 0

posedge 5 0 0 0 0 1 0 0 0

posedge 6 0 0 0 0 0 1 0 0

posedge 7 0 0 0 0 0 0 1 0

posedge 8 0 0 0 0 0 0 0 1

posedge 9 0 0 0 0 0 0 0 0

posedge 1 1 0 0 0 0 0 0 0

(b) sau đó tắt hết và lặp lại

SS=0: dừng, SS=1: cho phép dịch
MODE=0: TSP, MODE=1: PST
LED_SANG_DICH_TSP_PST (input clk, input reset, input SS, input
MODE, output reg [7:0] LED)
always @ (posedge clk)
if (reset) out = 8’b0000_0000;
else
if (SS==1)
if (MODE==0) //TSP
if (out==8’b0000_0000)
out=8’b1000_0000;
else out=out>>1;
else //MODE==1 //PST
if (out==8’b0000_0000)
out=8’b0000_0001;
else out=out<<1;
else out = out;
endmodule
44 Verilog HDL Basics
LED_SANG_DICH_TTR_TNV (input clk, input reset, input SS, input
MODE, output reg [7:0] LED)
always @ (posedge clk)
if (reset) out = 8’b0000_0000;
else
if (SS==1)
if (MODE==0) %TTR
if (out==8’b0000_0000)
out=8’b0001_1000;
else out[7:4]=out[7:4]<< 1;
out[3:0]=out[3:0]>> 1;
else //MODE==1 %TNV
if (out==8’b0000_0000)
out=8’b1000_0001;
else begin //~Xilinx
out[7:4]=out[7:4]>> 1;
out[3:0]=out[3:0]<<1;
end
end
LED_SANG_DAN_TSP_PST (input clk, input reset, input SS, input MODE,
output reg [7:0] LED)
always @ (posedge clk)
if (reset) out = 8’b0000_0000;
else
if (SS==1)
if (MODE==0) //TSP
if (out==8’b1111_1111)
out=8’b0000_0000;
else if (out== 8’b0000_0000)
out= 8’b1000_0000;
else out=out>>1 | 8’b1000_0000;
else //MODE==1 //PST
if (out==8’b1111_1111)
out=8’b0000_0000;
else if (out== 8’b0000_0000)
out= 8’b0000_0001;
else out=out<<1 | 8’b0000_0001;
else out = out; 46 Verilog HDL Basics
endmodule