Thanks to visit codestin.com
Credit goes to www.scribd.com

Scribd
Upload
125 views4 pages

Verilog Module Examples

The document contains 9 questions, each describing a Verilog module. Q1 assigns the input vec to the output outv and assigns each bit of vec to individual outputs o0, o1, o2. Q2 assigns the lower and upper 8 bits of the 16-bit input in to the 8-bit outputs out_lo and out_hi respectively. Q3 concatenates 6 5-bit inputs to generate a 32-bit output with the inputs packed into the lower 24 bits and the remaining bits set to 1.

Uploaded by

vipako9305
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
125 views4 pages

Verilog Module Examples

The document contains 9 questions, each describing a Verilog module. Q1 assigns the input vec to the output outv and assigns each bit of vec to individual outputs o0, o1, o2. Q2 assigns the lower and upper 8 bits of the 16-bit input in to the 8-bit outputs out_lo and out_hi respectively. Q3 concatenates 6 5-bit inputs to generate a 32-bit output with the inputs packed into the lower 24 bits and the remaining bits set to 1.

Uploaded by

vipako9305
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Q1.

module top_module ( input wire [2:0] vec,

output wire [2:0] outv,

output wire o2,

output wire o1,

output wire o0 ); // Module body starts after module declaration

assign outv[0] = vec[0];

assign outv[1] = vec[1];

assign outv[2] = vec[2];

assign o0 = vec[0];

assign o1 = vec[1];

assign o2 = vec[2];

endmodule

Q2.

module top_module(

input wire [15:0] in,

output wire [7:0] out_hi,

output wire [7:0] out_lo );

assign out_lo = in[7:0];

assign out_hi = in[15:8];

endmodule

Q3.

module top_module (

input [4:0] a, b, c, d, e, f,

output [7:0] w, x, y, z );

assign {w,x,y,z} = { a [4:0], b[4:0], c[4:0], d[4:0],e[4:0],f[4:0],1'b1, 1'b1} ;

endmodule
Q4.

module top_module(

input [7:0] in,

output [7:0] out

);

assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};

endmodule

Q5.

module top_module (

input [7:0] in,

output [31:0] out );//

assign out = { {24{in[7]}},in[7:0]};

endmodule

Q6.

module top_module (

input a, b, c, d, e,

output [24:0] out );//

// The output is XNOR of two vectors created by

// concatenating and replicating the five inputs.

assign out = ~{{5{a}},{5{b}},{5{c}},{5{d}},{5{e}}} ^ {{5{a,b,c,d,e}}};

endmodule

Q7.

module top_module ( input clk, input d, output q );

wire w1,w2;

my_dff d0(.d(d),.clk(clk),.q(w1));

my_dff d1(.d(w1),.clk(clk),.q(w2));

my_dff d2(.d(w2),.clk(clk), .q(q));

endmodule
Q8.

module top_module (

input clk,

input [7:0] d,

input [1:0] sel,

output [7:0] q

);

wire [7:0]w1,w2,w3;

my_dff8 d0(.clk(clk), .d(d),.q(w1));

my_dff8 d1(.clk(clk), .d(w1), .q(w2));

my_dff8 d3(.clk(clk), .d(w2), .q(w3));

always @(*)

begin

case(sel)

2'b00 : q=d;

2'b01 : q=w1;

2'b10 : q=w2;

2'b11 : q=w3;

endcase

end

endmodule

Q9.

module top_module(

input [31:0] a,

input [31:0] b,

output [31:0] sum

);

wire w1;

wire cin;

add16 ad1(.a(a[15:0]), .b(b[15:0]),.sum(sum[15:0]),.cin(cin), .cout(w1));


add16 ad2(.a(a[31:16]), .b(b[31:16]),.sum(sum[31:16]), .cin(w1));

endmodule

You might also like