Project Work Title:

Physical Design Implementation and Closure of a

Low Power Subsystem with Multi-Voltage
Feedthroughs

Course No. : MELZG628T

Course Title: Project Work

Project Work Done by:

Amrut Narasinha Grampurohit

BITS ID: 2020HT80514

Degree Program: M.Tech Microelectronics

Research Area: Advanced VLSI Design

Project Work carried out at:

MediaTek Bangalore Private Limited,
Bangalore

BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE,

PILANI
VIDYA VIHAR, PILANI, RAJASTHAN -
333031.

July 2022
Contents

1. Broad Area of Work 3

2. Background 3

3. Objectives 4

4. Scope of Work 4

5. Plan of Work 4

6. Literature References 6

7. Particulars of the Supervisor and Examiner 6

8. Remarks of the Supervisor 7

9. Email Acknowledgement & Approval by Supervisor 9

10. Email Acknowledgement & Approval by Additional Examiner 10

1. Broad Area of Work

VLSI Design and Implementation has existed since the 1970s and was intended for designs with
a device/gate count of > 10K. While modern ICs have millions of gates, and Giga-Scale
Integration (GSI) was introduced to categorize multi-million gate designs, the nomenclature has
not changed in the market and we still use VLSI. When designing Digital ICs, the VLSI Design
Flow can be broadly divided into two phases (or) Flows: Frontend & Backend Flow.
• The Frontend Flow consists of identifying the architecture solution for a given IC
specification and transform it into an RTL Description, which is then followed by
Functional Verification.
• The Backend Flow is responsible for the Physical Implementation of the RTL Description
i.e., the RTL is converted into physical gates and interconnections. The main tasks in the
Backend Flow are Synthesis, Physical Design and Signoff (otherwise known as Design
Closure)

2. Background

While designing modern semiconductor chips, the abbreviation “PPA” i.e., Power, Performance
& Area is the main focus. Companies compete to achieve the best PPA so that the market is in
their favor. With the constant advancement in Technology Nodes (6nm, 5nm etc) used to
fabricate these complex chips, the constraints are made even more stringent during
implementation. For example, to optimize Power Consumption, we can employ Low Power
strategies such as Power Switches, Isolation mechanisms, Level Shifters and so on. But we must
also ensure that the design is able to function at the frequency spec with these Low Power
Constraints and also should not incur a major Area Overhead.

My team members and I at MediaTek Bangalore Private Limited take individual ownership of
the Netlist to GDS Implementation and Closure (Signoff) of various Subsystems that belong in
the Multimedia IP of a Smartphone SoC. With the help EDA tools licensed from industry leaders
such as Cadence® and Synopsys®, we are able to realize these complex designs onto Silicon
while meeting the PPA Targets. The Project Work will focus on the real-time implementation
of a subsystem that needs to use Low Power Strategies, and in addition, has a unique challenge
to implement Multi-Voltage Feedthroughs. TSMC 6nm Node is the Advanced Technology Node
that will be used for implementation, and this subsystem will be part of a Smartphone SoC in
MediaTek’s future lineup.
3. Objectives

The objectives of the project are as follows:

• Elaborate all the steps in the Netlist to GDS flow and provide an in-depth view of the
major challenges faced along with their resolutions.
• Elaborate on Design Closure (Signoff) and provide an in-depth view of the major
challenges faced along with their resolutions.

4. Scope of Work

Scope of this project is to take Full Ownership of the Netlist to GDS implementation and
the Signoff checks to ensure successful Tape-out of the Design/Subsystem.

5. Plan of Work

Fig 1 illustrates the work plan.

Phases Start Date-End Date Work to be done

Dissertation 23rd Jul 2022 – 30 Jul 2022 Literature Review and prepare
Outline Dissertation Outline
Floorplan 31 Jul 2022 – 8 Aug 2022 Floorplanning of design with placement
of Macros, VAs and Sanity Checks
Placement & 9 Aug 2022 – 30 Aug 2022 Iterations between Floorplan and
Optimization Placement depending on QoR, followed
by PPA optimization
CTS (Clock Tree 31 Aug 2022 – 21 Sep 2022 Building the Clock Tree w.r.t. to Clock
Synthesis) & Architecture of the design, followed
Post CTS by PPA optimization
Optimization
Route & Post 22 Sep 2022 – 6 Oct 2022 Detailed Routing of the design, analysis
Route of Route QoR followed by PPA
Optimization Optimization
ECO & 6 Oct 2022 – 10 Nov 2022 Timing & Functional ECOs done in
Signoff Phase parallel with Signoff checks.
Preparation of 11 Nov 2022 – 20 Nov 2022 Dissertation Reports and PPT.
Dissertation
Report &
Presentations
Fig 1: Physical Design Work Flow & Plan
6. Literature References

[1] Khoshrow Golshan. “Physical Design Essentials: An ASIC Design Implementation

Perspective”. New York, 2007

[2] J. Bhasker, Rakesh Chadha. “Static Timing Analysis for Nanometer Designs”. New
York, 2009

[3] Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic. “Digital Integrated

Circuits: A Design Perspective”. Bangalore, 2016

[4] S. Perremans, L. Claesen and H. De Man, "Static Timing Analysis of Dynamically

Sensitizable Paths”, 26th ACM/IEEE Design Automation Conference, Las Vegas, NV, USA,
1989, pp. 568-573

[5] J. Ganesh Prasad; Sudha R Karbari; Sajeesh Ammikkallingal; Sukanya Kamath Bellal,
“Analysis, Physical Design and Power Optimization of Design Block at Lower Technology
Node”, 2018 3rd IEEE International Conference on Recent Trends in Electronics,
Information & Communication Technology (RTEICT)

7. Particulars of the Supervisor and Examiner

Supervisor Additional Examiner

Name Samba Sivam Vemala Sharath Chandra L

Qualification M.Tech in Microelectronics M.Tech in ICs & Systems

with with
15+ yrs. Industrial experience 15+ yrs. Industrial Experience
Designation Senior Department Manager Department Manager

Employing
MediaTek Bangalore Private MediaTek Bangalore Private
Organization
Limited, Bangalore Limited, Bangalore
and Location

Phone No.(with
+91 9742272470 +91 9845285296
STD Code)

Email Address [email protected] [email protected]

8. Remarks of the Supervisor

The project focuses on the physical implementation of a cutting-edge technology node in

the semiconductor industry, and aims to provide an in-depth view on the execution process
and challenges faced by Physical Design Engineers. The student has the right skill set to
execute and complete the project. Furthermore, execution of the project will enhance his
knowledge which will be an asset to the organization. As the Supervisor, I approve the
project.

Information about the Supervisor:

• Name: Samba Sivam Vemala

• Designation: Senior Department Manager
• Employing Organization: MediaTek Bangalore Private Limited
• Email Address: [email protected]
 BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI
WORK INTEGRATED LEARNING PROGRAMMES (WILP) DIVISION
SECOND SEMESTER OF ACADEMIC YEAR 2022-2023

MELZG628T : PROJECT WORK OUTLINE

STUDENT ID No. 2020HT80514

NAME OF THE STUDENT AMRUT NARASINHA GRAMPUROHIT
STUDENT'S EMAIL ADDRESS [email protected]
STUDENT’S EMPLOYING MEDIATEK BANGALORE PRIVATE LIMITED,
ORGANIZATION & LOCATION BANGALORE
SUPERVISOR’S NAME SAMBA SIVAM VEMALA
SUPERVISOR’S EMPLOYING MEDIATEK BANGALORE PRIVATE LIMITED,
ORGANIZATION & LOCATION BANGALORE
SUPERVISOR’S EMAIL ADDRESS [email protected]
ADDITIONAL EXAMINAER’S NAME SHARATH CHANDRA L
ADDITIONAL EXAMINER’S EMPLOYING MEDIATEK BANGALORE PRIVATE LIMITED,
ORGANIZATION & LOCATION BANGALORE
ADDITIONAL EXAMINER’S EMAIL
ADDRESS [email protected]
PHYSICAL DESIGN IMPLEMENTATION AND
DISSERTATION / PROJECT / PROJECT
CLOSURE OF A LOW POWER SUBSYSTEM WITH
WORK TITLE
MULTI-VOLTAGE FEEDTHROUGHS

EMAIL VERIFICATION EMAIL VERIFICATION

Signature of Student Signature of Supervisor Signature of Additional Examiner

Name: AMRUT NARASINHA

Name: SAMBA SIVAM VEMALA Name: SHARATH CHANDRA L
GRAMPUROHIT