Notable Highlights
● 11+ years of experience in the area of RTL Front design.
● Sound knowledge in RTl Coding and debugging.
● FPGA Implementation and debugging skills at Board level.
● Interfaces worked on - DDR3 ,I2C, SPI,QSPI, Parallel Flash , Ibert ,DAC , ADC ,UART , Ethernet ,
Aurora Implementation etc
● Worked with SoC team to propagate block level sdc constraints to the top-level using primetime
tool and Formality checks
● Spyglass CDC constraints preparation, abstract models’ generation and using abstract models for
subsystems CDC quality Checks.
● Involved in constraint development, synthesis, power management check and timing closure
● For technical discussions I had been to ISRO Space Applications Centre (SAC), Ahmedabad, and
ISRO Headquarters, Bengaluru and so on.
Projects Handled
Project 1: SOC and Subsystem Integration From April 2024
Client: AiMicron
Responsible for SOC and Subsystem integration and Lint, CDC, PTPX, and Synthesis signoff, power
optimization using power artist and PTPX tools. Responsible to work with multiple teams and coordinate.
Project 2: Liberty Mesa (LTM)
Client: Intel (Jul 2022 – Apr 2024)
Tools used: SpyglassCDC, Spyglass Lint, VCS/Rivera, Fusion Compiler.
Roles and Responsibilities:
Writing complib src file generation using TCL script , DMZ flow compilation and debugging errors.
Created UPF files for checks for multiple blocks. Writing the timing constraint file and ensured proper
clock domain crossing (CDC) verification for multi-clock designs. Worked on Zero Wire Load (ZWL) for
timing model for SDC. Worked on RTL Comp check and Lint to make it compile free. Verification of
Ippwrmod for Leakage Power.
Project 3: Laser Device Driver (Nov 2018 to Mar 2022)
Laser Device Driver card is primarily an AC to DC power supply designed to drive high intensity laser
device, with 230V AC input and 15A, up to 96V DC output.
Role: Power estimation, Parallel NOR flash, DAC ,RTL code development for the following list of interfaces
to validate the customer unit which includes memories like SRAM ,Flash, DAC using SPI ,Parallel ADC,
Video DAC, QSPI, UART
Project 4: Aurora protocol for high-speed data exchange
Implementation of Aurora protocol for high-speed data exchange between FPGA 's in VPX platform.
Reusing and integrating FIFO IP with Aurora. AXI slave peripheral implementation of user defined
registers.
Project 5 : Data Encryption Standard (DES) (Apr 2017 to Nov 2018)
Description: Encrypting a 64-bit data with a 64-bit key is the objective of DES Algorithm. The DES Algorithm
is implemented using Verilog HDL. The algorithm has two parts of key generation and 16 rounds
implementation. The design has been verified with standard test cases simulated and performed all quality
checks.
Methodologies: Linting using spyglass, RTL logic synthesis using design compiler and update technical
documentation
Tools: VCS, Spyglass lint, Design Compiler
Project 6 : SOC level Quality checks (Dec 2015 to Apr 2017)
Description: Performed SOC level Compilation, CDC, Synthesis, and VCLP Quality checks
Methodologies: Linting and CDC using spyglass, RTL logic synthesis using design compiler and VCLP.
Tools: VCS, Spyglass lint, Design Compiler
Project 7 : Design and Integration of Watch Dog Timer using Verilog. (Aug 2015 to Dec 2015)
Responsibilities: I have implemented design and testbench of Watch Dog Timer using verilog. Watch Dog
Timer is a system which keeps track on system activity and whenever system is inactive for more than
timeout value then watch dog timer resets the system (brings out of hang situation)., fix the linting,
Spyglass CDC issues in RTL design.
Interrupt Controller is a design to collect interrupts from various peripheral controllers and forwards the
interrupts to processors on priority basis which is programmed by processor through APB protocol
interface. This continues till all interrupts are serviced by processor generated by peripheral controllers. It
interfaces with processor on one side using APB interface and other side with peripheral controllers.
Methodologies: RTL logic synthesis, CDC and Synthesis Constraint development and Signoff, Code coverage
and generate the technical documentation.
Tools: VCS, Spyglass lint, Spyglass CDC, Design Compiler
Project 8 : System Architecture Planning and Realization of Integrated Communication System for Naval
Networks (Aug 2013 to Apr 2015)
Description:
Integrated Communication System (ICS) is a single communication network to provide various integrated
services like Voice/Video/Data to the users in a single platform in the ship-borne network.
Methodologies: RTL logic synthesis, CDC and Synthesis Constraint development and Signoff, Code coverage
and generate the technical documentation.
Tools: VCS, Spyglass lint, Spyglass CDC, Design Compiler
