LOKESHWARAN KITTAPPAN

● Mobile no: +91-9585550593

● Email: [email protected]

⚪ Summary

 I have 16 years of experience in Electronics, specializing in RTL Development, Micro

Architecture, Electronic Hardware Design, and VLSI Tutoring.

 Expertise in the Verilog ,VHDL RTL programming for synthesis, simulation and
Implementation using Vivado,Vitis, Quratus ,ISE with these following process like Write RTL test
fixtures for simulation, Create a Finite State Machine (FSM)

 Experienced with the XILINX IP Core, place and route, floor plan, layout design, configuration
of bit files and MCS files for Download in to Xilinx FPGA & SOC. Hands on experience on
Microblaze,Nios & ARM Cortex-9 Processor architecture with AXI interfaces.

 Well experienced with Architecture of FPGA like Logic cells, Look up tables, CLB, BRAM,
DSP-48A, CDMA and supply rails like VCCO, VCCAUX, VCCINT, VREF. Strongly experienced in ILA
logic analyzer, Chip Scope Pro, Digital storage oscilloscope and various I/O standards of Xilinx &
Intel FPGA’s.

 Strong Hardware design and troubleshooting knowledge in FPGA’s and it’s interfacing with
external peripherals and modules like Thermal CCD, CMOS Image sensors, DDR Memories,
Motor Drivers, Sensors, ADC,DAC, Memories and Power rails and displays.

 Strong Knowledge in image sensor Interface with Zynq Soc with Thermal, Visible, Low light
Camera’s.

 Skilled and submitted the Project with Maven Silicon for RISC-V Architecture (3 Stage
Pipelining) as value added course through NXP.

⚪ Skills
Programming: Verilog,VHDL,System Verilog,Embedded C
Hardware: Xilinx & Intel FPGA’s and SOC’s
Script: TCL,Python
IDE’s: ISE, Vivado, SDK, Vitis, HLS, Quartus, GCC
ASIC Design: Genus,Xcelium,Verdi,Spyglass
OS: Windows, Unix
Architecture: RISC-V ,ARM-33 ,ARM-55 , RISC-V ,R5 ,M33
Protocols: I2C, SPI, UART, JTAG, MIPI CSI-2,SDI,VoSPI, 1-G Ethernet,USB,
High-Speed Transceivers concepts

Work Experience [SOC RTL Design & FPGA Validation]

NXP Semiconductors Pvt Ltd March 2022 to Present
Bangalore

RTL Design:
I have been working with RTL Design of Security IP’s like Asymmetric Crypto , FA
Protection Controller which are integrating with CPU for SOC security .

FPGA Validation:

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 I have been leading the Two members of FPGA Validation team and also doing all
hands on FPGA activities with SOC RTL to FPGA RTL conversion for validate the SOC with Xilinx
Virtex Ultrscale + FPGA.
Work Experience [ASIC Video Sub-system & USB Module Micro Architect]
Tessolve Semiconductor Pvt Ltd September 2021 to Feb2022
Bangalore

Roles & Responsibilities:

Role: Senior Design Lead
Client : Marvel Semiconductor

Project Module1:
Worked as Automotive ASIC Video Subsystem Micro Architect for Autonomous vehicle and
participating in the Micro architecture Development team for Interfacing Video Subsystem Unit
which have the multiple CSI-2 Cameras and Video Codec Unit which is Mapped with NOC Unit .

Project Module2:
Worked in same project for Synopsys USB3.1 PHY IP Interface with Host USB Controller
and PIPE & UTMI Interface in Physical layer .

Work Experience [FPGA Hardware Design Member in technical Team]

Tonbo Imaging Pvt Ltd October2020 to September 2021
Bangalore

Roles & Responsibilities:

Role: FPGA RTL Firmware Design Engineer

Projects Working:
1. Kinglet GeoCool camera interface with Cyclone-5 Altera FPGA
 Its a Cooled thermal camera which gives Camera Link output and its connected
with the Cyclone V SOC through Camera Link to 28-bit parallel converter .
 FPGA Configures the sensor Configuration register and cooler mechanism through
UART Protocol and the bytes are processed into the FPGA and the processed
parallel output’s are connected to connected to display .
2. Athena VGA Thermal Sensor Interface with Artix-7 FPGA

 Its a thermal camera which gives 14-bit parallel output and its connected with the
Artix-7 FPGA .The 14 bits data’s are processed into the FPGA and sending out to
display.

List of Processing techniques Used in FPGA

->Non Uniformity correction and 1-point NUT
->Sharpness & Brightness
->Histogram Equalization
->Bad Pixel removal
->Creating Meta data for sensor

Work Experience [FPGA Hardware Design Engineer]

Optimized Electrotech Pvt Ltd May2018 to October2020

Bangalore

Worked as a FPGA RTL Hardware Engineer in the platform of Xilinx FPGA’s & Zynq Devices.

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 Roles & Responsibilities:
Role: FPGA RTL Hardware Design Engineer
Responsibilities:
Projects Worked:
1. LWIR Sensors Interface with FPGA
2. Thermal Sensors Interface with FPGA
3. Frame Grabber for Multiple Sensor Interface
4. Camera link to LVDS Converter

->Designed RTL Hardware for Configuring the 5.5Mpixels (2560*2160) Top & Bottom based
Camera using JTAG Protocol,Capturing the Pixels data & Convert Grey scale data to binary, Scaling
the frame , Offset removal & Controller the various gain,Histogram equalization,Brightness
Correction & Sharpness Correction,8Bit & 16bit data alignment etc..

Then the Processed data is Sending to the CDMA by ARM Cortex A9 and writing into the DDR3 at
PS Side, from there the PS DDR data will be sent to PC through Ethernet by LWIP also same
happening in PL side DDR3 as well.

->Schematic design for custom Sensor board as well intermediate board between sensors FPGA.
->Found the FPGA & Zynq Boards or parts for various Prototypes (01,02,03).
->Creating I2C, UART, SPI, JTAG Protocols in Verilog and VHDL for Accelerometer and Gyroscope.

⚪ Work Experience [Xilinx FAE]

Excelpoint Systems (India) Private Limited April 2017 to May 2018
Bangalore

Roles & Responsibilities

Role: Xilinx Field Application Engineer

Responsibilities:
->Developed reference design for various Xilinx Development Boards like SP601, AC701, KC705,
VC707, ZC702, ZC706, ZCU102 etc.
->Correction in Architecture and suggested alternative for various customers for various types of
projects like

 ADAS (Zynq Ultra scale +MPSOC )

 Medical Eye Gaze Project (Zynq 7000)
 Electronic Voting Machine (Spartan 6)
 5G Research Project for IIT Chennai (RFSOC)
 SDI to MIPI Protocol Converter & HDMI to MIPI Converter etc..
 Conducting presentation for Xilinx Products and Applications for various customers
 Verifying the Customer Schematic for various Projects and suggest the corrections
 Solving the customer issues like Vivado & ISE Tools error, Design timing error,
License issues, Clocking issues etc.
 Attended 15 Days training for Xilinx applications-based architecture Development
at Xilinx R&D (Dublin, Ireland))

⚪ Work Experience [Design]

GENN CONTROLS INDIA PVT LTD Sep 2013 to April 2017
Coimbatore

Roles & Responsibilities

Role:FPGA Firmware Developer & Hardware Designer

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 Responsibilities:

 Verilog & VHDL RTL Design for complete Project

 FPGA Board Schematic Design
 Interfacing the Peripherals like EEPROM, FLASH, DAC, ADC, HMI with various protocols
like UART, SPI, I2S, Ethernet etc.
 Complete control of FPGA RTL Firmware for Lines Scan & Area scan image sensor .
 Fixing the Camera in a Color sorting Machine and checking the alignment, Focus &
Tuning the camera according to the Focus
 Conducting Presentation to the customers
 Doing test and trial with various commodities depends upon its color level

 We have completed the task of sorting of different color material using color camera’s and which is
interfaced with SPARTAN-6 Custom board which is designed by our own effort and skills. For
Programming, I am using the VERILOG HDL for create the. BIT &. MCS Files which is compiled
through ISE 14.7 of Xilinx tool also code has been implementing through the same.

List of projects worked at GENN Controls India Pvt Ltd

1 Color sorting of various commodities Using FPGA

This project is mainly Interfacing the Image sensors, with the FPGA through the Clock
which is generated by the FPGA with the timing of camera scan sequence. Depends upon the
analog signal which has come from the image sensor the scanned commodity will be
segregated depends upon the sensitivity of the image sensor with respect to commodity and
light source.

2 Grading of commodity size using FPGA

This project is mainly for grade and sort the commodities depend upon the size and color
of the commodity using PYTHON 1.3/0.5/0.3 Megapixels Global Shutter CMOS Image Sensors
which will give the digital output of 12-bit resolution.

⚪ Work Experience [Teaching]

VIVEKANANDHA ENGINEERING COLLEGE FOR WOMEN Aug 2009 to April 2013
Sankari West, Salem Dist, TN, India

 Worked as an Assistant professor, College Placement incharge, Dept Project coordinator, College
Industrial visit coordinator for three years (2010-2013).
 Internally guided for the project of “Digital re balancing loop for Gyroscope” which had executed
at VSSC, Thiruvanandhapuram.
 Internally guided for the project of “Boiler Feed Pump Control using PLC” this had executed at
NTPC, Kayamkulam.
 Internally guided for the project of “Head movement-based PC control” this had executed at
KELETRON, Ernakulum.
 Life time member for ISTE, member in CSI (Computer society of India).
 Worked in the area of AICTE, ISO Certification, and FDP during those service periods as assistant
professor.
 Organized training material for board meetings, presentations, and training sessions for
management.

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Achievements

 With my individual and team effort we achieved the task of Technology conversion from
Microcontroller to FPGA for sorting Machines at very first time in Coimbatore.
 I have done the complete RTL coding (from scratch) for the Long range surveillance camera
interface with Zync7000 SOC and it is used by Optimized Electro Tech for all the camera’s right
now .

⚪ Certifications from various Institutions

 Digital System Design with Verilog and Vivado(One week),

 RISC-V Design with Maven Silicon (Three Months)
 Digital System Design with VHDL and Vivado(One week),
 DSP Design using System Generator
 C-Based design -HIGH Level Synthesis with Vivado Hlx Tool(One week),
 Xilinx Design Constraints and Static Timing Analysis(One week),
 Zynq Ultrscale+ MPSOC For the Software Developers (Three days),
 Ultra Fast Design Methodology Using Xilinx Vivado,
 Designing with ZYNQ SOC and its Applications (One Week),
 Designing with Ultrascale and Ultrscale+ Architecture,
 Embedded System Design with Petalinux Tools(Three Days)

⚪ Work Experience [Teaching]

NIIT Jan 2008 to July 2009
Erode, TN, India

 Worked as a .NET Framework trainer with the certification from Microsoft for ASP.NET – C# Web
Design.

⚪ Summary of Academic Chronicles

UNDER GRADUATION [2004-2007]

Secured first class in B.E. (Electronics & communication Engineering) from M.Kumarasamy
college of engineering, karur, affiliated to Anna University, Chennai.

DIPLOMA [1999-2002]
Secured first class in Diploma (Electrical & Electronics Engineering) from N.P.C.A.P.T,
Kottagiri, affiliated to Directorate of technical education.

Personal Details

DOB : 15th, May 1983

Nationality : Indian
Marital status : Married
Languages : English,Tamil, Malayalam,Kannada,Telugu,Hindi

Date: K.Lokeshwaran

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