VLSI Design
ECE314
Spring 2022
M3: VLSI Design
Lecture 1
Implementation Approaches
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory
D. Khalil ECE314 – M3 Lecture 1 1
Outline
Digital Circuit Implementation Approaches
Custom Semicustom
Cell-Based Array-Based
Standard Macro Pre-Diffused Pre-Wired Arrays
Cells Cells Arrays (FPGA's)
D. Khalil ECE314 – M3 Lecture 1 2
Custom Approach
• Handcrafting circuit and layout at the transistor level
• Difficult implementation due to minimal design automation
• Time consuming, high design cost, and long time-to-market
• Speed / power / area can be highly optimized
• Rare to use, typical cases are:
– Block reused many times (eg. library cells)
– Cost divided by a large volume (eg. Critical blocks in processor)
– Cost is not the prime criterion (eg. space applications)
D. Khalil ECE314 – M3 Lecture 1 3
Outline
Digital Circuit Implementation Approaches
Custom Semicustom
Cell-Based Array-Based
Standard Macro Pre-Diffused Pre-Wired Arrays
Cells Cells Arrays (FPGA's)
D. Khalil ECE314 – M3 Lecture 1 4
Cell-Based Approach
• Design uses a library of predesigned cells
• Easy implementation due to the use of design automation
• Library development is expensive and time-consuming
(provided by the fab)
• Less design time, less cost, and shorter time-to-market
• Limited speed / power / area optimization
• Most popular implementation approach
D. Khalil ECE314 – M3 Lecture 1 5
Standard Cells
• Library of standard cells:
– All logic gates of different fan-in and fan-out
– Flip-flops and latches
– Can have more complex functions: decoders, encoders, comparators…
• Each cell must have:
– Circuit schematic, symbol, and physical layout
– Models: behavioral, Verilog/VHDL, detailed timing, power, routing
• Typically available from fabs and library vendors
• Standard cells are redesigned for every technology generation
• Complex cells can be created by compilers to enable design
flexibility and generates layout at compilation (easier to use and
more adaptive to technology changes)
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Standard Cell Example
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Macro Cells
• Cells of more complex circuits:
– Multiplier, memories, data-path, embedded processor, …
• Macro reuse should offset initial design cost
• Increasing popularity
• Hard Macro
– Given functionality and defined layout
– Can be parameterized (the generator is called module compiler)
– Can achieve dense layout
– Optimized and predictable timing, power and area performance
– Cannot export to other technologies
– Typically used for embedded memories and microprocessors
D. Khalil ECE314 – M3 Lecture 1 8
Macro Cells
• Soft Macro
– Given functionality but without specific layout
– Needs synthesis, placement, and routing
– Final layout can differ each time it is instantiated
– Timing, power, and area are only determined after generation
– Typically uses structural generators
– Generators also provide timing constraints for placement & routing
– Easily exported to other technologies
– More popular than hard macros
• IP (Intellectual Property) Macro
– Macros bought from IP provider
– Buyer typically cannot reverse engineer the IP (black-box)
D. Khalil ECE314 – M3 Lecture 1 9
Example: Hard Macro
• 25632 (or 8192 bit) SRAM
• Generated by a hard-macro module compiler
• Provides fixed layout and accurate timing and power
D. Khalil ECE314 – M3 Lecture 1 10
Example: Soft Macro
• 8x8 booth Multipliers By
Synopsys ModuleCompiler
• Standard-cell methodology
• Different aspect ratios, timing,
power with different synthesis
and layout
D. Khalil ECE314 – M3 Lecture 1 11
Outline
Digital Circuit Implementation Approaches
Custom Semicustom
Cell-Based Array-Based
Standard Macro Pre-Diffused Pre-Wired Arrays
Cells Cells Arrays (FPGA's)
D. Khalil ECE314 – M3 Lecture 1 12
Pre-Diffused Array
• Also called “mask-programmable” gate arrays
• Wafers contain arrays of primitive cells with all fabrication steps
done except metal/via layers to achieve programmability
through metal/via masks
• Fast fabrication turnaround time (only metal/via layers)
• Low cost since high cost fabrication steps are shared
• One-time programmability only
• Less design time, less cost, and shorter time-to-market
• Very limited speed / power / area optimization
D. Khalil ECE314 – M3 Lecture 1 13
Pre-Wired Arrays
• Early versions: PROM, PAL, and PLA
• Modern version: FPGA “field-programmable gate arrays”
• Chips are pre-fabricated with programmable logic and programmable
interconnects and achieve full programmability in the field (location)
• Moderate fabrication cost since all fabrication steps are shared
• No fabrication steps after design at all
• Much less design time & cost, and much shorter time-to-market
• Very limited speed / power / area optimization
• Configuration (program) can be stored using different techniques:
– Fuse (one-time programmability only)
– Non-volatile EPROM (can be reprogrammed, keeps program indefinitely)
– Volatile RAM (can be reprogrammed, only keeps program while powered)
D. Khalil ECE314 – M3 Lecture 1 14
Programmable Logic (CLB)
• Programmable logic building unit is
the configurable logic block (CLB)
• Look up table (LUT)-based CLB consists of:
– N-bit LUT for combinational logic.
– Optional FF for sequential logic.
• N-bit LUT acts as a general purpose N-input
logic gate (truth table stored in 2N latches).
• Truth table latches and FF configuration latch
get their values during configuration.
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Programmable Wiring (PSM)
• FPGA layout is like a fabric with CLBs placed in a 2D array.
• Wires run horizontally & vertically between CLBs.
• Mesh-based programmable wiring uses programmable switch
matrices (PSMs) to connect all CLBs together.
• 2 types of PSM:
– Connect box:
connects CLB I/Os
to adjacent wires.
– Switch box:
Connects horizontal
and vertical wires.
D. Khalil ECE314 – M3 Lecture 1 16
Modern FPGAs
• Modern FPGAs use high speed EG: Xilinx Virtex II Pro
FPGA fabric and embed important
hardware (RAM, multipliers, ALUs,
full processor, high-speed I/Os) to
offer competitive performance/price
to cell-based implementation.
• Attractive for small volume and
low/medium performance:
– Off-the-shelf
– Low development cost/time FPGA Fabric
– Shortest time-to-market High-speed I/O
– Ease of upgrade (reprogrammability) Embedded memories
– Competitive performance Embedded PowerPC
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References
• Rabaey, chapter 8
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