+

William Stallings + Chapter 12

Computer Organization
Instruction Sets:
and Architecture
10th Edition Characteristics and Functions
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NJ. All rights reserved.

1 2

+Machine Instruction Characteristics Elements of a Machine Instruction

 The operation of the processor is determined by
the instructions it executes, referred to as machine Operation code
(opcode)
Source operand
reference
instructions or computer instructions • Specifies the operation • The operation may
to be performed. The involve one or more
operation is specified source operands, that
by a binary code, is, operands that are
known as the operation inputs for the operation
code, or opcode
 The collection of different instructions that the
processor can execute is referred to as the
processor’s instruction set Result operand Next instruction
reference reference
• The operation may • This tells the processor
produce a result where to fetch the next
instruction after the
execution of this
 Each instruction must contain the information instruction is complete

required by the processor for execution

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3 4
 Source and result operands can be
Instruction
fetch
Operand
fetch
Operand
store in one of four areas:
3) Processor register
 A processor contains one or
Multiple Multiple
1) Main or virtual memory more registers that may be
operands results  As with next instruction referenced by machine
references, the main or virtual instructions.
memory address must be
Instruction Instruction Operand
Data
Operand
supplied  If more than one register
address operation address address exists each register is
Operation
calculation decoding calculation calculation
assigned a unique name or
number and the instruction
Instruction complete,
Return for string 2) I/O device must contain the number of
or vector data the desired register
fetch next instruction  The instruction must specify
the I/O module and device for
the operation. If memory-
mapped I/O is used, this is
4) Immediate
just another main or virtual
memory address  The value of the operand is
contained in a field in the
Figure 12.1 Instruction Cycle State Diagram instruction being executed
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+ +
Instruction Representation Instruction Representation
 Opcodes are represented by abbreviations
 Within the computer each instruction is represented by a called mnemonics
sequence of bits
 Examples include:
 The instruction is divided into fields, corresponding to the
 ADD Add
constituent elements of the instruction
 SUB Subtract
4 bits 6 bits 6 bits  MUL Multiply
Opcode Operand Reference Operand Reference  DIV Divide
 LOAD Load data from memory
16 bits
 STOR Store data to memory

 Operands are also represented symbolically

Figure 10.2 A Simple Instruction Format  Each symbolic opcode has a fixed binary representation
Figure 12.2 A Simple Instruction Format  The programmer specifies the location of each symbolic operand

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 Instruction Types Instruction Comment
SUB Y, A, B Y¬A–B
•Arithmetic instructions provide
computational capabilities for
•Movement of data into or
out of register and or
MPY T, D, E T¬D´E
processing numeric data memory locations ADD T, T, C T¬T+C
•Logic (Boolean) instructions operate DIV Y, Y, T Y¬Y÷T
on the bits of a word as bits rather
than as numbers, thus they provide
capabilities for processing any
other type of data the user may wish
to employ Instruction Comment
(a) Three-address instructions
Data Data LOAD D AC ¬ D
processing storage MPY E AC ¬ AC ´ E
Instruction Comment ADD C AC ¬ AC + C
MOVE Y, A Y¬A STOR Y Y ¬ AC
SUB Y, B Y¬Y–B LOAD A AC ¬ A
MOVE T, D T¬D SUB B AC ¬ AC – B
MPY T, E T¬T´E DIV Y AC ¬ AC ÷ Y
ADD T, C T¬T+C STOR Y Y ¬ AC
Data
Control DIV Y, T Y¬Y÷T
movement
•Test instructions are used to test the •I/O instructions are needed (b) Two-address instructions (c) One-address instructions
value of a data word or the status of a to transfer programs and
computation data into memory and the
results of computations
•Branch instructions are used to branch back out to the user
to a different set of instructions
depending on the decision made
A- B
Figure 12.3 Programs to Execute Y=
C+ (D´ E)
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9 10

Instruction Set Design

Table 12.1 Very complex because it affects so many aspects of the computer system

Utilization of Instruction Addresses

(Non-branching Instructions)
Defines many of the functions performed by the processor

Number of Addresses Symbolic Representation Interpretation

3 OP A, B, C A ¬ B OP C
Programmer’s means of controlling the processor
2 OP A, B A ¬ A OP B
1 OP A AC ¬ AC OP A
0 OP T ¬ (T – 1) OP T

AC = accumulator
Fundamental design issues:
T = top of stack
(T – 1) = second element of stack Operation repertoire Data types Instruction format Registers Addressing
A, B, C = memory or register locations • How many and which • The various types of data • Instruction length in bits, • Number of processor • The mode or modes by
operations to provide and upon which operations are number of addresses, size registers that can be which the address of an
how complex operations performed of various fields, etc. referenced by instructions operand is specified
should be and their use

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11 12
 + Numbers
Types of Operands
 All machine languages include numeric data types

 Numbers stored in a computer are limited:

 Limit to the magnitude of numbers representable on a machine
 In the case of floating-point numbers, a limit to their precision

 Three types of numerical data are common in computers:

 Binary integer or binary fixed point
 Binary floating point
 Decimal

 Packed decimal
 Each decimal digit is represented by a 4-bit code with two digits
stored per byte
 To form numbers 4-bit codes are strung together, usually in
multiples of 8 bits

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+ +
Characters Logical Data
 An n-bit unit consisting of n 1-bit items of data, each item
 A common form of data is text or character strings having the value 0 or 1
 Textual data in character form cannot be easily stored or  Two advantages to bit-oriented view:
transmitted by data processing and communications systems
because they are designed for binary data
 Memory can be used most efficiently for storing an array of
 Most commonly used character code is the International Boolean or binary data items in which each item can take on only
Reference Alphabet (IRA) the values 1 (true) and 0 (false)

 Referred to in the United States as the American Standard Code

for Information Interchange (ASCII)  To manipulate the bits of a data item
 If floating-point operations are implemented in software, we
 Another code used to encode characters is the Extended need to be able to shift significant bits in some operations
Binary Coded Decimal Interchange Code (EBCDIC)  To convert from IRA to packed decimal, we need to extract the
 EBCDIC is used on IBM mainframes rightmost 4 bits of each byte

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15 16
 Data Type Description Byte unsigned integer
7 0
General Byte, word (16 bits), doubleword (32 bits), quadword (64 bits),
and double quadword (128 bits) locations with arbitrary binary Word unsigned integer
contents. 15 0

Integer A signed binary value co4ntained in a byte, word, or doubleword, Doubleword unsigned integer
using twos complement representation. 31 0

Ordinal An unsigned integer contained in a byte, word, or doubleword.

Quadword unsigned integer
Unpacked binary coded
decimal (BCD)
A representation of a BCD digit in the range 0 through 9, with one
digit in each byte. Table 12.2 63

twos comp
sign bit
0

Byte signed integer

Packed BCD Packed byte representation of two BCD digits; value in the range 0 7 0
(twos complement)
to 99. sign bit
Word signed integer
Near pointer A 16-bit, 32-bit, or 64-bit effective address that represents the
x86 15 0
(twos complement)
offset within a segment. Used for all pointers in a nonsegmented sign bit
memory and for references within a segment in a segmented Doubleword signed integer

Data Types
memory. 31 0
(twos complement)
sign bit
Far pointer A logical address consisting of a 16-bit segment selector and an Quadward usigned integer
offset of 16, 32, or 64 bi ts. Far pointers are used for memory 63 0
(twos complement)t
references in a segmented memory model where the identity of a sign bit
segment being accessed must be specified explicitly. exp signif.
Half precision
15 9 0
floating point
Bit field A contiguous sequence of bits in which the position of each bit is
sign bit
considered as an independent unit. A bit string can begin at any bit Single precision
exp significand
position of any byte and can contain up to 32 bits. 31 22 0
floating point
Bit string A contiguous sequence of bits, containing from zero to 232 – 1 sign bit
Double precision
exp significand
bits. 63 51 0
floating point
Byte string A contiguous sequence of bytes, words, or doublewords, sign bit integer bit
containing from zero to 232 – 1 bytes. exponent significand
Double extended precision
floating point
79 63 0
Floating point See Figure 12.4.
Packed SIMD (single Packed 64-bit and 128-bit data types
instruction, multiple data) Figure 12.4 x86 Numeric Data Formats

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17 18

+ ARM Data Types

Single-Instruction-Multiple-Data ARM processors support

(SIMD) Data Types data types of:

•8 (byte)
•16 (halfword)
•32 (word) bits in length

 Introduced to the x86 architecture as part of the extensions of the

instruction set to optimize performance of multimedia applications
All three data types can Alignment checking
 These extensions include MMX (multimedia extensions) and SSE also be used for twos •When the appropriate control
complement signed bit is set, a data abort signal
(streaming SIMD extensions) integers indicates an alignment fault for
attempting unaligned access

 Data types:
 Packed byte and packed byte integer
 Packed word and packed word integer
 Packed doubleword and packed doubleword integer
 Packed quadword and packed quadword integer
For all three data types Unaligned access
 Packed single-precision floating-point and packed double-precision an unsigned
floating-point interpretation is •When this option is enabled,
the processor uses one or
supported in which the more memory accesses to
value represents an generate the required transfer
unsigned, nonnegative of adjacent bytes transparently
to the programmer
integer
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19 20
 Type Operation Name Description
Move (transfer) Transfer word or block from source to destination
Data bytes Store Transfer word from processor to memory
in memory Load (fetch) Transfer word from memory to processor
(ascending address values Exchange Swap contents of source and destination
Data Transfer
from byte 0 to byte 3) Clear (reset) Transfer word of 0s to destination

Table 12.3
Byte 3 Set Transfer word of 1s to destination
Push Transfer word from source to top of stack
Byte 2 Pop Transfer word from top of stack to destination
Add Compute sum of two operands
Byte 1
Common
Subtract Compute difference of two operands

Byte 0 Multiply Compute product of two operands

Arithmetic
Divide
Absolute
Compute quotient of two operands
Replace operand by its absolute value
Instruction Set
Negate
Increment
Change sign of operand
Add 1 to operand
Operations
31
Byte 3 Byte 2 Byte 1 Byte 0
0 31
Byte 0 Byte 1 Byte 2 Byte 3
0 Decrement
AND
Subtract 1 from operand
Perform logical AND
(page 1 of 2)
OR Perform logical OR
ARM register ARM register NOT (complement) Perform logical NOT
Exclusive-OR Perform logical XOR
program status register E-bit = 0 program status register E-bit = 1 Test Test specified condition; set flag(s) based on outcome
Logical
Compare Make logical or arithmetic comparison of two or more
operands; set flag(s) based on outcome
Set Control Class of instructions to set controls for protection
Variables purposes, interrupt handling, timer control, etc.
Shift Left (right) shift operand, introducing constants at end (Table can be found on page
Figure 12.5 ARM Endian Support - Word Load/Store with E-bit 426 in textbook.)
Rotate Left (right) shift operand, with wraparound end
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21 22

Table 12.4
Type Operation Name Description
Jump (branch) Unconditional transfer; load PC with specified address
Jump Conditional Test specified condition; either load PC with specified
address or do nothing, based on condition Processor Actions for Various Types of Operations
Jump to Subroutine Place current program control information in known
location; jump to specified address
Transfer data from one location to another
Return Replace contents of PC and other register from known

Execute
location
Fetch operand from specified location and execute as
Table 12.3 Data Transfer
If memory is involved:
Determine memory address
Transfer of Control instruction; do not modify PC
Skip Increment PC to skip next instruction
Perform virtual-to-actual-memory address transformation
Check cache
Skip Conditional Test specified condition; either skip or do nothing based
on condition Common Initiate memory read/write
Halt
Wait (hold)
Stop program execution
Stop program execution; test specified condition
Instruction Set May involve data transfer, before and/or after
Arithmetic
No operation
repeatedly; resume execution when condition is satisfied
No operation is performed, but program execution is Operations Perform function in ALU
Set condition codes and flags
(page 2 of 2)
continued
Input (read) Transfer data from specified I/O port or device to
destination (e.g., main memory or processor register)
Logical Same as arithmetic
Output (write) Transfer data from specified source to I/O port or device Similar to arithmetic and logical. May involve special logic to
Conversion
Input/Output Start I/O Transfer instructions to I/O processor to initiate I/O perform conversion
operation
Update program counter. For subroutine call/return, manage
Test I/O Transfer status information from I/O system to specified Transfer of Control
destination parameter passing and linkage
Translate Translate values in a section of memory based on a table
of correspondences Issue command to I/O module
Conversion I/O
(Table can be found on page
Convert Convert the contents of a word from one form to another
426 in textbook.)
If memory-mapped I/O, determine memory-mapped address
(e.g., packed decimal to binary)

(Table can be found on page 427 in textbook.)

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23 24
 Table 12.5
Data Transfer Examples of IBM EAS/390 Data Transfer Operations
Operation Number of Bits
Mnemonic Name Transferred Description
L Load 32 Transfer from memory to register
LH Load Halfword 16 Transfer from memory to register
LR Load 32 Transfer from register to register
LER Load (Short) 32 Transfer from floating-point register to
floating-point register
Must specify: LE Load (Short) 32 Transfer from memory to floating-point
register
• Location of the source and
destination operands LDR Load (Long) 64 Transfer from floating-point register to
Most fundamental type of • The length of data to be floating-point register
machine instruction transferred must be indicated LD Load (Long) 64 Transfer from memory to floating-point
• The mode of addressing for each register
operand must be specified
ST Store 32 Transfer from register to memory
STH Store Halfword 16 Transfer from register to memory
STC Store Character 8 Transfer from register to memory
STE Store (Short) 32 Transfer from floating-point register to
memory
STD Store (Long) 64 Transfer from floating-point register to
memory
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25 26

+  Most machines provide the basic arithmetic

operations of add, subtract, multiply, and divide

 These are provided for signed integer (fixed- Table 12.6

point) numbers
Basic Logical Operations
 Often they are also provided for floating-point
and packed decimal numbers

 Other possible operations include a variety of

single-operand instructions: P Q NOT P P AND Q P OR Q P XOR Q P=Q
 Absolute Arithmetic 0 0 1 0 0 0 1
 Take the absolute value of the operand
0 1 1 0 1 1 0
 Negate
1 0 0 0 1 1 0
 Negate the operand
 Increment 1 1 0 1 1 0 1
 Add 1 to the operand
Decrement
 Subtract 1 from the operand

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27 28
 0

(a) Logical right shift

0
Table 12.7
(b) Logical left shift

S
Examples of Shift and Rotate Operations
(c) Arithmetic right shift

0 Input Operation Result

S
10100110 Logical right shift (3 bits) 00010100
(d) Arithmetic left shift

10100110 Logical left shift (3 bits) 00110000

10100110 Arithmetic right shift (3 bits) 11110100
(e) Right rotate
10100110 Arithmetic left shift (3 bits) 10110000
10100110 Right rotate (3 bits) 11010100
(f) Left rotate 10100110 Left rotate (3 bits) 00110101
Figure 12.6 Shift and Rotate Operations

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29 30

+
Instructions that Input/Output
change the
format or Conversion  Variety of approaches taken:
operate on the  Isolated programmed I/O
format of data
 Memory-mapped programmed I/O
 DMA
 Use of an I/O processor
An example of a
more complex
editing
instruction is the
An example EAS/390  Many implementations provide only a few I/O
is converting Translate (TR) instructions, with the specific actions specified by
from instruction parameters, codes, or command words
decimal to
binary

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31 32
 System Control +
Transfer of Control
Instructions that can be executed only while the processor is in a
certain privileged state or is executing a program in a special  Reasons why transfer-of-control operations are required:
privileged area of memory
 It is essential to be able to execute each instruction
Typically these instructions are reserved for the use of the more than once
operating system
 Virtually all programs involve some decision making
 It helps if there are mechanisms for breaking the task up
Examples of system control operations: into smaller pieces that can be worked on one at a time

 Most common transfer-of-control operations found in

A system control instruction An instruction to read or Access to process control
may read or alter a control modify a storage protection blocks in a instruction sets:
register key multiprogramming system
 Branch
 Skip
 Procedure call
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33 34

Memory
address Instruction Skip Instructions
200
201 Typically implies that one
202 SUB X, Y
203 BRZ 211 instruction be skipped,
Unconditional Includes an implied thus the implied address
branch Conditional address equals the address of the
branch next instruction plus one
210 BR 202 instruction length
211

225 BRE R1, R2, 235

Conditional
branch
Because the skip
235 instruction does not Example is the
require a destination increment-and-skip-if-
address field it is free to zero (ISZ) instruction
do other things
Figure 12.7 Branch Instructions
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35 36
 +
Addresses Main Memory
4000
Procedure Call Instructions 4100 CALL Proc1
Main
4101 Program

 Self-contained computer program that is incorporated into a

larger program 4500

 At any point in the program the procedure may be invoked, or called

4600 CALL Proc2
 Processor is instructed to go and execute the entire procedure and 4601 Procedure
then return to the point from which the call took place 4650 CALL Proc2 Proc1
4651
 Two principal reasons for use of procedures: RETURN
 Economy
 A procedure allows the same piece of code to be used many times 4800

 Modularity Procedure
Proc2

 Involves two basic instructions: RETURN

 A call instruction that branches from the present location to the
procedure (a) Calls and returns (b) Execution sequence
 Return instruction that returns from the procedure to the place from
which it was called
Figure 12.8 Nested Procedures
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37 38

Stack
y2
Pointer
y1

Old Frame Pointer Frame

4601 4651 Pointer
4101 4101 4101 4101 4101 Q: Return Point
Stack
(a) Initial stack (b) After (c) Initial (d) After (e) After (f) After (g) After x2 x2
contents CALL Proc1 CALL Proc2 RETURN CALL Proc2 RETURN RETURN Pointer

x1 x1

Old Frame Pointer Frame Old Frame Pointer

Pointer

P: Return Point P: Return Point

Figure 12.9 Use of Stack to Implement Nested Procedures of Figure 12.8
(a) P is active (b) P has called Q

Figure 12.10 Stack Frame Growth Using Sample Procedures P and Q

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39 40
 + Table 12.8
x86 Operation Types
x86 Status Flags
 The x86 provides a complex array of operation types including a
number of specialized instructions Status Bit Name Description

 The intent was to provide tools for the compiler writer to produce CF Carry Indicates carrying or borrowing out of the left-most bit position
optimized machine language translation of high-level language following an arithmetic operation. Also modified by some of
programs the shift and rotate operations.

 Provides four instructions to support procedure call/return: PF Parity Parity of the least-significant byte of the result of an arithmetic
 CALL or logic operation. 1 indicates even parity; 0 indicates odd
 ENTER
parity.
 LEAVE AF Auxiliary Carry Represents carrying or borrowing between half-bytes of an 8-bit
 RETURN arithmetic or logic operation. Used in binary-coded decimal
arithmetic.
 When a new procedure is called the following must be performed upon
entry to the new procedure: ZF Zero Indicates that the result of an arithmetic or logic operation is 0.
 Push the return point on the stack SF Sign Indicates the sign of the result of an arithmetic or logic
 Push the current frame pointer on the stack operation.
 Copy the stack pointer as the new value of the frame pointer
 Adjust the stack pointer to allocate a frame OF Overflow Indicates an arithmetic overflow after an addition or subtraction
for twos complement arithmetic.
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41 42

Category Instruction Description

Symbol Condition Tested Comment PADD [B, W, D] Parallel add of packed eight bytes, four 16-bit words, or two 32-bit
A, NBE CF=0 AND ZF=0 Above; Not below or equal (greater than, doublewords, with wraparound.
PADDS [B, W] Add with saturation.
unsigned)
PADDUS [B, W] Add unsigned with saturation
AE, NB, NC CF=0 Above or equal; Not below (greater than or PSUB [B, W, D] Subtract with wraparound.
PSUBS [B, W] Subtract with saturation.

Table
equal, unsigned); Not carry Arithmetic PSUBUS [B, W] Subtract unsigned with saturation
B, NAE, C CF=1 Below; Not above or equal (less than, PMULHW Parallel multiply of four signed 16-bit words, with high-order 16

BE, NA CF=1 OR ZF=1

unsigned); Carry set
Below or equal; Not above (less than or 12.9 PMULLW
bits of 32-bit result chosen.
Parallel multiply of four signed 16-bit words, with low-order 16 bits
of 32-bit result chosen.
Table 12.10
PMADDWD Parallel multiply of four signed 16-bit words; add together adjacent
equal, unsigned) pairs of 32-bit results.
E, Z ZF=1 Equal; Zero (signed or unsigned) PCMPEQ [B, W, D] Parallel compare for equality; result is mask of 1s if true or 0s if

G, NLE [(SF=1 AND OF=1) OR (SF=0 Greater than; Not less than or equal (signed) x86 Comparison
PCMPGT [B, W, D]
false.
Parallel compare for greater than; result is mask of 1s if true or 0s if MMX
Condition
and OF=0)] AND [ZF=0] false.

GE, NL (SF=1 AND OF=1) OR (SF=0 Greater than or equal; Not less than (signed)
PACKUSWB
PACKSS [WB, DW]
Pack words into bytes with unsigned saturation.
Pack words into bytes, or doublewords into words, with signed Instruction Set
AND OF=0) Codes Conversion PUNPCKH [BW, WD,
saturation.
Parallel unpack (interleaved merge) high-order bytes, words, or
L, NGE (SF=1 AND OF=0) OR (SF=0
AND OF=1)
Less than; Not greater than or equal (signed) for DQ]
PUNPCKL [BW, WD,
doublewords from MMX register.
Parallel unpack (interleaved merge) low-order bytes, words, or

LE, NG (SF=1 AND OF=0) OR (SF=0 Less than or equal; Not greater than (signed) Conditional DQ]
PAND
doublewords from MMX register.
64-bit bitwise logical AND
PNDN 64-bit bitwise logical AND NOT

NE, NZ
AND OF=1) OR (ZF=1)
ZF=0 Not equal; Not zero (signed or unsigned)
Jump Logical
POR
PXOR
64-bit bitwise logical OR
64-bit bitwise logical XOR

NO OF=0 No overflow and PSLL [W, D, Q] Parallel logical left shift of packed words, doublewords, or
quadword by amount specified in MMX register or immediate

NS SF=0 Not sign (not negative) SETcc Shift PSRL [W, D, Q]

value.
Parallel logical right shift of packed words, doublewords, or
quadword.
NP, PO PF=0 Not parity; Parity odd
Instructions PSRA [W, D] Parallel arithmetic right shift of packed words, doublewords, or
quadword.
O OF=1 Overflow (Table can be found on page
Data Transfer MOV [D, Q] Move doubleword or quadword to/from MMX register.
442 in the textbook.)
P PF=1 Parity; Parity even State Mgt EMMS Empty MMX state (empty FP registers tag bits).
(Table can be found on page Note: If an instruction supports multiple data types [byte (B), word (W), doubleword (D), quadword
S SF=1 Sign (negative) 440 in the textbook.) (Q)], the data types are indicated in brackets.
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43 44
 +
x86 Single-Instruction, Multiple-
Data (SIMD) Instructions
 1996 Intel introduced MMX technology into its Pentium
product line
 MMX is a set of highly optimized instructions for multimedia tasks

 Video and audio data are typically composed of large arrays

of small data types

 Three new data types are defined in MMX

 Packed byte
 Packed word
 Packed doubleword

 Each data type is 64 bits in length and consists of multiple

smaller data fields, each of which holds a fixed-point integer

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45 46

Code Symbol Condition Tested Comment

ARM Operation Types 0000 EQ Z=1 Equal
0001 NE Z=0 Not equal
0010 CS/HS C=1 Carry set/unsigned higher or same
0011 CC/LO C=0 Carry clear/unsigned lower
Load and store Branch Data-processing 0100 MI N=1 Minus/negative Table 12.11
instructions instructions instructions 0101 PL N=0 Plus/positive or zero
0110 VS V=1 Overflow
0111 VC V=0 No overflow
ARM
1000 HI C = 1 AND Z = 0 Unsigned higher Conditions
1001 LS C = 0 OR Z = 1 Unsigned lower or same for
Parallel addition
Multiply Extend 1010 GE N=V Signed greater than or equal Conditional
and subtraction
instructions instructions [(N = 1 AND V = 1)
Instruction
instructions OR (N = 0 AND V = 0)
1011 LT N≠V Signed less than Execution
[(N = 1 AND V = 0)
OR (N = 0 AND V = 1)]
1100 GT (Z = 0) AND (N = V) Signed greater than
Status register 1101 LE (Z = 1) OR (N ≠ V) Signed less than or equal
access 1110 AL — Always (unconditional)
instructions 1111 — — This instruction can only be executed (Table can be found on
Page 445 in the textbook.)
unconditionally

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47 48
 + Summary Instruction Sets:
Characteristics and
Chapter 12 Functions

 Machine instruction  Intel x86 and ARM data types

characteristics
 Types of operations
 Elements of a machine
instruction  Data transfer
 Instruction representation  Arithmetic
 Instruction types  Logical
 Number of addresses  Conversion
 Instruction set design  Input/output
 Types of operands  System control
 Numbers  Transfer of control
 Characters
 Logical data  Intel x86 and ARM operation
types
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