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Lecture 6 - Merged

Chapter 12 of 'Computer Organization and Architecture' discusses instruction sets, their characteristics, and functions. It includes details on instruction cycles, operand fetching, and various types of instructions such as three-address, two-address, and one-address instructions. The chapter also presents a table illustrating the utilization of instruction addresses for non-branching instructions.

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10 views5 pages

Lecture 6 - Merged

Chapter 12 of 'Computer Organization and Architecture' discusses instruction sets, their characteristics, and functions. It includes details on instruction cycles, operand fetching, and various types of instructions such as three-address, two-address, and one-address instructions. The chapter also presents a table illustrating the utilization of instruction addresses for non-branching instructions.

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+

William Stallings
Computer Organization
and Architecture
10th Edition
© 2016 Pearson Education, Inc., Hoboken,
NJ. All rights reserved.
+ Chapter 12
Instruction Sets:
Characteristics and Functions
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Instruction Operand Operand
fetch fetch store

Multiple Multiple
operands results

Instruction Instruction Operand Operand


Data
address operation address address
Operation
calculation decoding calculation calculation

Return for string


Instruction complete, or vector data
fetch next instruction

Figure 12.1 Instruction Cycle State Diagram


© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Instruction Comment
SUB Y, A, B Y¬A–B
MPY T, D, E T¬D´E
ADD T, T, C T¬T+C
DIV Y, Y, T Y¬Y÷T

Instruction Comment
(a) Three-address instructions
LOAD D AC ¬ D
MPY E AC ¬ AC ´ E
Instruction Comment ADD C AC ¬ AC + C
MOVE Y, A Y¬A STOR Y Y ¬ AC
SUB Y, B Y¬Y–B LOAD A AC ¬ A
MOVE T, D T¬D SUB B AC ¬ AC – B
MPY T, E T¬T´E DIV Y AC ¬ AC ÷ Y
ADD T, C T¬T+C STOR Y Y ¬ AC
DIV Y, T Y¬Y÷T

(b) Two-address instructions (c) One-address instructions

A- B
Figure 12.3 Programs to Execute Y=
C+ (D´ E)
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
Table 12.1
Utilization of Instruction Addresses
(Nonbranching Instructions)

Number of Addresses Symbolic Representation Interpretation


3 OP A, B, C A ¬ B OP C
2 OP A, B A ¬ A OP B
1 OP A AC ¬ AC OP A
0 OP T ¬ (T – 1) OP T

AC = accumulator
T = top of stack
(T – 1) = second element of stack
A, B, C = memory or register locations

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

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