Introduction to System Verilog

by
Revathi Pogiri
Assistant Professor, Dept. of ECE
GMR Institute of Technology Rajam.
ASIC Flow

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Verification Process

Courtesy: Maven Silicon

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Basic Testbench Functionality
The purpose of a testbench is to determine the correctness of the design under test
(DUT). This is accomplished by the following steps.
• Generate stimulus
• Apply stimulus to the DUT
• Capture the response
• Check for correctness
• Measure progress against the overall verification goals

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Directed Testing
• Using this approach, you look at the hardware specification and write a verification
plan with a list of tests, each of which concentrated on a set of related features.

• Armed with this plan, you write stimulus vectors that exercise these features in the
DUT

• You then simulate the DUT with these vectors and manually review the resulting log
files and waveforms to make sure the design does what you expect.

• Once the test works correctly, you check it off in the verification plan and move to
the next one.

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Directed Testing

Figure shows how directed tests incrementally cover the features in the verification plan.
Each test is targeted at a very specific set of design elements. If you had enough time, you
could write all the tests needed for 100% coverage of the entire verification plan.

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Directed Testing

The figure shows the total design space and features that are covered by directed test
cases. In this space are many features, some of which have bugs. You need to write tests
that cover all the features and find the bugs.

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Methodology Basics
Following are the few test principles:
• Constrained-random stimulus: Random stimulus is crucial for exercising
complex designs. A directed test finds the bugs you expect to be in the design,
whereas a random test can find bugs you never anticipated.

• Functional coverage: When using random stimulus, you need functional

coverage to measure verification progress.

• Layered testbench using transactors: A layered testbench helps you control the
complexity by breaking the problem into manageable pieces. Transactors provide
a useful pattern for building these pieces.

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Methodology Basics
• Common testbench for all tests: With appropriate planning, you can build a
testbench infrastructure that can be shared by all tests and does not have to be
continually modified.

• Test-specific code kept separate from the testbench: code specific to a single
test must be kept separate from the testbench to prevent it from complicating the
infrastructure

• Building this style of testbench takes longer than a traditionally directed

testbench - especially the self-checking portions. As a result, there may be a
significant delay before the first test can be run. This gap can cause a manager to
panic, so make this effort part of your schedule.

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Methodology Basics

• In Figure, you can see the initial delay before the first random test runs.
• Every random test you create shares this common testbench, as opposed to directed
tests where each is written from scratch.
• single constrained-random testbench is now finding bugs faster than the many directed
ones

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Constrained-Random Stimulus
• A random test often covers a wider space than a directed one. This extra coverage
may overlap other tests or may explore new areas that you did not anticipate.

• If these new areas find a bug, you are in luck!

• If the new area is not legal, you need to write more constraints to keep random
generation from creating illegal design functionality

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Constrained-random test coverage

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Coverage convergence
• Start at the upper left with basic constrained-random tests. Run them with many
different seeds.

• When you look at the functional coverage reports, find the holes where there are gaps
in the coverage.

• Now you make minimal code changes, perhaps by using new constraints, or by
injecting errors or delays into the DUT.

• Spend most of your time in this outer loop. Writing directed tests for only a few
features that are very unlikely to be reached by random tests.

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Coverage convergence

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Things to Randomize
• Device configuration
• Environment configuration
• Input data
• Errors and violations
• Delays

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Feedback from Functional Coverage
to Stimulus

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Testbench components
• In the simulation, the testbench wraps around the DUT, just as a hardware tester
connects to a physical chip.

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Testbench components
• It is comprised of many bus functional models (I3FM), which you can think of as
testbench components - to the DUT they look like real components.
• If the real device connects to AMI3A. USB. PCI. and SPI buses, you have to build
equivalent components in your testbench that can generate stimulus and check the
response as shown in Figure.

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Layered Testbench
• A key concept for any modern verification methodology is the layered testbench.

• Although this process may seem to make the test bench more complex, it actually
helps to make your task easier by dividing the code into smaller pieces that can be
developed separately.

• Layered test bench is composed with

1. The Signal and Command Layers
2. The Functional Layer
3. The Scenario Layer

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The Signal and Command Layers

• At the bottom is the signal layer that contains the DUT and the signals that connect
it to the testbench
• The DUT's inputs are driven by the driver that runs single commands, such as bus
read or write.
• The DUT's output drives the monitor that takes signal transitions.

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The Functional Layer

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The Functional Layer
• Functional layer feeds down into the command layer.
• The agent block (called the transactor in the VMM) receives higher-level
transactions such as DMA read or write and breaks them into individual
commands.
• These commands are also sent to the scoreboard that predicts the results of the
transaction. The checker compares the commands from the monitor with those in
the scoreboard.
• For example, write and read values from an RW register should match. When the
write operation is performed to the design, the scoreboard receives this packet.
After the same register is read back from the design, the read values are also sent to
the scoreboard. The scoreboard compares these two values and verifies the
matching.

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The Scenario Layer

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The Scenario Layer
• The functional layer is driven by the generator in the scenario layer.

• For example, a device is an MP3 player that can concurrently play music from its
storage, download new music from a host, and respond to input from the user, such
as adjusting the volume and track controls. Each of these operations is a scenario.

• The scenario layer of your testbench arranges all these steps with constrained-
random stimulus.

• The blocks in the testbench environment are developed at the beginning of

development. During the project, they may evolve and you may add functionality,
but these blocks should not change for individual tests.

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The Test Layer and Functional Coverage

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The Test Layer and Functional Coverage
• The test layer is at the top of the testbench.
• Design bugs that occur between OUT blocks are harder to find as they involve
multiple people reading and interpreting multiple specifications…
• This top-level test is the conductor: he does not play any musical instrument, but
instead guides the efforts of others. The test contains the constraints to create the
stimulus.

• Functional coverage measures the progress of all tests in fulfilling the verification
plan requirements.

• Do you need all these layers in your testbench? The answer depends on what your
DUT looks like. A complicated design requires a sophisticated testbench.

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The Test Layer and Functional Coverage
• For a simple design, the scenario layer may be so simple that you can merge it with the
agent.
• When estimating the effort to test a design, don't count the number of gates: count
the number of designers.
• Every time you add another person to the team, you increase the chance of
different interpretations of the specifications.

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Simulation Environment Phases
Build phase
• Generate configuration: Randomize the configuration of the DUT and the surrounding
environment.
• Build environment: Allocate and connect the testbench components based on the
configuration. For example, if the configuration chose three bus drivers, the testbench
would allocate and initialize them in this step.
• Reset the DUT
• Configure the DUT: Based on the generated configuration from the first step, load the
OUT command registers.

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Simulation Environment Phases
Run phase
• Start environment: Run the testbench components such as BFMs (Bus Functional
Model) and stimulus Generators
• Run the test: Start the test and then wait for it to complete. It is easy to tell when a
directed test has completed, but doing so can be complex for a random test.
• Starting from the top, wait for a layer to drain all the inputs from the previous layer
(if any), wait for the current layer to become idle, and then wait for the next lower
layer.
• You should also use time-out checkers to ensure that the OUT or testbench does not
lock up.

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Simulation Environment Phases
Wrap-up phase
• Sweep: After the lowest layer completes, you need to wait for the final transactions to
drain out of the DUT.
• Report:

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Introduction to Data Types
• System Verilog adds many new data types to help both hardware designers and
verification engineers.

• System Verilog introduces new data types with the following benefits:
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays: reduced memory usage, built-in
support for searching and sorting
• Classes and structures: support for abstract data structures
• Unions and packed structures: allow multiple views of the same
• data Strings: built-in string support
• Enumerated types: code is easier to write and understand

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Built-In Data Types: Verilog

• Verilog-1995 has two basic data types: variables and nets, both of which
hold 4-state values: 0, I, Z, and X.
• RTL code uses variables to store combinational and sequential values.
• Variables can be unsigned single or multi-bit (reg [7: 0] m), signed 32-bit
variables (integer), unsigned 64-bit variables (time), and floating-point
numbers (real).
• Variables can be grouped together into arrays that have a fixed size.
• All storage is static, meaning that all variables are alive for the entire
simulation and routines cannot use a stack to hold arguments and local
values.

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Built-In Data Types: Verilog

• A net is used to connect parts of a design such as gate-primitives and

module instances
• Nets come in many flavours but most designers use scalar and vector wires
to connect together the ports of design blocks.

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System Verilog Data Types

➢ System Verilog is an extension to Verilog and is also used as an HDL.

➢ Verilog has reg and wire data-types to describe hardware behavior.

➢ Since verification of hardware can become more complex and

demanding, datatypes in Verilog are not sufficient to develop efficient

testbenches and testcases.

➢ Hence System Verilog has extended Verilog by adding more C like data-

types for better encapsulation and compactness.

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Built-In Data Types: System Verilog

• System Verilog adds many new data types to help both hardware
designers and verification engineers:

• 4-State Data Types (Eg: The logic type)

• 2-State Data Types

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4 - state Data Types

➢ Types that can have unknown (X) and high-impedance (Z) value in

addition to zero (0) and one (1) are called 4-state types.

➢ reg can only be driven in procedural blocks like always and initial while

wire data types can only be driven in assign statements.

➢ System Verilog introduces a new 4-state data type called logic that can be

driven in both procedural blocks and continuous assign statements.

➢ But, a signal with more than one driver needs to be declared a net- type

such as wire so that System Verilog can resolve the final value.

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Built-In Data Types: The Logic Type

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Built-In Data Types: The Logic Type
• You can use the logic type to find netlist bugs as this type can only have a
single driver.

• Rather than trying to choose between reg and wire, declare all your signals
as logic, and you'll get a compilation error if it has multiple drivers.

• A logic signal can be used anywhere a net is used, except that a logic
variable cannot be driven by multiple structural drivers, such as when you
are modelling a bidirectional bus.

• Any signal that you do want to have multiple drivers, such as a

bidirectional bus, should be declared with a net type such as a wire.

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2 - state Data Types

➢ In a typical verification testbench, there are many cases where we don’t

really need all the four values (0, 1, x, z) like for example when modeling a

network packet with a header that specifies the length of the packet.

➢ Length is usually a number, but not X and Z.

➢ System Verilog adds many new 2-state data types that can only store and

have a value of either 0 or 1. T

➢ his will aid in faster simulation, take less memory and are preferred in

some design styles

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2 - state Data Types

➢ The most important 2-state data type is bit which is used most often in

testbenches.

➢ A variable of type bit either 0 or 1 which represents a single bit.

➢ A range from MSB to LSB should be provided to make it represent and

store multiple bits

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Built-In Data Types: 2-State Data Types

• System Verilog introduces several 2-state data types to improve simulator

performance and reduce memory usage, compared with variables declared
as 4-state types.

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Built-In Data Types: 2-State Data Types

• You might be tempted to use types such as byte to replace more verbose
declarations such as logic [7: 0 ]

• Hardware designers should be careful as these new types are signed

variables. and so a byte variable can only count up to 127, not the 255 you
may expect. It has the range -128 to +127

• You could use byte unsigned. but that is more verbose than just bit [7: 0 ].

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Built-In Data Types: 2-State Data Types

• Use the $isunknown() operator that returns 1 if any bit of the expression
is X or Z.

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Arrays

➢ An array is a collection of variables, all of the same type, and accessed

using the same name plus one or more indices.
➢ In System Verilog vector width/dimensions declared before the object
name is referred to as packed array and array size/dimensions declared
after the object name is referred to as an unpacked array

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Arrays
Single dimensional array

Multidimensional array
Multidimensional arrays are also known as an array of arrays.
int arr[2][3];

This array has total 2*3 = 6 elements.

TWO-DIMENSIONAL ARRAY DECLARATION

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Arrays
The data in a two-dimensional array is stored in a tabular form as shown in the
below diagram.

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Packed and Unpacked array in SystemVerilog

•The term packed array is used to refer to the dimensions declared before the data

identifier name

•The term unpacked array is used to refer to the dimensions declared after the data

identifier name

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Packed array

➢ Packed arrays can be of single bit data types (reg, logic, bit), enumerated types, and

recursively packed arrays and packed structures

➢ One dimensional packed array is referred to as a vector

➢ Vector: A vector is a multi-bit data object of reg/logic/bit declared by specifying a

range

➢ Scalar: Scalar is 1-bit data object of reg/logic/bit declared without specifying a range

➢ A packed array is a mechanism for subdividing a vector into sub-fields, which can be

conveniently accessed as array elements.

➢ A packed array is guaranteed to be represented as a contiguous set of bits

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Packed array

Packed Arrays:
•In packed arrays, the bits are stored consecutively in memory without any gaps or
padding.
•The bit order is determined by the range specified in the declaration.
Example:
bit [7:0] packed_array;
stored as follows:

7 6 5 4 3 2 1 0
1 0 1 0 1 0 1 0

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Packed array

Packed Arrays:
•In packed arrays, the bits are stored
consecutively in memory without any gaps or
padding.
•The bit order is determined by the range
specified in the declaration.
Example:

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UnPacked array

➢ Unpacked arrays can be of any data type.

➢ Unpacked arrays shall be declared by specifying the element ranges after the identifier
name.
➢ An unpacked array may or may not be so represented as a contiguous set of bits.
➢ In unpacked arrays, the bits are stored according to the order of elements declared in
the array.
➢ There may be gaps or padding between elements, depending on the data type and
structure of the array.

bit unpacked_array[7:0];

0 1 2 3 4 5 6 7
1 0 1 0 1 0 1 0

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UnPacked array

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Arrays

➢ Packed arrays store bits consecutively in memory based on the specified range, while

unpacked arrays store bits based on the order of the array elements.

➢ The choice between packed and unpacked arrays depends on the design requirements

and the desired organization of data.

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Fixed-size arrays

➢ In fixed size array, array size will be constant throughout the simulation, Once
the array is declared no need to create it.
➢ By default, the array will be initialized with value ‘0’.

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Fixed-size arrays

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Fixed-size arrays

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Fixed-size arrays

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Fixed-size arrays

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Fixed-size arrays

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Fixed-size arrays

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Fixed-size arrays

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Fixed-size arrays

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Fixed-size arrays

Note:

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Fixed-size arrays

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Dynamic arrays

➢ A dynamic array is an unpacked array whose size can be set or changed at run time,

and hence is quite different from a static array where the size is pre-determined

during declaration of the array.

➢ The default size of a dynamic array is zero until it is set by the new () constructor.

➢ A dynamic array dimensions are specified by the empty square brackets [ ].

Syntax:

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Dynamic arrays

Resize the dynamic array

//Change the length of the array after declaration/initialization

d_array1 = new[10]; //dynamic array of 10 elements

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Dynamic arrays
//Allocate 6 new elements and retain values of 4 elements.
d_array1 = new[10](d_array1);

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Dynamic arrays
➢ How to add new items to a dynamic array ?
➢ Many times we may need to add new elements to an existing dynamic array without losing its
original contents.
➢ Since the new() operator is used to allocate a particular size for the array, we also have to copy the
old array contents into the new one after creation.

Delete the dynamic array

//delete array
d_array1.delete;
array_name.delete() method will delete the array

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Dynamic arrays

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Dynamic Arrays

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Queue

➢ A queue is a variable-size, ordered collection of homogeneous elements.

➢ like a dynamic array, queues can grow and shrink

➢ queue supports adding and removing elements anywhere

➢ Queues are declared using the same syntax as unpacked arrays, but specifying $ as

the array size. In queue 0 represents the first, and $ representing the last entries.

➢ queue can be bounded or unbounded.

➢ bounded queue – queue with the number of entries limited or queue size specified

➢ unbounded queue – queue with unlimited entries or queue size not specified

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Queue
Queue Declaration
data_type queue_name[$];
where:
data_type – data type of the queue elements.
queue_name – name of the queue.

Queue Declaration Example

Queue Initialization

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Queue

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Queue

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Queue

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Queue operations

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Queue operations

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Associative Arrays

➢ Associative array Stores entries in a sparse matrix.

➢ Associative arrays allocate the storage only when it is used, unless like in the dynamic
array we need to allocate memory before using it.
➢ In associative array index expression is not restricted to integral expressions but can be
of any type.
➢ An associative array implements a lookup table of the elements of its declared type. The
data type to be used as an index serves as the lookup key and imposes an ordering.
➢ When the size of the collection is unknown or the data space is sparse, an associative
array is a better option.

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Associative Arrays

Array Declaration
data_type array_name [ index_type ];

where:
data_type – data type of the array elements.
array_name – name of the associative array.
index_type – data-type to be used as an index, or *.
* indicates the array is indexed by any integral expression of arbitrary size.

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Associative Arrays

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Associative Arrays

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Associative Arrays

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Associative Arrays

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Associative Arrays

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Associative Arrays

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Array manipulation methods

➢ There are many built-in methods in System Verilog to help in array searching and

ordering.

➢ Array manipulation methods simply iterate through the array elements and each

element is used to evaluate the expression specified by the with clause.

➢ The iterator argument specifies a local variable that can be used within the with

expression to refer to the current element in the iteration.

➢ If an argument is not provided, item is the name used by default.

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Array manipulation methods
➢ The with clause and expresison is mandatory for some of these methods and for some
others its optional.
➢ Mandatory 'with' clause:
➢ These methods are used to filter out certain elements from an existing array based on a
given expression.
➢ All such elements that satisfy the given expression is put into an array and returned.
Hence the with clause is mandatory for the following methods.

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Array manipulation methods

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Array manipulation methods

Optional 'with' clause

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Array manipulation methods

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Array ordering methods

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Array ordering methods

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Array Reduction methods

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Array Reduction methods

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Array manipulation methods

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Array manipulation methods

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Array manipulation methods

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Creating New Types with typedef

➢ In complex testbenches some variable declarations might have a longer data-type

specification or require to be used in multiple places in the testbench.

➢ In such cases we can use a typedef to give a user-defined name to an existing data type.

➢ The new data-type can then be used throughout the code and hence avoids the need to

edit in multiple places if required.

Syntax:

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Creating New Types with typedef

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Creating New Types with typedef

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Alias
➢ In System Verilog, an alias is a named reference to a variable, signal, or instance.
➢ It provides a way to refer to a variable using a different name.
➢ Aliases can be useful in many situations, including reducing code complexity, enhancing
readability, and improving simulation performance.
➢ It is also used to model a bi-directional short-circuit and can be used inside modules,
interfaces and generate blocks.
➢ Here's an example of how to create an alias in System Verilog:

➢ In this example, the signal data is assigned the value 8'hFF using the alias mydata.
➢ The advantage of using an alias is that it allows you to refer to the same signal using
different names, which can make the code more readable and easier to understand.

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Creating New Types with typedef

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Creating New Types with typedef

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Creating User-Defined Structures

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Creating User-Defined Structures

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Creating User-Defined Structures

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Creating User-Defined Structures

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Creating User-Defined Structures

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Creating User-Defined Structures

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Enumurated types

➢ An enumerated type defines a set of named values.

➢ In the following example, light_* is an enumerated variable that can store one of the
three possible values (0, 1, 2).
➢ By default, the first name in the enumerated list gets the value 0 and the following
names get incremental values like 1 and 2.

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Enumurated types

➢ The user can assign any integer value for any of the enumerated names.
➢ If any name does not have an assigned value, then it automatically takes the
incremented value of the previous name.

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Enumurated types

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Enumurated types
Why do we need enumeration?
To make the code more simple and readable.
Consider the following example without enumeration.

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Enumurated types
The following code is more readable because of the enumerated names RED, YELLOW and
GREEN.

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Enumurated types

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Enumurated types

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Enumurated types

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Strings
➢ What is a System Verilog string?
➢ The string data-type is an ordered collection of characters.
➢ The length of a string variable is the number of characters in the collection which can
have dynamic length and vary during the course of a simulation.
➢ A string variable does not represent a string in the same way as a string literal. No
truncation occurs when using the string variable.
➢ Syntax:
➢ string variable_name [= initial_value];
➢ variable_name is a valid identifier and the optional initial_value can be a string literal,
the value "" for an empty string, or a string data type expression.
➢ If an initial value is not specified at the time of declaration, then the variable defaults
to an empty string literal.

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Strings

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Strings

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Strings

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String conversion methods

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