6/18/25, 10:26 AM #No.1 Design Verification Course in Hyderabad | Start Your High-Paying Career Now!

Course Curriculum Download 2025 Curriculum

Introduction

Semiconductor ecosystem
VLSI design cycle - front end design flow & backend design flow
What is ASIC & FPGA
FPGA design flow & ASIC design and verification flow
SoC example and industry updates
Opportunities for VLSI engineers in India
VLSI industry work profiles and roles
How to be industry ready?

Digital Design

Digital system design & applications

Introduction
What is digital & analog
Introduction to digital system design
Elements of digital logic, number system
Code conversion, logic gates, K-maps, Boolean algebra, SOP, POS
BCD, excess-3, gray code, ASCII, complements
Combinational logic design: adders, subtractors, multipliers, dividers, comparators, multiplexing,
demultiplexing, encoders, decoders, parity, checkers, data path, control path, ALU
Sequential logic design: synchronous logic design, asynchronous logic design
Latches
Flip-flops
Counters (asynchronous, synchronous, mod, Johnson, ring)
Registers (SISO, SIPO, PISO, PIPO, USR, LFSR)
FSM (Mealy and Moore – overlapping and non-overlapping)
FIFO (asynchronous, synchronous)
Memories (RAM, ROM)

Verilog

https://vlsifirst.com/course/vlsi-rtl-design-and-verification/hyderabad 1/6
6/18/25, 10:26 AM #No.1 Design Verification Course in Hyderabad | Start Your High-Paying Career Now!

Introduction & Importance of HDL - HDL vs High Level Languages.

Basic Language elements
Design Methodologies - Top Down, Bottom Up
Verilog data types
Verilog Modelling Styles:
Dataflow Modelling – continuous assignment statements
Gate Level Modelling/Structural modelling
Behavioural Modelling – Procedural blocks, procedural block statements – blocking and non-blocking
assignments.
Switch Level Modelling – switch primitives
System Tasks
Logic Gates, Half Adder, Full Adder, Half subtractor, Full subtractor.
Multiplexer – 2:1, 4:1, 8:1 and other mux-oriented problems.
Logic gates using Mux, Encoder, Decoder, Priority Encoder
Stratified Event Queue or Timing Regions In-depth explanation with examples.
Comparator, Seven Segment, Multipliers
Combinational Circuits to be taught in Behavioral (IF, CASE) and Gate level
Adders – RCA, Carry Look ahead adder, ALU, Subtractor, Division Circuits
Sequential Circuits:
Latch – Definition, usage, types, Coding and Simulation Result Explanation.
Flipflop – Types (dff, tff, jkff), Coding and Simulation Result Explanation, Sync and Async FF. Difference
between Latch and Flipflop, Why Nonblocking should be used for Sequential Circuits?
Counter - Both Synchronous and Asynchronous, Mod Counters, Repeated Counters, Ring, Johnson
Counters.
FSM – Melay and Moore, Timescale, Parameter, Local Param, ifdef
Shift registers – SISO,PISO,PIPO,PISO, Bi-directional Registers, Universal Shift Registers
MEMORIES – RAM, ROM, Frequency Dividers, Self-checking testbenches.
Define, setup, hold time, Types of delays to be used in coding. – Inter,Intra,Gate
Sequential and Parallel execution blocks, generate blocks, Primitives - Try
Randomization based testbenches, Task oriented TB.
Synthesizable vs Non-Synthesizable Constructs explanation with examples, Loops.
Race conditions in Verilog with Live examples

System Verilog

ASIC Verification:
Introduction & Importance

https://vlsifirst.com/course/vlsi-rtl-design-and-verification/hyderabad 2/6
6/18/25, 10:26 AM #No.1 Design Verification Course in Hyderabad | Start Your High-Paying Career Now!

Verification Methodologies
System Verilog: Introduction to Verification and System Verilog.
Data Types:
Integer, Void
String, Event
User-defined Enumerations
Class Arrays
Fixed Size Arrays - Packed and Un-Packed
Dynamic Array - Associative Array, Queues, structure, Union, typedef
Procedural Statements and Flow Control:
always_ff, always_comb, Blocking & Non-Blocking assignments
Unique-I, Priority-If
While, do-while, for each & enhanced for loop
Repeat, Forever
Break & Continue
Named Blocks and Statement Labels
Disable block and disable statements
Event Control.
Tasks and Functions:
Tasks
Functions
Argument passing – Automatic, Static
Processes:
fork-join
fork-join any
fork-join none
wait-fork
disable-fork
Classes:
Classes
This Keyword
Constructors
Static Class Properties & Methods
Class Assignment
Shallow Copy & Deep Copy
Parameterized Classes
Inheritance
Overriding Class Members
Super Keyword

https://vlsifirst.com/course/vlsi-rtl-design-and-verification/hyderabad 3/6
6/18/25, 10:26 AM #No.1 Design Verification Course in Hyderabad | Start Your High-Paying Career Now!

Polymorphism, Casting
Data Hiding and Encapsulation
Abstract Classes & Virtual Methods
Class Scope Resolution Operator
Extern methods
Type def Classes.
Randomization & Constraints:
Constraint Blocks
External Constraint Blocks
Inheritance
Inside operator
Weighted distribution
Implication and if-else and other constructs.
IPCSemaphore - Mailbox - Event:
Scheduling Semantics
Program Block
Interface
Mod port
Clocking Blocks.
Assertion:
Assertions
SVA Building Blocks
SVA Sequence
Implication Operator
Repetition Operator
SVA Built in Methods
Ended and Disable iff.
Coverage:
Coverage
Functional Coverage – Types
Coverage Options - Parameters and define.
Project on System Verilog on Industry Standard Protocol with assertions and coverage along with tool
explanation.

Universal Verification Methodology

INTRODUCTION

https://vlsifirst.com/course/vlsi-rtl-design-and-verification/hyderabad 4/6
6/18/25, 10:26 AM #No.1 Design Verification Course in Hyderabad | Start Your High-Paying Career Now!

What is UVM?
Why UVM?
Overview of UVM Structure.

UVM Testbench Architecture

Test Bench Structure

Explanation of Test Bench
UVM Objects and UVM Components
UVM Sequence Item
UVM Sequence and UVM Sequencer
UVM Driver and UVM Monitor
UVM Agent and UVM Scoreboard
UVM Test and UVM Top.

UVM Phases

Types of Phases
Explanation of Phases

UVM TLM

Analysis Port
Usage of TLM Ports
Declaration and Connection of Ports

Register Layer

Introduction
Register Model
Register Environment
Connection of Register Environment

UVM Reporting

Reporting Methods
Configurations
Usecases

UVM Configurations

Usage of Configurations
Set Config Methods

UVM Factory

https://vlsifirst.com/course/vlsi-rtl-design-and-verification/hyderabad 5/6
6/18/25, 10:26 AM #No.1 Design Verification Course in Hyderabad | Start Your High-Paying Career Now!

Registration
Factory Methods Explanation
UVM Callback

Body Call back

Usage and Importance of Call Backs
Lock Grab

Examples
Arbitration
Importance of Arbitration
Usage of Arbitration
Sequencer Arbitration
Virtual Sequence, Sequencer
Need and Usage of Virtual Sequence and Sequencer.

Sequential and Parallel Sequence, Layered Sequences

Overview and Implementation of Sequences.

UVM MACROS

Macros Explanation in UVM.

UVM Project

UVC Development for Industry standard protocol.

Explanation of IP, VIP, SOC Level Testbench flow, Testplans, Verification plan.

Projects

Students will work on some of the below Design and Verification projects as part of training project. APB, AHB, AXI, SPI ,
UART, I2C, MEMORY CONTTROLLER, USB, UTMI, PCIE, ETHERNET, AES. Linux Operation System, Vim Editor.

https://vlsifirst.com/course/vlsi-rtl-design-and-verification/hyderabad 6/6