GATE SOLUTIONS

ELECTRONICS & COMMUNICATION

ENGINEERING

1987-2020

Office: F-126, (Lower Basement), Katwaria Sarai, New Delhi-110 016

Phone: 011-26522064  Mobile: 81309 09220, 97118 53908
Email: [email protected], [email protected]
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IES MASTER PUBLICATION
F-126, (Lower Basement), Katwaria Sarai, New Delhi-110016
Phone : 011-26522064, Mobile : 8130909220, 9711853908
E-mail : [email protected]
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Copyright © 2020, by IES MASTER Publication. No part of this booklet may be
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First Edition : 2016

Second Edition : 2017

Third Edition : 2018

Fourth Edition : 2019

Fifth Edition : 2020

Typeset at : IES Master Publication, New Delhi-110016

 PREFACE

The Graduate Aptitude Test in Engineering (GATE) is an All-India examination administered and conducted
in eight zones across the country by the GATE Committee comprising of Faculty members from IISc,
Bangalore and other seven IITs on behalf of the National Coordinating Board, Department of Education,
Ministry of Human Resources Development.
The GATE score/rank is used for admissions to Post Graduate Programmes (ME, M.Tech, MS, direct PhD)
in institutes like IIT and IISc, etc. with financial assistance offered by the Ministry of Human Resource
Development. PSUs too use the GATE scores for recruiting candidates for various prestigious jobs with
attractive remuneration.
The door to GATE exam is through previous year question papers. If you are able to solve question
papers in access of 10 years, you are sure to clear the GATE exam, and open new vistas of career and
learning.
The Electronics & Communication Engineering GATE 2021 book from IES Master offers detailed topic-
wise solutions for the past 34 years question papers. The emphasis is clearly on the understanding of
concepts and building upon a holistic picture. So as you finish a topic, for instance, Basics of Network
Analysis, you will find all the previous years’ question papers with detailed explanation under that
particular topic.
The approach has been to provide explanation in such a way that just by going through the solutions,
students will be able to understand the basic concepts and will apply these concepts in solving other
questions that might be asked in future exams.
Every care has been taken to bring an error-free book. However, comments, suggestions, and feedback
for improvement in the future editions are most welcome.

IES Master Publication

New Delhi
 CONTENT

1. Network Theory ..................................................................................................... 1 – 117

2. Signal and Systems ........................................................................................... 118 – 215

3. Electronic Devices ............................................................................................ 216 – 292

4. Analog Electronics ............................................................................................. 293 – 421

5. Digital Circuits ................................................................................................... 422 – 521

6. Microprocessor.................................................................................................. 522 – 545

7. Control Systems ................................................................................................ 546 – 662

8. Communications ............................................................................................... 663 – 791

9. Electromagnetics .............................................................................................. 792 – 916

10. Mathematics ...................................................................................................... 917 – 978

11. General Aptitude .............................................................................................. 979 – 1018

 UNIT-1 NETWORK THEORY

SYLLABUS

Network solution methods : nodal and mesh analysis; Network theorem; superposition, Thevenin and
Norton’s, maximum power transfer; Wye-Delta transformation; Steady state sinusoidal analysis using
phasors; Time domain analysis of simple linear circuits; solution of network equations using Laplace
transform; Frequency domain analysis of RLC circuits; Linear 2-port network parameters: driving point
and transfer functions; State equations for network

CONTENTS

1. Basics of Network Analysis ..................................................... 02–22

2. DC Transients and Steady State Response ............................ 23–64

3. Resonance ............................................................................... 65–72

4. Network Theorems .................................................................. 73–91

5. Two Port Networks ................................................................ 92–109

6. Network Functions and Network Synthesis ....................... 110–114

7. Network Graphs .................................................................. 115–117

 Electronics & Communication Engineering
2 GATE SOLVED PAPER 1987-2020

1 BASICS OF NETWORK ANALYSIS

charge the 0.1 F capacitor from 0V to 3V is

1– Mark
SW
+3V 120 B A
1. A connection is made consisting of resistance A
in series with a parallel combination of t=0
resistances B and C. Three resistors of the value
0.1F
10  , 5  , 2  are provided. Consider all
possible permutations of the given resistors into
the positions A, B, C, and identify the (a) 0.3 (b) 0.45
configurations with maximum possible overall (c) 0.9 (d) 3
resistance, and also the ones with minimum [GATE-2015]
possible overall resistance. The ratio of maximum
to minimum value of the resistances (upto second 5. In the circuit shown, the average value of the
decimal place) is __________ voltage Vab (in Volts) in steady state condition is
_____
[GATE-2017]
1k 1F 1mH 2k
b a
2. In the network shown in the figure, all resistors
+ Vab +
are identical with R  300  . The resistance – – 5V
5sin(5000t )
Rab (in  ) of the network is _____.
a [GATE-2015]
R R R R R
R
R R R 6. At very high frequencies, the peak output
R=300
voltage V0(in Volts) is _____
R R
Rab R R R R 100 F

b +
[GATE-2015] 1k 1k V0
100 F
3. In the given circuit, the values of V1 and V2 1.0sin(t)V
+ –
–
respectively are
4 1k 1k

I 100 F
+ 2I +
V2 5A 4 4 V1 [GATE-2015]
– –

7. In the circuit shown, the voltage Vx (in Volts)

(a) 5V, 25V (b) 10V, 30V is _____
(c) 15V, 35V (d) 0V, 20V 0.5V X
[GATE-2015]
10
4. In the circuit shown, the switch SW is thrown +
A VX 20 8 0.25VX
from position A to position B at time t = 0. The –
energy  in J  taken from the 3V source to [GATE-2015]
Electronics & Communication Engineering
NETWORK THEORY 9
(a) –105 V (b) +105 V (a) 0 A (b) 4 A
(c) – 15 V (d) + 15 V (c) 1 A (d) None of the above
[GATE-1993] [GATE-1997]

3– Marks 5– Marks
1. In the circuit shown, the current iD through 1. Find the input resistance Rin of the infinite
the ideal diode (zero cut in voltage and zero section resistive network shown in figure.
forward resistance) equals 1 1 1 1 1
iD
4 
Rin  1 1 1 1

+
– 10 V 4 1 2A
[GATE-1996]

ANSWER KEY

1 Mark 17. (d) 3. (1) 20. (b)

1. (2.14) 18. (a) 4. (d) 21. (a)

2. (100) 19. (c) 5. (5) 22. (None of these)

3. (a) 20. (a) 6. (–1A) 23. (d)

4. (c) 21. (d) 7. (1.5) 24. (d)

5. (5) 22. (a) 8. (20) 25. (d)

6. (0.5) 23. (b) 9. (29.09) 26. (d)

7. (8) 24. (c) 10. (2.504) 27. (b)

8. (2.8) 25. (b) 11. (10) 28. (b)

9. (a) 26. (a) 12. (0.4083) 29. (d)

10. (0.5) 27. (d) 13. (2.618) 30. (a)

11. (c) 28. (a) 14. (c) 3 Marks

12. (b) 29. (d) 15. (d) 1. (c)

13. (b) 30. (a & d) 16. (c)

14. (a) 2 Marks 17. (a)

15. (c) 1. (8.00) 18. (a)

16. (a) 2. (a) 19. (c)

IES MASTER Publication

 Electronics & Communication Engineering
10 GATE SOLVED PAPER 1987-2020

EXPLANATIONS

1– Mark R
= R R R = 100
3
Sol–1: (2.14)
Sol–3: (a)
4 x
A + I +
(1)
V2 5A 4 4 2I V1

B C – –

Applying nodal analysis at node (1), we get

x x
5 =   2I
Resistor are 2, 5 and 10 4 4
2x x
For maximum resistance B = 2, C = 5, A = 10  5 =
4
 2
4
x  4I
80  x = 5
Rmax =
7 Now,V1 = 5V  x  V1 
for minimum resistance,
V1  5  4  V2 = 0
A = 2, B = 5, C = 10
[KVL in the outermost loop]
16  V2 = 5 + 5 × 4 = 25 V
Rmin =
3
Rmax (80 / 7) Sol–4: (c)
=
Rmin (16 / 3) Initially capacitor is uncharged. For t > 0,
= 2.14 the circuit will be :
120 
Sol–2: (100) 3V
i(t) R

R RR R R R C 0.1 F
R eq R R R
R R
R R R R
Current in RC circuit while charging is given
(R=300 ) by :
V0  t/RC
R R/2 R/2 R i(t) = e where V0 = 3V
R R R R
R eq p r s
q Power delivered by the source = P
R R/2 R/2 R = 3i(t) [ P = V.I]
t t

Also, Energy =  Pdt   3i  t  dt

0 0

R eq 2R R R 2R Capacitor gets fully charged at steady state

i.e t   .

V0
[Here, branch ‘pqrs’ is removed as no current  E =  3. R e
0
 t/RC dt
flows through it, because it forms a balanced
bridge] 3V0

 1 e  t/RC 
=  0
 Req =  2R    2R   R  R R 1 RC  