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DOI: 10.35940/ijeat.A1083.1291S319

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 International Journal of Engineering and Advanced Technology (IJEAT)
ISSN: 2249 – 8958, Volume-9 Issue-1S3, December 2019

Low Power Implementation Of Ternary Content

Addressable Memory (TCAM)
Prithwiraj Das, Ria Pathak, P. Augusta Sophy Beulet

 information search words comprising altogether 1s and 0s. In

Abstract: In network routers, Ternary Content Addressable any case, in ternary CAM a third coordinating state "X" or
Memory (TCAM)[1] based search engines take an important role. "couldn't care less" put away at least one bit in the
One of the improved versions of Content Addressable Memory information word as shown in Fig. 1. This additional bits
(CAM) is TCAM. For high speed and broader searching operation
comes at an extra cost over the paired CAM as the inside
TCAM is used. Unlike normal CAM, TCAM has 3 logic states: 0,
1, ‘X’. In TCAM within one single clock cycle, search operation memory cell should now encode three potential states rather
can be performed. That is why it is called special type of memory. than the two of binary CAM. By a mask bit, this additional
Also, quick search ability is one of the popular features of TCAM. state is implemented to every memory cell.
To compare the search and stored data, TCAM array acts parallel
in every location. But high power dissipation is the main In various fields we can find the application of TCAM.
disadvantage of TCAM. To overcome this power dissipation in this Network routers are the main application of TCAM. In the
paper we proposed a low power TCAM implementation by using network switches each address has 2 sections. One is system
Reversible logic.[2] Reversible logic has less heat dissipating prefix, which can change in size contingent upon the subnet
characteristics property with respect to irreversible gate. Also, setup and the host address which involves the rest of the bits.
Reversible logic has ultra-low power characteristics feature. In
recent past it has been proved that reversible gates can implement Each subnet has organized musk. This system musk indicates
any Boolean function. which bits of the location are system prefix and which bits is
the host address. Steering is finished by the counseling of a
Keywords: TCAM, CAM, Reversible Logic, Fredkin Gate, directing table which is kept up by the switch. This switch
Feynman Gate, Peres Gate, Taffoli Gate contains each realized system prefix, the related system
cover, and the data expected to course bundles to that goal.
I. INTRODUCTION Ternary CAM makes the lookup process very efficient for the
routing table. By using “don‟t care” the addresses are stored
In today‟s life, we need high-performance memory for for the host part of the address.
TCAM RAM
network system. CAM is one such type of high performance
1 0 1 X X 0 0 PORT A
memory. Functionality of TCAM is different from Random
Access Memory (RAM). RAM is used to store information 0 1 1 0 X
0 1 PORT B
that it needed very often while the computer is running. But 1
0 1 X X 1 0 PORT C
the drawback is it cannot store any data permanently. CAM is
a hardware search engine. It is much faster than any 1 0 0 1 1 1 1 PORT D
algorithmic operation for search intensive application. CAM
is basically constructed of SRAM with an additional
comparison circuitry. This kind of circuitry can complete 0 1 1 0 1 PORT B
search operation in one clock cycle. CAM mainly uses two
search intensive techniques namely, packet forwarding and Fig. 1. Basic operation of TCAM Cell
packet classification to improve the speed. One of the
improved versions of Content Addressable Memory is Intrusion detection, pattern searching in genes, image
Ternary Content Addressable Memory (TCAM). Based on processing, data compression, artificial intelligence, radar
contents, Ternary Addressable Memory (TCAM) elects a applications, signal tracking, pattern matching in virus
word among stored ternary data. In one clock cycle TCAM detection [4] are the other applications of TCAM.
compares the search key with the entire stored words in
parallel and gives the address of the matched output with II. REVERSIBLE LOGIC
matching word. 0, 1, “X”[3] (don‟t care state) are 3 states of a
TCAM. TCAM architecture is more complex than the Everyday new faster, smaller and complex technology is
conventional CAM architecture. Binary CAM utilizes developing. For achieving higher speed the clock frequency
is increased. Increase in number of transistors into a chip
Revised Manuscript Received on December 16, 2019. makes that chip architecture more complex and the power
* Correspondence Author consumption also increases. Mostly, the gates used to
Prithwiraj Das, School of Electronics Engineering, Vellore Institute of perform logical operations are irreversible. It means every
Technology, Chennai, India. Email: [email protected]
Ria Pathak, School of Electronics Engineering, Vellore Institute of time when some information
Technology, Chennai, India. Email: [email protected] about the input is deleted or
Augusta Sophy Beulet.P *, School of Electronics Engineering, Vellore lost and that lost information is
Institute of Technology, Chennai, India. Email: [email protected]

Retrieval Number: A10831291S319/2019@BEIESP Published By:

DOI:10.35940/ijeat.A1083.1291S319 Blue Eyes Intelligence Engineering
455 & Sciences Publication
 Low Power Implementation Of Ternary Content Addressable Memory (TCAM)

dissipated as heat. In digital design one of the important 3*3 Fredkin gate structure is explained in Fig. 2. Here the
performance parameter is energy loss. Over the last decades input vectors are A, B, C and the output vectors are A, ~AC
this heat loss is reduced dramatically by higher level of XOR AB, ~AB XOR AC. The Quantum cost of this gate is 5.
integration and also by new fabrication processes. Reversible
B. Feynman Gate
logic can also reduce power dissipation of a circuit.
By definition logic function is called reversible if the
multiple output Boolean function of „n‟ variables F(x1, x2 ….
xn) [5] has
 The number of outputs equivalent to the number of
inputs.
 Any output pattern with an exceptional pre-image.

In a reversible gate, one to one mapping is coordinated Fig. 3. 2*2 Feynman Gate
between vectors of input and output; so the vector of input
states can be constantly remade. The output states vector does Fig. 3. is a 2*2 Feynman gate with input vectors A, B and
the reconstruction. A computation is called reversible if from the output vectors are A and A XOR B with a Quantum cost
output it is possible to recover the input. of 1. This gate is used as a copying gate. As the fan-out is not
Main properties of reversible logic is allowed in a reversible gate, this Feynman gate can be used as
replacement for duplication of the required output.
 Feedback is not allowed.
 Fan-out is not allowed. C. Peres Gate

Swap, inverter and buffer gates are naturally reversible

because they have same no of input and output.
Reversible logic came from the 2nd law of
thermodynamics. It states that “A state transition from one to
another equilibrium state is thermodynamically reversible, if
and only if the final state can be restored to the initial state,
without remaining any effect on the outside world.”
Reversible logic conserves power and hence reduces the
power dissipation in a circuit design. This is the main Fig. 4. 3*3 Peres Gate in both email address.
difference of reversible logic and irreversible logic. In
irreversible logic there is energy dissipation because of 3*3 Peres gate structure is described in Fig. 4. Input
information loss. vectors are A, B, C. and the output vectors are P=A, Q=A
The amount of energy dissipation for every bit operation XOR B, R=AB XOR C [5]. The Quantum cost of this gate is
(which are irreversible by nature) is minimum KTln2 joules, 4.
where K= Boltzmann constant and T is temperature at which
D. Taffoli Gate
the performance is performed. In room temperature because
of the bit loss heat generated. This heat is very small at room
temperature. But for higher computation, when the number of
bits lost is more than the heat dissipation became larger. It
affects the performance of that circuit. Both forward and
backward process can be run by reversible logic. Reversible
rationale can contribute to more yield. This yield can go back
and forth back to any point in the computation history. Four
types of reversible gates are used to implement our proposed
work. Fig. 5. Taffoli Gate
a. Fredkin gate
b. Feynman gate
c. Peres gate 3*3 Taffoli gate is mentioned in Fig. 5. Input vectors are A,
d. Taffoli gate B, C. and output vectors are P=A, Q=B, R=AB XOR C . The
A. Fredkin Gate Quantum cost [6] of a 3*3 Taffoli gate is 5.

III. SRAM CELL USING REVERSIBLE GATE

The Reversible SRAM cell is explained in Fig. 6. In this

proposed design we use 2 gates to implement SRAM cell.
Only a single bit data can be stored in this SRAM cell. This
cell has 2 states, i.e. HOLD and READ/WRITE.Working
principle of this reversible
SRAM cell depends on the
Fig. 2. 3*3 Fredkin Gate WL. When WL=0, SRAM cell

Retrieval Number: A10831291S319/2019@BEIESP Published By:

DOI:10.35940/ijeat.A1083.1291S319 Blue Eyes Intelligence Engineering
456 & Sciences Publication
 International Journal of Engineering and Advanced Technology (IJEAT)
ISSN: 2249 – 8958, Volume-9 Issue-1S3, December 2019

is in HOLD state and when WL=1 SRAM cell operates in In this work, we have implemented the TCAM Cell [8]
READ/WRITE mode. Output of Reversible SRAM cell is using reversible SRAM. TCAM Cell can be constructed by
shown in Fig. 7. Whereas Fig. 8. Describes the schematic of using PERES gate as well as TAFFOLI gate. At first write
Read Write SRAM CELL. (WL) signal and input data is given to the SRAM as inputs.
The output of the SRAM cell is given to 2*2 Feynman gate as
an input which is connected to another 2*2 Feynman gate,
followed by a 3*3 Fredkin gate. And at the end, this XORed
result is given as input to the Peres gate. From this gate the
Match line (ML) output is obtained. This match line (ML)
will be HIGH (1) when the search data bit (sl) and stored data
bit (b) matches for match bit (mb) be 0.

Match
WL WL SL SL Bit

3*3 2*2 2*2 2*2 3*3 3*3

Fredkin Feynman Feynman Feynman Fredkin Peres
Fig. 6. Schematic diagram of SRAM CELL Gate gate gate gate Gate Gate
0 ML
b 1 1 0
Table1: Truth Table of SRAM CELL Logic 1 for First Column cells
and previous match line
Write line q(n) Data Q(n+1) Bit state for others

1 0 0 0 0 Fig. 9. TCAM Cell using PERES Gate

1 1 1 1 1
If the stored and search data bit does not match then the
0 1 1 1 1 ML will be LOW (0). For Mb be 1, irrespective of the value
0 1 0 1 1 of sl and b, the ML will be always 1. TCAM Cell using
PERES gate block diagram is described in Fig. 9. and its RTL
view is shown in Fig. 10.

Fig. 7. Simulation results of SRAM CELL

IV. READ WRITE SRAM CELL

Fig. 8. illustrates the structure of read/ write SRAM cell Fig. 10. TCAM Cell using PERES gate
using reversible gates. Here the Row Decoder (WL) signal
controls the entire row. Quantum cost of this cell is 16 [7].
This TCAM cell can be implemented using Taffoli also. It
can be constructed by replacing the PERES gate with
TAFFOLI gate as in Fig. 11. But the Quantum cost is large in
the second case which also affects the worst case delay of the
circuit. But the garbage output is same for both designs.

VI. TCAM CELL WITH TAFFOLI GATE

The TCAM cell can be implemented with Taffoli gates as
well. In this structure we can replace the Peres gate with
Taffoli gate. After that we can calculate the delay and
Fig. 8. Schematic of Read Write SRAM CELL quantum cost of both TCAM. For Taffoli gate delay and
quantum cost is more than Peres gate. But the garbage value
V. TCAM CELL [9] is same for both cases.
Table 2 is the comparison
between Taffoli gate based

Retrieval Number: A10831291S319/2019@BEIESP Published By:

DOI:10.35940/ijeat.A1083.1291S319 Blue Eyes Intelligence Engineering
457 & Sciences Publication
 Low Power Implementation Of Ternary Content Addressable Memory (TCAM)

TCAM and Peres gate based TCAM. Here we have compared 0 1 1 1

both TCAM cell using Taffoli gate and Peres gate. We can 1 0 0 0
say from this table that for a single bit TCAM with Peres gate 1 0 1 1
Quantum cost and delay case is better than single bit TCAM 1 1 0 1
using Taffoli gate. The RTL view is shown in Fig. 12.
1 1 1 1
Simulation resultS of TCAM cell is shown in Fig. 13.

Fig. 11. TCAM Cell using PERES Gate

Fig. 13. Simulation result of TCAM cell

VII. 4*3 TCAM ARRAY ARCHITECTURE

In 4*3 array 4 numbers of each 3 bits can be stored in 4
rows [10]. From this array we can check the number where it
is saved in this array. Basically we can be informed where it
is saved in this array. In this array every TCAM will check
one bit. When we try to search a number, we give every bit in
the column for searching. When one bit is matched, match
line shows „1‟ (HIGH), like this if every bit matched with
stored bit every match line became one. But this case will
happen for one memory location only. But if any one of the
bits is not matched it becomes 0 (LOW). For this reason we
give every match line to the AND gate. If all the match line is
1 then only the AND gate output becomes 1. All the AND
gate outputs are sent to the 4:2 Encoder. Between those four
locations which location matches the searched data, the
decoder will give that matched location in single clock cycle.
Fig. 14. describes the working of 4*4 TCAM array.

Fig. 12. TCAM CELL using Taffoli gate

Table 2: Comparison of TCAM cells
Model Quantum Worst Case Garbage
Cost Delay Output
Single bit
TCAM with 18 18 6
Taffoli gate

Single bit
TCAM with 17 17 6
Peres gate

Table3: Truth Table of TCAM CELL

Stored Data Search data Match Data Match Data
bit (sl) bit (b) bit (mb) line (ml)
0 0 0 1
0 0 1 1
0 1 0 0

Retrieval Number: A10831291S319/2019@BEIESP Published By:

DOI:10.35940/ijeat.A1083.1291S319 Blue Eyes Intelligence Engineering
458 & Sciences Publication
 International Journal of Engineering and Advanced Technology (IJEAT)
ISSN: 2249 – 8958, Volume-9 Issue-1S3, December 2019

data is stored in this array. In this array, every TCAM can

check the matching of one bit. When we try to search a
number, we give every bit in the column for searching. When
one bit is matched with stored data (b), match line shows one.
Like this if every searched data match with stored bit, then
every match line became one. But if any of them is not
matched then ML becomes 0.

Fig. 14. Simulation result of 4*3 TCAM array

In the case of 4*4 TCAM array, we need sixteen TCAM

unit cells, four AND gates and one 4:2 encoder. At first, we
store four 4 bits data into the memory. Then we search for the
memory location of the searched data. Each bit of searched
data (sl) is given to each of the columns to search in parallel.
Then for each row, the match line (ML) outputs of all the
columns are sent to one AND gate. Whenever all the match
lines are one then only the AND gate output becomes one
(HIGH). This indicates the matched location in the array. The
encoder will provide the matched location of the TCAM
array memory. We can use this TCAM array as virtual
memory. Fig. 15 describes the simulation result of 4*4
TCAM array.

Fig. 16. 5*4 TCAM array architecture

Fig. 17. Simulation results of 5*4 TCAM array

For this reason we give every match line of a row to AND

Fig. 15. Simulation result of 4*4 TCAM array gate as inputs. If all the match line is 1 then only the AND
gate output became 1. We are using 5:3 encoder to locate the
address of the matched data. . Fig.16 describes the
VIII. PROPOSED 5*4 TCAM ARRAY architecture of 5*4 TCAM array and Fig. 17 describes the
ARCHITECTURE simulation result of 5*4 TCAM
In 5*4 array store five numbers in 5 row, each number array.
having 4 bits. From this array we can check where the search

Retrieval Number: A10831291S319/2019@BEIESP Published By:

DOI:10.35940/ijeat.A1083.1291S319 Blue Eyes Intelligence Engineering
459 & Sciences Publication
 Low Power Implementation Of Ternary Content Addressable Memory (TCAM)

IX. CONCLUSION
Being a lecturer for more than 25 years,
90nm based Spartan-3 FPGA is proved to work efficiently Dr. P. Augusta Sophy, has developed a passion
with TCAM using reversible logic. In this paper, we towards teaching Engineering subjects and guiding
projects. The passion has naturally been extended
implemented different types of TCAM array and checked towards developing the students too. Have handled
there working process. We made this TCAM cells with more than 20 different subjects in Electronics and
reversible logic i.e. Fredkin Gate, Feynman Gate, Taffoli Communication Engineering and guided more than
50 projects in UG and PG levels. She has
Gate and Peres gate to reduce the heat dissipation in TCAM. published 24 research papers in International
Also we noticed that Peres gate is better than Taffoli gate Conferences and Journals. She did her research work in the field of VLSI
when it comes to quantum cost and delay case. We have also Signal Processing in Anna University, in 2015. Received her M.E degree
from Anna University and finished her B.E degree in Government College of
proposed a new architecture of TCAM array using AND Engineering, Tirunelveli. Now she is working as Associate Professor in VIT
gates instead of parity Encoder. It also reduces the University, Chennai.
complexity of the circuit.

REFERENCES
1. Inayat Ullah, Zahid Ullah, Jeong-A Lee. "EE-TCAM: An
Energy-Efficient SRAM-Based TCAM on FPGA." Electronics, MDPI
journal, publised 10 septenber 2018
2. Kostas Pagiamzis, Ali Sheikholeslami, “Content-Addressable Memory
(CAM) Circuits andArchitectures: A Tutorial and Survey”, IEEE
JOURNAL OF SOLID-STATE CIRCUITS VOL.41, NO. 3, MARCH
2006
3. Md. Selim Al Mamun, David Menville “Quantum Cost Optimization
for Reversible Sequential Circuit” (IJACSA) International Journal of
Advanced Computer Science and Applications, Vol.4, No. 12,2013
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IEEE International Conference on Nanotechnology Portland Marriott
August 15-18, 2011, Portland, Oregon, USA.
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2012, pp.148
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AUTHORS PROFILE

Mr. Prithwiraj Das has completed his Bachelor of

Engineering in the stream of Electronics and
communication Engineering from RCC Institute of
Information Technology, Kolkata . Now he is
pursuing his Masters of Technology in VLSI Design
from Vellore Institute of Technology University,
Chennai. His area of interest is Digital IC Design,
DFT. Currently, he is an Technical graduate intern at
Intel Corporation.

Ms. Ria Pathak completed her Bachelor of

Engineering in the stream of Electronics and
communication Engineering from Dr. Sudhir
Chandra Sur Degree Engineering College, Kolkata,
West Bengal and pursuing her Masters in the field of
VLSI Design from Vellore Institute of Technology
University, Chennai. Her area of interests includes
VLSI, IoT and Artificial Intelligence.

Retrieval Number: A10831291S319/2019@BEIESP Published By:

DOI:10.35940/ijeat.A1083.1291S319 Blue Eyes Intelligence Engineering
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