LAB MANUAL
Subject Code: CS 404
Subject Name: Computer Organization & Architecture
List of Experiments
Exp. Experiment Name
No.
2 To design the circuit of half adder.
3 To design the circuit of full adder.
4 To design the circuit of half subtractor.
5 To design the circuit of full subtractor.
6 To design an 8×1 Multiplexer.
7 To design a 4 bit combinational shifter.
8 To design a BCD adder.
9 To design a 4-bit adder subtractor.
10 To design an ALU.
11 To design 2:4 Decoder
EXPERIMENT NO.2
Objective: To design the circuit of half adder.
IC USED: 7486(X-OR), 7408(AND).
THEORY: A half adder is a logical circuit that performs an additional operation on two binary digits.
The half adder produces a sum and a carry value which are both binary digits.
A half adder circuit has two inputs A and B and two outputs – S representing sum and C representing
carry.
S = A xor B i.e. (A’B + AB’)
C = A and B i.e. (A.B)
TRUTH TABLE:
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
SCHEMATIC DIAGRAM:
WAVEFORM:
RESULT: The output waveform of half adder is verified.
EXPERIMENT NO.3
Objective: To design the circuit of full adder.
IC USED: 7486(X-OR), 7408(AND), 7432(OR).
THEORY: A full adder is a logical circuit that performs an additional operation on three binary digits.
The half adder produces a sum and a carry value which are both binary digits.
A full adder circuit has three inputs A,B and Cin and two outputs – S representing sum and Cout
representing carry.
S = A xor B xor C
C = A.B +C(A xor B)
TRUTH TABLE:
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
SCHEMATIC DIAGRAM:
WAVEFORM:
RESULT: The output waveform of full adder is verified.
EXPERIMENT NO.4
Objective: To design the circuit of half subtractor.
IC USED: 7486(X-OR), 7408(AND), 7404(NOT).
THEORY: A half subtractor is a logical circuit that performs an subtraction operation on two binary
digits. The half subtractor produces a Difference and a borrow value which are both binary digits.
A half subtractor circuit has two inputs X, Y and two outputs – D representing difference and B
representing borrow.
D = A xor B i.e. (A’B + AB’)
B = A’B
TRUTH TABLE:
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
SCHEMATIC DIAGRAM:
WAVEFORM:
RESULT: The output waveform of half subtractor is verified.
EXPERIMENT NO.5
Objective: To design the circuit of full subtractor.
IC USED: 7486(X-OR), 7408(AND), 7432(OR),7404(NOT).
THEORY: A full subtractor is a logical circuit that performs an subtraction operation on three binary
digits. The full subtractor produces a difference and a borrow value which are both binary digits.
A Full adder circuit has three inputs A,B and C and two outputs – DIFF representing difference and
BOR representing borrow.
S = A xor B xor C
C = A’.B +C(A xnor B)
TRUTH TABLE:
A B C DIF BOR
F
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
SCHEMATIC DIAGRAM:
WAVEFORM:
RESULT: The output waveform of full subtractor is verified.
EXPERIMENT NO.6
Objective: To design an 8×1 Multiplexer.
IC USED: 7486(X-OR), 7408(AND), 7432(OR), 7404(NOT), 74151A (8×1 MUX).
THEORY: A multiplexer is a device that performs multiplexing i.e. it selects one of many analog or
digital input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has n
select lines, which are used to select which input line to be sent to the output.
A Boolean equation for 8×1 Multiplexer is
Z = A’.B’.C’ + A’.B’.C + A’.B.C’ + A’.B.C + A.B’.C’ + A.B’.C + A.B.C’ + A.B.C
TRUTH TABLE:
S0 S1 S2 Z
0 0 0 A
0 0 1 B
0 1 0 C
0 1 1 D
1 0 0 E
1 0 1 F
1 1 0 G
1 1 1 H
SCHEMATIC DIAGRAM:
WAVEFORM:
RESULT: The output waveform of 8×1 Multiplexer is verified.
EXPERIMENT NO.7
Objective: To design a 4 bit combinational shifter.
IC USED: 74157(quad 2×1 MUX).
THEORY: An n-bit shift circuit has a single n-bit data input A, and a single n-bit output R and a
number of control inputs to determine the shift amount ( 0 to n-1).
In this case the possible shift operations are SHIFT LEFT and SHIFT RIGHT. This shifting depends
on selection line input S. If S = 0 then SHIFT RIGHT operation takes place , else SHIFT LEFT
operation takes place.
SCHEMATIC:
WAVEFORM:
RESULT: The circuit of 4-bit combinational shifter is designed and output is verified.
EXPERIMENT NO.8
Objective: To design a BCD adder.
IC USED: 7483A (4-bit adder), 7408(AND), 7432(OR).
THEORY:
It is possible to perform addition in BCD by first adding in binary, and then converting to BCD
afterwards. Conversion of the simple sum of two digits can be done by adding 6 (that is, 16 – 10)
when the result has a value greater than 9.
For example:
1001 + 1000 = 10001 = 0001 0001
9 + 8 = 17 = 1 1
In BCD, there cannot exist a value greater than 9 (1001) per nibble. To correct this, 6 (0110) is added
to that sum to get the correct first two digits:
0001 0001 + 0000 0110 = 0001 0111
1 1+ 0 6= 1 7
This gives two nibbles, 0001 and 0111, which correspond to the digits "1" and "7". This yields "17"
in BCD, which is the correct result. This technique can be extended to adding multiple digits, by
adding in groups from right to left, propagating the second digit as a carry, always comparing the 5-
bit result of each digit-pair sum to 9.
SCHEMATIC:
WAVEFORM:
RESULT: BCD adder is designed and output is verified.
EXPERIMENT NO.9
Objective: To design a 4-bit adder subtractor.
IC USED: 7483A (4-bit adder), 7486(X-OR).
THEORY:
It is a combinational circuit which can act as both a binary adder and a binary subtractor. It is
constructed using 4 full adders.Block diagram of the circuit is shown below:
In this case if sub is 0, then the circuit acts as an adder,else subtractor. Subtraction is done by adding
two’s compliment of B to A, which effectively results in A - B.
SCHEMATIC:
WAVEFORM:
RESULT: The circuit of a 4-Bit adder subtractor is designed and verified.
EXPERIMENT NO.10
Objective: To design an ALU.
IC USED: 74153(4×1 MUX), 7432(OR), 7404(NOT), 7408(AND), 7486(XOR).
THEORY: In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic
and logical operations. The ALU is a fundamental building block of the central processing unit (CPU)
of a computer, and even the simplest microprocessors contain one for purposes such as maintaining
timers. The processors found inside modern CPUs and graphics processing units (GPUs)
accommodate very powerful and very complex ALUs; a single component may contain a number of
ALUs.
Mathematician John von Neumann proposed the ALU concept in 1945.
Below is a block diagram for an ALU:
SCHEMATIC:
WAVEFORM:
RESULT: The ALU is designed and its output is verified.
