L6491

Datasheet

High voltage high and low-side 4 A gate driver

Features
• High voltage rail up to 600 V
• dV/dt immunity ± 50 V/ns in full temperature range
• Driver current capability: 4 A source/sink
• Switching times 15 ns rise/fall with 1 nF load
• 3.3 V, 5 V TTL/CMOS inputs with hysteresis
• Integrated bootstrap diode
SO-14 • Comparator for fault protections
• Smart shutdown function
• Adjustable deadtime
• Interlocking function
• Compact and simplified layout
• Bill of material reduction
• Effective fault protection
• Flexible, easy and fast design

Applications

Product status link

• Motor driver for home appliances, factory automation, industrial drives and
L6491 fans
• HID ballasts
• Power supply unit
Product label
• Induction heating
• Wireless chargers
• Industrial inverters
• UPS

Description
The L6491 is a high voltage device manufactured with the BCD6 “OFF-LINE”
technology. It is a single-chip half-bridge gate driver for N-channel power MOSFET or
IGBT.
The high-side (floating) section is designed to stand a voltage rail up to 600 V. The
logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing
microcontroller/DSP.
An integrated comparator is available for fast protection against over-current, over-
temperature, etc.

DS9763 - Rev 2 - March 2024 www.st.com

For further information contact your local STMicroelectronics sales office.
 L6491
Block diagram

1 Block diagram

Figure 1. Block diagram

VCC

PGND

COMPARATOR

DS9763 - Rev 2 page 2/23

 L6491
Pin description

2 Pin description

Figure 2. Pin configuration

LIN 1 14 BOOT
SD/OD 2 13 HVG
HIN 3 12 OUT
VCC 4 11 NC
DT 5 10 CP+
SGND 6 9 CP-
PGND 7 8 LVG

Table 1. Pin description

Pin number Pin name Type Function

1 LIN I Low-side driver logic input (active low)

Shutdown logic input (active low)/open-drain
2 SD/OD (1) I/O
comparator output
3 HIN I High-side driver logic input (active high)
4 VCC P Lower section supply voltage
5 DT I Deadtime setting
6 SGND P Signal ground
7 PGND P Power ground

8 LVG (1) O Low-side driver output

9 CP- I Comparator negative input

10 CP+ I Comparator positive input
11 NC Not connected
12 OUT P High-side (floating) common voltage

13 HVG (1) O High-side driver output

14 BOOT P Bootstrapped supply voltage

1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This
allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low.
When the SD is set low, gate driver outputs are forced low and assure low impedance.

DS9763 - Rev 2 page 3/23

 L6491
Truth table

3 Truth table

Table 2. Truth table

Input Input

SD LIN HIN LVG HVG

L X (1) X (1) L L

H H L L L
H L H L L
H L L H L
H H H L H

1. X: don't care.

DS9763 - Rev 2 page 4/23

 L6491
Electrical data

4 Electrical data

4.1 Absolute maximum ratings

Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress
ratings only and functional operation of the device at these conditions is not implied. Operating outside maximum
recommended conditions for extended periods of time may impact product reliability and result in device failures.

Table 3. Absolute maximum ratings

Each voltage referred to SGND unless otherwise specified.
Value
Symbol Parameter Unit
Min. Max.

VCC Supply voltage - 0.3 21 V

VPGND Low-side driver ground VCC - 21 VCC + 0.3 V

Vout Output voltage Vboot - 21 Vboot + 0.3 V

Vboot Bootstrap voltage -0.3 620 V

Vhvg High-side gate output voltage Vout - 0.3 Vboot + 0.3 V

Vlvg Low-side gate output voltage PGND - 0.3 VCC + 0.3 V

Vcp- Comparator negative input voltage (1) -0.3 5.5 V

Vcp+ Comparator positive input voltage (1) -0.3 5.5 V

Vi Logic input voltage -0.3 15 V

VOD Open-drain voltage -0.3 15 V

dVout/dt Allowed output slew rate 50 V/ns

Ptot Total power dissipation (TA = 25 °C) 1.0 W

TJ Junction temperature 150 °C

Tstg Storage temperature -50 150 °C

ESD Human body model 2 kV

1. Spikes up to 20 V can be tolerated if the duration is shorter than 50 ns (fSW = 120 kHz).

4.2 Thermal data

Table 4. Thermal data

Symbol Parameter SO-14 Unit

Rth (JA) Thermal resistance junction to ambient 120 °C/W

DS9763 - Rev 2 page 5/23

 L6491
Electrical data

4.3 Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Pin Parameter Test conditions Min. Max. Unit

VCC 4 Supply voltage 10 20 V

VPS (1)
7-6 Low-side driver ground -1.5 +1.5 V

VBO (2) 14 - 12 Floating supply voltage 9.3 20 V

Vout 12 DC output voltage -9 (3) 580 V

Comparator negative
VCP- 9 VCP+ ≤ 2.5 V 5 (4) V
input pin voltage
Comparator positive
VCP+ 10 VCP- ≤ 2.5 V 5 (4) V
input pin voltage
fsw Switching frequency HVG, LVG load CL = 1 nF 800 kHz

TJ Junction temperature -40 125 °C

1. VPS = VPGND - SGND.

2. VBO = Vboot - Vout.
3. LVG off. VCC = 12.5 V. Logic is operational if Vboot > 5 V.
4. At least one of the comparator's inputs must be lower than 2.5 V to guarantee proper operation.

DS9763 - Rev 2 page 6/23

 L6491
Electrical characteristics

5 Electrical characteristics

5.1 AC operation

Table 6. AC operation electrical characteristics

VCC = 15 V; PGND = SGND; TJ = +25 °C
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit

High/low-side driver turn-on

ton OUT = 0 V 85 120 ns
1 vs. 8 propagation delay
BOOT = VCC
3 vs 13 High/low-side driver turn-off
toff CL = 1 nF 85 120 ns
propagation delay
Vi = 0 to 3.3 V
2 vs. Shutdown to high/low-side driver see Figure 3
tsd 85 120 ns
8, 13 propagation delay

Measured applying a voltage

Comparator triggering to high/low-side
tisd step from 0 V to 3.3 V to pin 175 220 ns
driver turn-off propagation delay
CP+; CP- = 0.5 V
Delay matching, HS and LS turn-on/off
MT (1) 30 ns

RDT = 0 Ω, CL = 1 nF 0.12 0.18 0.24 µs

RDT = 100 kΩ, CL = 1 nF

1.2 1.4 1.6 µs
DT 5 Deadtime setting range see Figure 4 CDT = 100 nF

RDT = 200 kΩ, CL= 1 nF

2.2 2.6 3 µs
CDT = 100 nF

RDT = 0 Ω, CL = 1 nF 50 ns

RDT = 100 kΩ, CL = 1 nF

165 ns
MDT Matching deadtime (2) CDT = 100 nF

RDT = 200 kΩ, CL = 1 nF

260 ns
CDT = 100 nF

tr Rise time CL = 1 nF 15 40 ns
8,13
tf Fall time CL = 1 nF 15 40 ns

1. MT = max. (|ton(LVG) - toff(LVG)|, |ton(HVG) - toff(HVG)|, |toff(LVG) - ton(HVG)|, |toff(HVG) - ton(LVG)|).

2. MDT = | DTLH - DTHL | (see Figure 5).

DS9763 - Rev 2 page 7/23

 L6491
Electrical characteristics

Figure 3. Timing

50% 50%
LIN
tr tf
90% 90%

LVG 10% 10%

ton toff

50% 50%
HIN
tr tf
90% 90%

HVG 10% 10%

ton toff

50%
SD
tf
90%

LVG/HVG 10%

tsd

Figure 4. Typical deadtime vs. DT resistor value

2.75

2.50 Approximated formula for Rdt

2.25 calculation (typ):
Rdt [kΩ] = 82 · DT [µs] -14.8
2.00

1.75
DT [µs]

1.50

1.25

1.00

0.75

0.50

0.25

0.00
0 50 100 150 200 250

Rdt [kΩ]

DS9763 - Rev 2 page 8/23

 L6491
Electrical characteristics

5.2 DC operation

Table 7. Operation electrical characteristics

VCC = 15 V; PGND = SGND; TJ = + 25 °C
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit

Low-side supply voltage section

VCC_hys VCC UV hysteresis 0.5 0.6 0.72 V

VCC_thON VCC UV turn-ON threshold 8.7 9.3 9.8 V

VCC_thOFF VCC UV turn-OFF threshold 8.2 8.7 9.2 V

VCC = 8 V
SD = 5 V; LIN = 5 V;
Undervoltage quiescent supply
Iqccu HIN = SGND; 160 210 μA
4 current
RDT = 0 Ω;
CP+ = SGND; CP- = 5 V
VCC = 15 V
SD = 5 V; LIN = 5 V;
Iqcc Quiescent current HIN = SGND; 540 700 μA
RDT = 0 Ω;
CP+ = SGND; CP- = 5 V

Bootstrapped supply voltage section (1)

VBO_hys VBO UV hysteresis 0.48 0.6 0.7 V

VBO_thON VBO UV turn-ON threshold 8 8.6 9.1 V

VBO_thOFF VBO UV turn-OFF threshold 7.5 8.0 8.5 V

VCC = VBO = 7 V
SD = 5 V; LIN and
Undervoltage VBO quiescent
IQBOU HIN = 5 V; 20 30 μA
14-12 current
RDT = 0 Ω;
CP+ = SGND; CP- = 5 V
VBO = 15
SD = 5 V; LIN and
IQBO VBO quiescent current HIN = 5 V; 90 120 μA
RDT = 0 Ω;
CP+ = SGND; CP- = 5 V
ILK High voltage leakage current BOOT = HVG = OUT = 600 V 8 μA

Bootstrap driver on resistance

RDS(on) (2) 175 Ω

Driving buffer section

LVG/HVG ON
High/low-side source peak 3.5 4 A
Iso TJ = 25 °C
current
Full temperature range 2.5 A
8, 13
LVG/HVG OFF
3.5 4 A
Isi High/low-side sink peak current TJ = 25 °C

Full temperature range 2.5 A

Logic inputs
Vil Low level logic threshold 0.95 1.45 V
1, 2, 3 High level logic threshold
Vih 2 2.5 V
voltage

DS9763 - Rev 2 page 9/23

 L6491
Electrical characteristics

Symbol Pin Parameter Test conditions Min. Typ. Max. Unit

VSSD 2 Smart SD unlatch threshold 0.8 V

LIN and HIN connected

Vil_S 1, 3 Single input voltage 0.8 V
together and floating
RPD_HIN HIN pull-down resistor HIN = 15 V 58 75 125 kΩ

IHINh 3 HIN logic “1” input bias current HIN = 15 V 120 200 260 μA

IHINl HIN logic “0” input bias current HIN = 0 V 1 μA

RPU_LIN LIN pull-up resistor 287 430 860 kΩ

ILINl 1 LIN logic “0” input bias current LIN = 0 V 5 10 15 μA

ILINh LIN logic “1” input bias current LIN = 15 V 1 μA

RPD_SD SD pull-down resistor SD = 15 V 250 375 750 kΩ

ISDh 2 SD logic “1” input bias current SD = 15 V 20 40 60 μA

ISDl SD logic “0” input bias current SD = 0 V 1 μA

1. VBO = Vboot - Vout.

2. RDS(on) is tested in the following way:
RDS(on) = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC, VBOOT1) - I2(VCC, VBOOT2)] where I1 is pin 14 current when
VBOOT = VBOOT1, I2 when VBOOT = VBOOT2.

Table 8. Sense comparator

VCC = 15 V, TJ = +25 °C
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit

Vio 9, 10 Input offset voltage -15 15 mV

Iib 9, 10 Input bias current VCP+ = 1 V, VCP- = 1 V 1 μA

RON_SD SD on-resistance SD\OD = 400 mV 15 20 31 kΩ

2
IOD Open-drain low level sink current VCP+ = 1 V; VCP-= 0.5 V 13 20 27 mA

Rpu = 100 kΩ to 5 V; VCP- = 0.5 V

td_comp Comparator delay voltage step on CP+ = 0 to 3.3 V 100 155 ns
50% CP+ to 90% SD
CL=10 nF;
SR 2 Slew rate Rpu = 5 kΩ to 5 V; 10 V/μs
90% SD to 10% SD

Note: Comparator is disabled when VCC is in UVLO condition.

DS9763 - Rev 2 page 10/23

 L6491
Waveform definitions

6 Waveform definitions

Figure 5. Deadtime and interlocking waveform definitions

LIN

ING

ING
CONTROL SIGNAL EDGES HIN

OCK
LOC
OVERLAPPED:

ERL
ER
INTERLOCKING + DEAD TIME LVG

INT

INT
DTLH DTHL
HVG
gate driver outputs OFF gate driver outputs OFF
(HALF-BRIDGE TRI-STATE) (HALF-BRIDGE TRI-STATE)

LIN

CONTROL SIGNALS EDGES HIN

SYNCHRONOUS (1):
DEAD TIME
LVG
DTLH DTHL
HVG
gate driver outputs OFF gate driver outputs OFF
(HALF-BRIDGE TRI-STATE) (HALF-BRIDGE TRI-STATE)

LIN

CONTROL SIGNALS EDGES HIN

NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME: LVG
DEAD TIME
DTLH DTHL
HVG

gate driver outputs OFF gate driver outputs OFF

(HALF-BRIDGE TRI-STATE) (HALF-BRIDGE TRI-STATE)

LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED, HIN
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
LVG
DTLH DTHL
HVG

gate driver outputs OFF gate driver outputs OFF

(HALF-BRIDGE TRI-STATE) (HALF-BRIDGE TRI-STATE)

(*) HIN and LIN can be connected togheter and driven by just one control signal

DS9763 - Rev 2 page 11/23

 L6491
Smart shutdown function

7 Smart shutdown function

The L6491 device integrates a comparator committed to the fault sensing function. The comparator input can be
connected to an external shunt resistor in order to implement a simple overcurrent detection function.
The output signal of the comparator is fed to an integrated MOSFET with the open-drain output available on pin 2,
shared with the SD input. When the comparator triggers, the device is set in shutdown state and both its outputs
are set to low level leaving the half-bridge in 3-state.

Figure 6. Smart shutdown timing waveforms

CP-

CP+

HIN/LIN

PROTECTION
HVG/LVG

SD/OD

open drain gate

(internal)

disable time
Fast shut down:
the driver outputs are set in SD state immediately after the comparator
triggering, even if the SD signal has not yet reach the lower input threshold

An approximation of the disable time is given by:

SHUT DOWN CIRCUIT

VBIAS

RSD where:

SD/OD
FROM/TO
SMART
CONTROLLER
SD

CSD RON_OD LOGIC

RPD_SD

DS9763 - Rev 2 page 12/23

 L6491
Smart shutdown function

In common overcurrent protection architectures, the comparator output is usually connected to the SD input and
an RC network is connected to this SD/OD line in order to provide a monostable circuit, which implements a
protection time following the fault condition.
Differently from the common fault detection systems, the L6491 smart shutdown architecture allows immediate
turn-off of the output gate driver in case of fault, by minimizing the propagation delay between the fault detection
event and the current output switch-off. In fact the time delay between the fault and the output turn-off is no longer
dependent on the RC value of the external network connected to the SD/OD pin. In the smart shutdown circuitry,
the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. At
the same time, the internal logic turns on the open-drain output and holds it on until the SD voltage goes below
the smart SD unlatch threshold VSSD. When such threshold is reached, the open-drain output is turned off,
allowing the external pull-up to recharge the capacitor. The driver outputs restart following the input pins as soon
as the voltage at the SD/OD pin reaches the higher threshold of the SD logic input.
The smart shutdown system gives the possibility to increase the time constant of the external RC network (that
determines the disable time after the fault event) up to very large values without increasing the delay time of the
protection.
Any external signal provided to the SD pin is not latched and can be used as control signal in order to perform, for
instance, PWM chopping through this pin. In fact when a PWM signal is applied to the SD input and the logic
inputs of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs
and vice versa.

DS9763 - Rev 2 page 13/23

 L6491
Typical application diagram

8 Typical application diagram

Figure 7. Typical application diagram

BOOTSTRAP DRIVER FLOATING STRUCTURE

VCC VCC 4 14 BOOT
+
CVCC1
H.V.
Cboot
HVG
DRIVER
FROM CONTROLLER Rg
HIN 3 LEVEL 13 HVG
Rfilt SHIFTER
Cfilt 5V

LOGIC

FROM CONTROLLER SHOOT

LIN 1
THROUGH
Rfilt PREVENTION 12 OUT
Cfilt
TO LOAD
VCC
LVG
Vpu DRIVER Rg
8 LVG
FROM/TO RSD
CONTROLLER SD/OD 2

5V PGND
CSD SMART
COMPARATOR RLP
SD 10 CP+
+
- CP- CLP
Vpu
9
VCC
DT 5 DEAD Rp1
CVCC2
TIME
Rshunt
RDT CDT SGND 7 Cp2 Rp2
6
PGND
System power ground

Figure 8. Suggested PCB layout

Vpu
SD/OD
CBOOT
LIN Rfilt Cfilt RSD

CSD
HIN Rfilt Cfilt

VCC
SGND
plane

CLP
CVCC1 RDT CDT
Cp+

Cp2

Vpu Rg
CVCC2 Rp2
Rp1 RLP
uC Signal GROUND
Rshunt

POWER GROUND
BOTTOM layer
TOP layer

DS9763 - Rev 2 page 14/23

 L6491
Bootstrap driver

9 Bootstrap driver

A bootstrap circuitry is needed to supply the high voltage section. This function is usually accomplished by a high
voltage fast recovery diode (see Section 9). In the L6491 an integrated structure replaces the external diode.

Figure 9. Bootstrap driver with external high voltage fast recovery

DBOOT

VCC BOOT

H.V.

HVG
CBOOT

OUT
TO LOAD

LVG

9.1 CBOOT selection and charging

To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor.
This capacitor CEXT is related to the MOS total gate charge:
Equation 1
Qgate
CEXT = Vgate (1)

The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It must be: CBOOT
>> CEXT.
For example: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV.
If HVG must be supplied for a long period, the CBOOT selection must take into account also the leakage and
quiescent losses.
For example: HVG steady-state consumption is lower than 120 μA, therefore, if HVG ton is 5 ms, CBOOT must
supply 0.6 μC to CEXT. This charge on a 1 μF capacitor means a voltage drop of 0.6 V.
The internal bootstrap driver offers a big advantage: the external fast recovery diode can be avoided (it usually
has very high leakage current). This structure can work only if VOUT is close to SGND (or lower) and, in the
meantime, the LVG is on. The charging time (tcharge) of the CBOOT is the time in which both conditions are fulfilled
and it Must be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDS(on) (typical value: 175 Ω). This drop can be
neglected at low switching frequency, but it should be taken into account when operating at high switching
frequency.
Eq. (2) is useful to compute the drop on the bootstrap DMOS:
Equation 2
Qgate
Vdrop = Icℎarge ∙ RDS(on) Vdrop = tcℎarge ∙ RDS(on) (2)

where Qgate is the gate charge of the external power MOS, RDS(on) is the ON-resistance of the bootstrap DMOS,
and tcharge is the charging time of the bootstrap capacitor.
For example: using a power MOS with a total gate charge of 30 nC, the drop on the bootstrap DMOS is about 1 V,
if the tcharge is 5 μs. In fact:
Equation 3
30nC
Vdrop = 5μs ∙ 175Ω~1V (3)

Vdrop should be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the
circuit topology doesn’t allow a sufficient charging time, an external diode can be used.

DS9763 - Rev 2 page 15/23

 L6491
Package information

10 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

10.1 SO-14 package outline

Figure 10. SO-14 package information

SEATING
PLANE 0.25 mm
h x 45° GAGE PLANE

C L

A H

A2
E
A1

7
8
B

e
D

14

DS9763 - Rev 2 page 16/23

 L6491
Package information

Table 9. SO-14 package mechanical data

Dimensions (mm)
Symbol
Min. Typ. Max.

A 1.35 1.75
A1 0.10 0.25
A2 1.10 1.65
B 0.33 0.51
C 0.19 0.25
D 8.55 8.75
E 3.80 4.00
e 1.27
H 5.80 6.20
h 0.25 0.50
L 0.40 1.27
k 0 8
ddd 0.10

Figure 11. SO-14 package suggested land pattern

1,27

0.60

4.0

6.7

DS9763 - Rev 2 page 17/23

 L6491
Ordering information

11 Ordering information

Table 10. Order code

Order Code Package Package marking Packaging

L6491D SO-14 L6941D Tube

L6491DTR SO-14 L6941D Tape and reel

DS9763 - Rev 2 page 18/23

 L6491

Revision history
Table 11. Document revision history

Date Version Changes

11-Mar-2015 1 Initial release.

Updated Table 7 (added RHIN_PD, RLIN_PU and RSD_PD ), Table 8 (added
22-Mar-2024 2
RON_SD) and Section 9.

DS9763 - Rev 2 page 19/23

 L6491
Contents

Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3 Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
4.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
8 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
9 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
9.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
10.1 SO-14 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

DS9763 - Rev 2 page 20/23

 L6491
List of tables

List of tables
Table 1. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 6. AC operation electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 7. Operation electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Sense comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. SO-14 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Typical deadtime vs. DT resistor value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Deadtime and interlocking waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Smart shutdown timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Suggested PCB layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Bootstrap driver with external high voltage fast recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. SO-14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. SO-14 package suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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