Layout Optimizations for Double Patterning
Lithography
David Z. Pan, Jae-seok Yang, Kun Yuan, Minsik Cho† , and Yongchan Ban
Dept. of ECE, The University of Texas at Austin, Austin, TX 78712
† IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
Abstract—Lithography process has become one of the most SADP, but requires more accurate overlay control to align two
fundamental limitations for 22nm technology node because of the exposures [12]–[15]. LFLE works by freezing the developed
following reasons: 1) combining immersion and computational resist pattern of the first exposure, then adding a second resist
lithography, which is the most advanced lithography scheme,
may not be enough to be used for 22nm patterning, 2) EUV layer immediately on top for the second exposure. The resist
(Extreme Ultra-Violet) lithography may not be available for pattern is etched at one time after developing. LFLE uses
mass production in the near future. As a practical solution, fewer processing steps [16] [17]. SADP works by depositing a
pitch doubling technique known as double patterning lithography spacer layer over the chip covering all hard mask features. The
(DPL) has become a strong candidate for 22nm lithography covered layer is selectively etched away leaving two sidewalls
process. Since layout decomposition in DPL plays an important
role in addressing the patterning quality, this paper will discuss along any ridge, then the ridge is removed [18]. The overlay
some recent advancement of decomposition and optimization requirement of SADP is less stringent than for other double
techniques for DPL friendly layout. We will also discuss the re- patterning methods. However, SADP is only applicable for 1-
search challenges for double patterning from an EDA perspective. D patterning having the same transistor length and requires
more processing steps.
Every type of DPL requires layout decomposition before
I. I NTRODUCTION
manufacturing [19] [20]. When two features are located
Current lithography technology has been facing severe lim- closely within the minimum design rule, they need to be de-
itations because 193nm based lithography tool is hard to print composed on two different masks for LELE and LFLE. SADP
sub-30nm half pitch patterns [1]–[6]. The smallest printable also requires layout decomposition to assign a feature to a
feature size is defined as K1·λ/NA where K1 is referred to specific sidewall. During decomposition, coloring conflict can
as K-factor for a given process showing the difficulty of be resolved by inserting stitches as shown in Fig. 1(a) without
lithography. λ is wave-length of the light source, and NA is the layout modification. However, minimum stitch insertion is
numerical aperture determined by lens size. Since the lower preferred because of the following reasons: 1) stitch insertion
bound of K-factor is 0.28 [7], it is challenging to print sub- requires overlap margin for overlay, resulting in unwanted chip
30nm patterns with current lithography equipments. area increase, 2) stitches may result in significant printability
One possible solution to overcome the limitation is to degradation due to overlay error and line-end effect [21].
use high NA lithography system. Chip makers have been
using immersion lithography for sub-40nm patterning which
enhances NA from 0.93 (dry) to 1.35 (wet). However, it is hard
to find new liquid material to increase NA more than 1.35 in
the near future. E-beam lithography and nanoimprint are not
yet in the mainstream [8], as well. As an ideal solution, EUV
lithography has been proposed. Since the wavelength of EUV
light source is 13.5nm, sub-10nm patterning is possible with (a) Resolvable conflict (b) Native Conflict
EUV. However, EUV lithography equipment is not available Fig. 1. Resolvable and native conflict.
for 22nm production due to technical barriers such as the lack
of power sources, resists, and defect-free masks [9] [10]. Several decomposition methods to achieve minimum stitch
An alternative choice for sub-22nm technology node is insertion have been proposed after placement and rout-
DPL [11]. In DPL, pitch size which limits the patterning ing [22] [23]. However, decomposition after layout generation
resolution, becomes twice than that of single patterning. may be too late to resolve all the conflicts. Fig. 1(b) shows a
Double patterning can be implemented in three ways: Litho- case in which stitch insertion cannot resolve a conflict. Such
Etch-Litho-Etch (LELE), Litho-Freeze-Litho-Etch (LFLE), an irresolvable conflict is called a native conflict which can
and Self-Aligned Double Patterning (SADP). LELE uses two only be removed by layout modification. Therefore, an effort
lithography exposures and etches on hard-mask to create to reduce native conflicts should be taken during placement,
smaller chip features. LELE uses fewer processing steps than routing, and redundant via optimization to shorten design time.
This paper will discuss the recent achievements to enhance
decomposability and patterning quality in DPL.
In this paper, we will survey layout decomposition meth-
ods developed recently in section II. DPL friendly routing
(a) Decomposition without (b) Decomposition with over-
approaches will be introduced in section III. In section IV, overlay compensation lay compensation
we show other layout optimization issues for better double
patterning quality. We draw the conclusion and point out some Fig. 3. Overlay compensated decomposition.
research directions in Section V.
II. L AYOUT D ECOMPOSITION In [26], Yang et al. proposes an overlay aware timing
Double patterning layout decomposition can be categorized analysis method from measurement of translation, rotation,
as rule-based and model-based methods. Rule-based approach and magnification overlay, and shows that decomposition plays
is relative simple to apply, while time-expensive lithography a roll to compensate the overlay effect in terms of timing
modeling is required in model-based methodology. variation. Fig. 3 shows an observation how to compensate the
Many research works, e.g., [22] [23] focus on rule-based overlay effect by decomposition. When we do not consider
methods. In [22], Kahng et al. proposed a practical double overlay during decomposition, the variation of a coupling
patterning layout decomposition flow. They first apply graph capacitance between two metal layers are in the same direction
techniques to detect the features associated with irresolvable as shown in Fig. 3(a). However, Fig. 3(b) shows less timing
conflict cycles. When an odd number of conflicts are detected variation because C1 decreases when C2 increases with over-
in a conflict graph, a stitch is inserted to break the conflict lay.
cycle. Then, the algorithm decomposes a design to minimize
the number of stitches based on ILP formulation. Various III. DPL F RIENDLY LAYOUT OPTIMIZATION
design constraints, such as minimum width and minimum Layout decomposition is the most critical step for DPL,
overlap margin, are also taken into account. as discussed in Section I and II, especially highly com-
Yuan et al. [23] developed an ILP based layout decom- plex for metal layers due to 2D patterns. However, layout
position algorithm for simultaneous conflict and stitch mini- decomposition itself can be very complex and NP-Complete,
mization. To enable effective co-optimization, they first pro- which cannot be solved by a 2-coloring algorithm. There-
posed a grid model to provide fine resolution for splitting fore, such criticality and complexity of layout decomposition
options. As Fig. 2 shows, the whole layout will be mapped clearly requires design time consideration, more specifically
into grids. Each grid is either empty or fully occupied by during detailed routing and redundant via insertion. Current
the pattern, and each occupied grid will be assigned one industrial effort to accomplish layout decomposition is to
color. Any boundary between occupied grids is a potential first finish detailed routing and via insertion, then perform
splitting location. After formulating their algorithm into ILP layout decomposition for DPL. If there is any indecomposable
problem, they also developed several speedup techniques to polygon, rip-up&rerouting should be performed repeatedly to
reduce problem size and improve the runtime and scalability. fix the conflict, resulting in long design-turn-around-time. A
Their results show significant improvement over traditional detailed routing oblivious DPL may generate highly complex
two-phase decomposition flow which separates coloring and patterns which may increase the indecomposable wire length.
splitting stages. Additionally, finding a decomposable layout is not sufficient
for successful DPL processes; the number of stitches should
be minimized to make a layout robust against overlay error.
Therefore, it is critical to consider DPL in a correct-by-
construction manner during detailed routing and redundant via
insertion.
Fig. 4 motivates why DPL-friendly detailed routing is a key
mincs mincs
to the successful DPL. For a net A-B-C, its Steiner tree is
shown in Fig. 4(a). If a conventional router connects this net,
it may generate a solution in Fig. 4(b) which is not decompos-
Fig. 2. Grid layout model for layout decomposition. able (even with stitches) due to the conflict inside the circle,
although it achieves the shortest possible wire length. If DPL-
There are layout decomposition flows which include lithog- friendly detailed routing is applied to this net, we can get either
raphy simulation. In [24], Bailey et al. make use of Optical (c) or (d) which is both decomposable for DPL with different
Proximity Correction (OPC) to analyze the quality of the overheads. We have a stitch in Fig. 4(c) but two vias in
decomposition. The validation result will be returned to the Fig. 4(d), in order to make a layout decomposable. Therefore,
flow for iterative refinement. Chiou et al. [25] further apply a detailed routing can play a critical role in improving layout
a model-base pattern splitting method to locally correct irre- decomposability by exploring the best trade-off among wire
solvable coloring errors after rule-based decomposition. length, stitch, and via.
Metal2 Metal2
A A E2 E2
DPL-friendly Extra Metal conflict
extension minsp
B B Metal1 mindp
Metal1
Decomposition
C C
E1 E1 conflict
Conflict
(a) Net A-B-C and its Steiner tree (b) A routing solution from a (a) (b)
with WL=21 in the dotted line are conventional detailed router has
shown. The checked boxes are the WL=24, but with decomposition Fig. 5. Illustration of redundant via DPL-compliance problem
blockages on M1. conflicts inside the dotted circle.
Stitch
proposed an ILP based post-routing redundant via insertion
A A algorithm to maximize insertion rate, while introducing zero
M1 Wire
conflict and minimal extra stitches to existing layout. More-
M2 Wire
over, to better resolve this problem in design side, the authors
B M2 B
Blockage
also developed a DPL-friendly detailed router with redundant
C C via consideration.
(c) One DPL-friendly solution (d) Another DPL-friendly solu- IV. OTHER L AYOUT O PTIMIZATION I SSUES
is shown with one stitch and tion is shown without any stitch
WL=34. and WL=28, but with 2 vias. To relieve the complexity and difficulty of layout decom-
position, many layout optimization and correction studies are
Fig. 4. This example motivates DPL consideration during detailed routing. conducted in terms of double patterning friendly OPC, gridded
Detailed routing algorithm can make effective trade-off among layout decom-
posability, wire length, the number of stitches, and the number of vias. design, process-design co-optimization, etc.
For post layout correction, many studies [28]–[31] proposed
a new OPC method to adapt double patterning and layout
Cho et al. [21] presents the first DPL friendly detailed decomposition problem. In [28], Li at al. introduced an overlap
routing algorithm which performs routing and layout decom- correction method on the stitching locations. For any re-cut
position in one shot, in a correct-by-construction manner. and/or redesigned pattern after verification, they categorized
The key idea in [21] is to perform detailed routing and lay- DP decompositions and introduced a new Adaptable OPC
out decomposition simultaneously in a correct-by-construction (Ad-OPC) algorithm by reusing post OPC layout to speed
manner, in order to accomplish high layout decomposability up the correction and improve its convergence according to
and reduce the number of overlay-error-prune stitches. In environment surrounding. In a similar way, Gheith at al.
detailed, while routing a net, the algorithm in [21] finds a path in [29] suggested a DPL OPC method which can be able
which introduces fewer DPL-related conflicts with the already to consider interlayer misalignment and corner rounding at
routed wires. Since decomposition is done along with detailed decomposed edges. Stitch point optimization for 3D wafer-
routing, [21] directly outputs a decomposed layout without topography effect due to stack structure is studied in [31].
an extra time-consuming decomposition step. Experimental Kamohara et al. investigate the impact of light reflectivity on
results in [21] show that the proposed approach improves the the stitch point and suggested an optimal layout.
quality of layout significantly in terms of decomposability and Gridded design rule based on one dimensional layout is
the number of stitches with 3.6x speedup, compared with a one of solutions of DPL layout optimization. Many research
current industrial DPL design flow. works, e.g., [32] [33] have been reported a simple design
Redundant via, widely used yield improvement technique, rule for double patterning application. The basic idea is that
could introduce complexity in DPL compliance. Fig. 5(a) the target design layout is drawn with a single pitch and a
shows a motivational example, where the top rectangles are single line/space type to get the best process-robust layout.
metal2 and the bottom rectangles are metal1. As Fig. 5(a) In [32], Bencher et al. demonstrated the scaling capability
indicates, E1 and E2 are the extra metals, which is used of gridded design rule to 16nm and 22nm logic nodes and
to cover the via and the redundant via in both layers. To reported the results of their implementation on Intel 45nm
avoid introducing additional stitch, these extensions should node poly-silicon layer. Smayling et al. in [33] reported results
have the same color because the metal and the via touches of gridded rule for 22nm logic design in SADP.
in corresponding layer. However, this may cause conflicts due Process-design co-optimization [34] [35] has been actively
to the coloring assignment of existing layout. In Fig. 5(b), the studied to overcome the resolution limit. In [34], Rubinstein
stitch-free extension will introduce a conflict in both metal1 et al. used pattern matching technique and suggested through
and metal2. focus model to find process weak pattern for double patterning.
As a solution of the problem, Yuan et al. [27] developed The pattern matcher is orders of magnitude faster than full
a detailed routing framework to perform double patterning simulation, and can be used to quickly scan layouts for
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