L99PM62XP

Power management IC with LIN and high speed CAN

Features
■ Two 5V voltage regulators for microcontroller
and peripheral supply
■ No electrolytic capacitor required on regulator
outputs
■ Ultra low quiescent current in standby modes
■ Programmable reset generator for power-on PowerSSO-36
and undervoltage
■ Configurable window watchdog and fail safe
output Description
■ LIN 2.1 compliant (SAEJ2602 compatible) The L99PM62XP is a power management system
transceiver IC providing electronic control units with
■ Advanced HS CAN transceiver (ISO 11898-2/- enhanced system power supply functionality
5 and SAE J2284 compliant) with local failure including various standby modes as well as LIN
and bus failure diagnosis and HS CAN physical communication layers. It
contains two low drop voltage regulators to supply
■ HS CAN transceiver supports partial
the system microcontroller and external
networking
peripheral loads such as sensors and provides
■ Complete 3 channel contact monitoring enhanced system standby functionality with
interface with programmable cyclic sense programmable local and remote wake up
functionality capability.
■ Programmable periodic system wake up In addition, five high-side drivers, two low-side
feature drivers and two operational amplifiers increase
■ ST SPI interface for mode control and the system integration level.
diagnosis
The ST standard SPI interface (3.0) allows control
■ 5 fully protected high-side drivers with internal and diagnosis of the device and enables generic
4-channel PWM generator software development.
■ 2 low-side drivers with active zener clamping
Table 1. Device summary
■ 4 internal PWM timers
Order codes
■ 2 operational amplifiers with rail-to-rail outputs
Package
(VS) and low voltage inputs Tube Tape and reel
■ Temperature warning and thermal shutdown
PowerSSO-36 L99PM62XP L99PM62XPTR

Applications
■ Automotive ECU's such as door zone and body
control modules

September 2013 Doc ID 16363 Rev 4 1/98

www.st.com 1
Contents L99PM62XP

Contents

1 Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2 Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.3 Increased output current capability for voltage regulator V2 . . . . . . . . . 13
2.1.4 Voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.5 Voltage regulator behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.2 Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.3 V1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.4 VBAT standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.5 Wake up from standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.6 Wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.7 Cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.8 Timer interrupt / wake-up of microcontroller by timer . . . . . . . . . . . . . . . 19
2.3 Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 Configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.1 Change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Fail safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.1 Single failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.6 Reset output (NRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.7 Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.8 LIN bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.8.1 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.8.2 Wake up (from LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.8.3 LIN pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.9 High speed CAN bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.9.1 CAN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.9.2 Wake up (from CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.9.3 CAN sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2/98 Doc ID 16363 Rev 4

L99PM62XP Contents

2.9.4 CAN receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.9.5 CAN looping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.10 Serial peripheral interface (ST SPI standard) . . . . . . . . . . . . . . . . . . . . . . 33

3 Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.1 Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.1 Vs overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.2 Vs undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 37
3.3 High-side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4 Low-side driver outputs REL1, REL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5 SPI diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4 Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.4.1 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.5.1 Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.5.3 Power-on reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.5.4 Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.5.5 Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.5.6 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.5.7 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.5.8 High-side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.5.9 Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.5.10 Wake up inputs (WU1... WU3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.5.11 High speed CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.5.12 LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.5.13 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.5.14 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Doc ID 16363 Rev 4 3/98

Contents L99PM62XP

5.5.15 Inputs TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . 62

6 ST SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1 SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1.2 Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1.3 Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1.4 Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1.5 Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.6 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.7 Format of data shifted out at SDO during write cycle . . . . . . . . . . . . . . 70
6.1.8 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.1.9 Format of data shifted out at SDO during read cycle . . . . . . . . . . . . . . . 72
6.1.10 Read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.11 Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.2.2 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2.3 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

7 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

7.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

4/98 Doc ID 16363 Rev 4

L99PM62XP List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3. Wake up sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4. Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5. Fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6. Persisting fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7. Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 8. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 9. Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 10. Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 11. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 12. Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 13. Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 14. Power-on reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 15. Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 16. Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 17. Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 18. Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 19. Output (OUT_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 20. Outputs (OUT1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 21. Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 22. Wake up inputs (WU1... WU3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 23. CAN transmit data input: pin TXDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 24. CAN receive data output: pin RXDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 25. CAN bus common mode stabilization output termination: pin SPLIT . . . . . . . . . . . . . . . . . 54
Table 26. CAN transmitter and receiver: pins CANH and CANL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 27. CAN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 28. LIN transmit data input: pin TXD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 29. LIN receive data output: pin RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 30. LIN transmitter and receiver: pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 31. LIN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32. LIN pull-up: pin LINPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 33. Operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 34. Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 35. Input CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 36. DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 37. DO output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 38. DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 39. CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 40. Inputs TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 41. Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 42. Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 43. Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 44. Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 45. Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 46. Write command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 47. Write command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 48. Write command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Doc ID 16363 Rev 4 5/98

List of tables L99PM62XP

Table 49. Format of data shifted out at SDO during write cycle: global status register . . . . . . . . . . . 70
Table 50. Format of data shifted out at SDO during write cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 70
Table 51. Format of data shifted out at SDO during write cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 70
Table 52. Read command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 53. Read command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 54. Read command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 55. Format of data shifted out at SDO during read cycle: global status register. . . . . . . . . . . . 72
Table 56. Format of data shifted out at SDO during read cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 72
Table 57. Format of data shifted out at SDO during read cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 72
Table 58. Read and clear status command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 59. Read and clear status command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 60. Read and clear status command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 61. Format of data shifted out at SDO during read and clear status: global status register . . . 73
Table 62. Format of data shifted out at SDO during read and clear status: data byte 1. . . . . . . . . . . 73
Table 63. Format of data shifted out at SDO during read and clear status: data byte 2. . . . . . . . . . . 73
Table 64. Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 65. ID-header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 66. Family identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 67. Silicon version identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 68. SPI-frame-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 69. SPI register: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 70. SPI register: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 71. SPI register: CTRL register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 72. SPI register: STAT register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 73. Overview of control registers data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 74. Control register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 75. Control register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 76. Control register 1, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 77. Control register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 78. Control register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 79. Control register 2, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 80. Control register 3: command data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 81. Control register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 82. Control register 3, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 83. Control register 4: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 84. Control register 4, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 85. Control register 4, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 86. Control register 5: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 87. Control register 5, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 88. Control register 5, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 89. Control register 6: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 90. Control register 6, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 91. Control register 6, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 92. Overview of status register data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 93. Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 94. Status register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 95. Status register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 96. Status register 1, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 97. Status register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 98. Status register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 99. Status register 2, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 100. Status register 3: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6/98 Doc ID 16363 Rev 4

L99PM62XP List of tables

Table 101. Status register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 102. Status register 3, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 103. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 104. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Doc ID 16363 Rev 4 7/98

List of figures L99PM62XP

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. Voltage source with external PNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. Voltage source with external PNP and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Voltage source with external NPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Voltage source with external NPN and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Voltage regulator behaviour and diagnosis during supply voltage ramp-up / ramp-down
conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Watchdog in Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Change watchdog timing within long open window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Change watchdog timing within window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. General procedure to change watchdog timing out of fail safe mode. . . . . . . . . . . . . . . . . 25
Figure 15. Change watchdog timing out of fail safe mode (watchdog failure) . . . . . . . . . . . . . . . . . . . 25
Figure 16. Example: exit fail safe mode from watchdog failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 17. LIN master node configuration using LIN_PU (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. CAN wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Over voltage and under voltage protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 21. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. PowerSSO-36 thermal resistance junction to ambient vs PCB copper area (V1 ON) . . . . 44
Figure 24. PowerSSO-36 Thermal Impedance junction to ambient vs PCB copper area (single
pulse with V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25. PowerSSO-36 thermal fitting model (V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 26. Watchdog timing (long, early, late and safe window) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 27. Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 28. LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 29. SPI – transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 30. SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 31. SPI output timing (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 32. SPI output timing (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 33. SPI – CSN low to high transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 65
Figure 34. Read configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 35. Write configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 36. Format of data shifted out at SDO during write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 37. Format of data shifted out at SDO during read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 38. Format of data shifted out at SDO during read and clear status operation . . . . . . . . . . . . 74
Figure 39. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8/98 Doc ID 16363 Rev 4

L99PM62XP Block diagram and pin descriptions

1 Block diagram and pin descriptions

Figure 1. Block diagram

9V

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P$ 5(/
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Doc ID 16363 Rev 4 9/98

Block diagram and pin descriptions L99PM62XP

Table 2. Pin definition

Pin Symbol Function

1 AGND Analog ground

2 RxDC CAN receive data output
3 TxDC CAN transmit data input
4 CANH CAN high level voltage I/O
5 CANL CAN low level voltage I/O
6 SPLIT CAN reference voltage output, CAN termination
7 CANSUP CAN supply input; to allow external CAN supply from V1 or V2 regulator.
8 NRESET Nreset output to micro controller; Internal pull-up of typ. 100 KΩ (reset state = LOW)
9 V1 Voltage regulator 1 output: 5 V supply e.g. micro controller, CAN transceiver
Voltage regulator 2 output: 5 V supply for external loads (IR receiver, potentiometer,
10 V2
sensors) or CAN Transceiver. V2 is protected against reverse supply.
11 TxDL LIN Transmit data input
RxDL -> LIN receive data output
12 RxDL/NINT NINT -> indicates local/remote wake-up events or provides a programmable timer
interrupt signal
13 OP2+ Non inverting input of operational amplifier 2
14 OP2- Inverting input of operational amplifier 2
15 OP2_OUT Output of operational amplifier 2
16 DI SPI: serial data input
17 DO SPI: serial data output
18 CLK SPI: serial clock input
19 CSN SPI: chip select not input
20…22 WU1…3 Wake-up Inputs 1to 3: Input pins for static or cyclic monitoring of external contacts
23 OP1_OUT Output of operational amplifier 1
24 OP1- Inverting input of operational amplifier 1
25 OP1+ Non inverting input of operational amplifier 1
26 OUT4 High-side driver output (7 Ω, typ)
27 OUT3/FSO Configurable as high-side driver output (7 Ω, typ) or fail safe output pin (default)
28 OUT2 High-side driver output (7 Ω, typ)
29 OUT1 High-side driver output (7 Ω, typ)
30 OUT_HS High-side driver (1 Ω, typ)
31 VS Power supply voltage
32 LINPU High-side driver output to switch off LIN master pull up resistor
33 LIN LIN bus line
34 REL1 Low-side driver output (2 Ω typ)

10/98 Doc ID 16363 Rev 4

L99PM62XP Block diagram and pin descriptions

Table 2. Pin definition (continued)

Pin Symbol Function

35 REL2 Low-side driver output (2 Ω typ)

36 PGND Power ground (REL1/2, LIN and CAN GND), to be externally connected to AGND

Figure 2. Pin connection (top view)

$*1'   3*1'
5['&   5(/
7['&   5(/
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233   230
230   23287
23287   :8
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Note: It is recommended to connect the PGND pin directly to the TAB.

Doc ID 16363 Rev 4 11/98

Description L99PM62XP

2 Description

2.1 Voltage regulators

The L99PM62XP contains 2 independent and fully protected low drop voltage regulators,
which are designed for very fast transient response and do not require electrolytic output
capacitors for stability.
The output voltage is stable with ceramic load capacitors > 220 nF.

2.1.1 Voltage regulator: V1

The V1 voltage regulator provides 5 V supply voltage and up to 250 mA continuous load
current and is mainly intended for supply of the system microcontroller. The V1 regulator is
embedded in the power management and fail-safe functionality of the device and operates
according to the selected operating mode.
It can be used to supply the internal HS CAN Transceiver via the CANSUP pin externally. In
case of a short circuit condition on the CAN bus, the output current of the transmitter is
limited to 100 mA and the transceiver is turned off in order to ensure continued supply of the
microcontroller.
In addition the regulator V1 drives the L99PM62XP internal 5 V loads. The voltage regulator
is protected against overload and overtemperature. An external reverse current protection
has to be provided by the application circuitry to prevent the input capacitor from being
discharged by negative transients or low input voltage. The output voltage precision is better
than +/- 2% (incl. temperature drift and line-/load regulation) in active mode; respectively
+/- 3% during low current operation (i. e. in V1 standby mode). Current limitation of the
regulator ensures fast charge of external bypass capacitors. The output voltage is stable for
ceramic load capacitors > 220 nF.
If the device temperature exceeds the TSD1 threshold, all outputs (OUTx, RELx, V2, LIN) is
deactivated except V1. Hence the micro controller has the possibility for interaction or error
logging. In case of exceeding TSD2 threshold (TSD2>TSD1), also V1 is deactivated (see
state chart in Chapter 3: Protection and diagnosis). A timer is started and the voltage
regulator is deactivated for tTSD = 1sec. During this time, all other wakeup sources (CAN,
LIN, WU1 to3 and wake up of µC by timer) are disabled. After 1 sec, the voltage regulator
tries to restart automatically. If the restart fails 7 times, within one minute, without clearing
and thermal shutdown condition still exists, the L99PM62XP enters the forced VBAT standby
Mode.
In case of short to GND at “V1” after initial turn on (V1 < 2V for at least 4ms) the L99PM62XP
enters the forced VBAT standby Mode. Reactivation (wake-up) of the device can be achieved
with signals from CAN, LIN, WU1..3 or periodic wake by timer (see Section 2.2.8: Timer
interrupt / wake-up of microcontroller by timer ).

2.1.2 Voltage regulator: V2

The voltage regulator V2 can supply additional 5 V loads (e.g. logic components or the
integrated HS CAN transceiver or external loads such as sensors or potentiometers). The

12/98 Doc ID 16363 Rev 4

L99PM62XP Description

maximum continuous load current is 100 mA. The regulator provides accuracy better than
+ 3% at 50 mA (4 % at 100 mA and is protected against.
● Overload
● Overtemperature
● Short circuit (short to ground and battery supply voltage)
● Reverse biasing

2.1.3 Increased output current capability for voltage regulator V2

For applications which require high output currents, the output current capability of the
regulator can be increased my means of the integrated operational amplifiers and an
external pass transistor.

Figure 3. Voltage source with external PNP

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9

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Figure 4. Voltage source with external PNP and current limitation

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Figure 3 shows a possible configuration with a PNP pass element using voltage regulator 2
to provide the voltage reference for the regulated output voltage V3.

Doc ID 16363 Rev 4 13/98

Description L99PM62XP

The Vs operating range for this circuit is 5.5 V to 18 V. It is important the respect the input
common mode range specified for the operational amplifiers.
The output voltage V3 can be calculated using the following formula:
v2 R1 + R2
v 3 = ------ ⋅ --------------------- [ V ]
2 R2

The circuit in Figure 4 provides additional current limitation using an additional PNP
transistor and R6 which allows setting the current limit.

Figure 5. Voltage source with external NPN

/30

9 9V

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5


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Figure 6. Voltage source with external NPN and current limitation

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Figure 5 shows a possible configuration with an NPN pass element using voltage regulator
2 to provide the voltage reference for the regulated output voltage V3. This circuit requires
fewer components compared to the configuration in Figure 3 but has a limited Vs operating
range (6 V to 18 V).

14/98 Doc ID 16363 Rev 4

L99PM62XP Description

The output voltage V3 can be calculated using the following formula:

v2 R1 + R2
v 3 = ------ ⋅ --------------------- [ V ]
2 R2

The circuit in Figure 6 provides additional current limitation using an additional NPN
transistor and R5 which allows setting the current limit.
Alternatively, voltage regulator 1 can be used to provide the 5 V reference for this topology.
However, the additional current consumption through R3 and R4 has to be considered in
V1standby mode.

2.1.4 Voltage regulator failure

The V1, and V2 regulator output voltages are monitored.
In case of a drop below the V1, V2 – fail thresholds (V1,2 < 2 V, typ for t > 2 µs), the V1,2-fail
bits are latched. The fail bits can be cleared by a dedicated SPI command.

Short to ground detection

If 4 ms after turn on of the regulator the V1,2 voltage is below the V1,2 fail thresholds,
(independent for V1,2), the L99PM62XP identifies a short circuit condition at the related
regulator output and the regulator is switched off.
In case of V1 short to GND failure the device enters VBAT standby mode automatically. Bits
Forced VBAT STD2/SHTV1 and V1 fail were set.
In case of a V2 short to GND failure the V2short and V2 fail bit is set.
If the output voltage of the corresponding regulator once exceeded the V1,2 fail thresholds
the short to ground detection is disabled. If a short to ground condition occurs the regulator
outputs switches off due to thermal shutdown (V1 at TSD2; V2 at TSD1).

Doc ID 16363 Rev 4 15/98

Description L99PM62XP

2.1.5 Voltage regulator behaviour

Figure 7. Voltage regulator behaviour and diagnosis during supply voltage ramp-up / ramp-
down conditions
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2.2 Operating modes

The L99PM62XP can be operated in 4 different operating modes:
● Active
● Flash
● V1 standby
● VBAT standby
A cyclic monitoring of wake-up inputs and a periodic interrupt/wake-up by timer is available
in standby modes.

2.2.1 Active mode

All functions are available and the device is controlled by the ST SPI Interface.

2.2.2 Flash mode

To program the system microcontroller, the L99PM62 can be operated in Flash mode where
the internal watchdog is disabled. This mode can also be used for software debugging.

16/98 Doc ID 16363 Rev 4

L99PM62XP Description

Except for the disabled watchdog, the Flash mode is identical to active mode and all device
features are available.
The mode can be entered if one of the following conditions is applied:
● VTxDL > VFlash
● VTxDC > VFlash
At exit from Flash mode (VTxD < VFlash) no NReset pulse is generated and the watchdog
starts with a long open window.
Note: Setting both TxDL and TxDC to high voltage levels (> VFlash) is not allowed

2.2.3 V1 standby mode

The transition from active mode to V1 standby mode is controlled by SPI.
To supply the micro controller in a low power mode, the voltage regulator 1 (V1) remains
active. In order to reduce the current consumption, the regulator goes in low current mode
as soon as the supply current of the microcontroller goes below the Icmp current threshold.
At this transition, the L99PM62 also deactivates the internal watchdog.
Relay outputs, LIN and CAN transmitters is switched off in V1 standby mode. High-side
outputs and the V2 regulator remain in the configuration programmed prior to the standby
command.
A cyclic supply of external contacts and a synchronized monitoring of the contact state can
be activated and configured by SPI.
In V1 standby mode various wake up sources can be individually programmed. Each wake
up event puts the device into active mode and forces the RxDL/NINT pin to a low level
indicating the wake-up condition to the microcontroller.
After power ON reset (POR) all wake up sources are activated by default except the
periodic interrupt/wake timer.
With the interrupt timer the micro controller can be forced from ‘stop’ to ‘run’ after a
programmable period. The RxDL/NINT pin is forced low after the timer is elapsed. The
L99PM62XP enters active mode and is awaiting a valid watchdog trigger.
Both internal timers can be used for this feature.
The interrupt timer (TINT) at pin RxDL/NINT is only available in V1 standby mode.
Note: Inputs TxDL, TxDC and CSN must be at high level or at high impedance in order to achieve
minimum standby current in V1 standby mode.
Inputs DI and CLK must be at GND or at high impedance to achieve minimum standby
current in V1 standby mode.

Interrupt
The interrupt signal (linked to RxDL/NINT internally) indicates a wake-up event from V1
standby mode. In case of a wake-up by Wake-up Inputs, activity on LIN or CAN, SPI access
or timer-interrupt the NINT pin is pulled low for 56 µs.
In case of V1 standby mode and (IV1 > Icmp), the device remains in standby mode, the V1
regulator switches to high current mode and the watchdog starts. No Interrupt signal is
generated.

Doc ID 16363 Rev 4 17/98

Description L99PM62XP

2.2.4 VBAT standby mode

The transition from active mode to VBAT standby mode is initiated by an SPI command.
In VBAT standby mode, the V1 voltage regulator, relay outputs, LIN and CAN transmitters are
switched off. High-side outputs and the V2 regulator remain in the configuration
programmed prior to the standby command.
In VBAT standby mode the current consumption of the L99PM62XP is reduced to a minimum
level.
Note: Inputs TXDL, TXDC and CSN must be terminated to GND in VBAT standby to achieve
minimum standby current.
This can be achieved with the internal ESD protection diodes of the microcontroller
(microcontroller is not supplied in this mode; V1 is pulled to GND).

2.2.5 Wake up from standby modes

A wake-up from standby mode switches the device to active mode. This can be initiated by
one or more of the following events:

Table 3. Wake up sources

Wake up source Description

LIN bus activity Can be disabled by SPI

CAN bus activity Can be disabled by SPI
Level change of WU1 - 3 Can be individually configured or disabled by SPI
Device remains in V1 standby mode but watchdog is enabled (If
IV1 > Icmp Icmp = 0) and the V1 regulator goes into high current mode (increased
current consumption). No interrupt is generated.
Programmable by SPI
– V1 standby mode: device wakes up and Interrupt signal is generated
Timer interrupt / wake up
at RxDL/NINT when programmable timeout has elapsed
of µC by TIMER
– VBAT standby mode: device wakes up, V1 regulator is turned on and
NReset signal is generated when programmable timeout has elapsed
Always active (except in VBAT standby mode)
SPI access
Wake up event: CSN is low and first rising edge on CLK

To prevent the system from a deadlock condition (no wake up possible) a configuration
where the periodic timer interrupt and wake up by LIN and HS CAN are disabled, is not
allowed. The default configuration is entered for all wake-up sources in case of such an
invalid setting.
All wake-up events from V1 standby mode (except IV1 > Icmp) are indicated to the
microcontroller by a low-pulse at RxDL/NINT (duration: 56 µs).
Wake-up from V1 standby by SPI Access might be used to check the interrupt service
handler.

18/98 Doc ID 16363 Rev 4

L99PM62XP Description

2.2.6 Wake-up inputs

The de-bounced digital inputs WU1 to WU3 can be used to wake up the L99PM62XP from
standby modes. These inputs are sensitive to any level transition (positive and negative
edge)
For static contact monitoring, a filter time of 64 µs is implemented at WU1-3. The filter is
started when the input voltage passes the specified threshold.
In addition to the continuous sensing (static contact monitoring) at the wake up inputs, a
cyclic sense functionality is implemented. This feature allows periodical activation of the
wake-up inputs to read the status of the external contacts. The periodical activation can be
linked to Timer1 or Timer2 (see Section 2.2.7: Cyclic contact supply ). The input signal is
filtered with a filter time of 16 µs after a programmable delay (80 µs or 800 µs) according to
the configured timer on-time. A wake-up is processed if the status has changed versus the
previous cycle.
The outputs OUT_HS and OUT1-4 can be used to supply the external contacts with the
timer setting according to the cyclic monitoring of the wake-up inputs.
If the wake-up inputs are configured for cyclic sense mode the input filter timing and input
filter delay (WUx_filt in control register 2) must correspond to the setting of the high-side
output which supplies the external contact switches (OUTx in control register 0).
In standby mode, the inputs WU1-3 are SPI configurable for pull-up or pull-down current
source configuration according to the setup of the external. In active mode the inputs have a
pull down resistor.
In active mode, the input status can be read by SPI (Status Register 2). Static sense should
be configured (Control Register 2) before the read operation is started (In cyclic sense
configuration, the input status is updated according to the cyclic sense timing; Therefore,
reading the input status in this mode may not reflect the actual status).

2.2.7 Cyclic contact supply

In V1 standby and VBAT standby modes, any high-side driver output (OUT1..4, OUTHS) can
be used to periodically supply external contacts.
The timing is selectable by SPI
Timer 1: period is Xs. The on-time is 10 ms resp. 20 ms: With X ∈ {1, 2, 3, 4 s}
Timer 2: period is X ms. The on- time is 100 µs resp. 1ms: With X ∈ {10, 20, 50, 200 ms}

2.2.8 Timer interrupt / wake-up of microcontroller by timer

During standby modes the cyclic wake up feature, configured via SPI, allows waking up the
µC after a programmable timeout according to timer1 or timer2.
From V1 standby mode, the L99PM62XP wakes up (after the selected timer has elapsed)
and sends an interrupt signal (via RxDL/NINT pin) to the µC. The device enters active mode
and the watchdog is started with a long open window. The microcontroller can send the
device back into V1 standby after finishing its tasks.
From VBAT standby mode, the L99PM62XP wakes up (after the selected timer has elapsed),
turns on the V1 regulator and provides an NReset signal to the µC. The device enters active
mode and the watchdog is started with a long open window. The microcontroller can send
the device back into VBAT standby after finishing its tasks.

Doc ID 16363 Rev 4 19/98

Description L99PM62XP

2.3 Functional overview (truth table)

Table 4. Functional overview (truth table)

Operating modes

Function Comments V1-standby VBAT-standby

Active mode static mode static mode
(cyclic sense) (cyclic sense)

Voltage-regulator, V1 VOUT = 5 V On On(1) Off

Voltage-regulator, V2 VOUT = 5 V On/ Off (2) On(2) / Off On(2) / Off
Reset-generator On On Off
Off (On: I_V1 > Icmp-
Window watchdog V1 monitor On Off
threshold and Icmp = 0)
Wake up Off Active(3) Active(3)
Oscillator time
HS-cyclic supply On / Off On(2) / Off On(2) / Off
base
Relay driver On Off Off
Operational amplifiers On Off Off

LIN LIN 2.1 On Off(4) Off(4)

HS_CAN On Off(4) Off(4)

FSO (if configured by Fail safe
OUT3/FSO Off(5) OUT3/FSO Off(5) OUT3/FSO Off(5)
SPI), active by default output
Oscillator On (6) (6)

Vs-monitor On (7) (7)

1. Supply the processor in low current mode.

2. Only active when selected via SPI.
3. Unless disabled by SPI.
4. The bus state is internally stored when going to standby mode. A change of bus state leads a wake-up after exceeding of
internal filter time (if wake-up by LIN or CAN is not disabled by SPI).
5. ON in fail-safe condition: If Standby mode is entered with active Fail Safe mode, the output remains ON in Standby mode.
6. Activation = ON if cyclic sense is selected.
7. cyclic activation = pulsed ON during cyclic sense.

20/98 Doc ID 16363 Rev 4

L99PM62XP Description

Figure 8. Operating modes

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2.4 Configurable window watchdog

During normal operation, the watchdog monitors the micro controller within a programmable
trigger cycle: (10 ms, 50 ms, 100 ms, 200 ms)
In VBAT standby and Flash program modes, the watchdog circuit is automatically disabled.
In V1 standby mode a wake up by timer is programmable in order to wake up the µC (see
Section 2.2.8: Timer interrupt / wake-up of microcontroller by timer). After wake-up, the
watchdog starts with a long open window. After serving the watchdog, the µC may send the
device back to V1 standby mode.

Doc ID 16363 Rev 4 21/98

Description L99PM62XP

After power-on or standby mode, the watchdog is started with a long open window (65 ms
nominal). The long open window allows the micro controller to run its own setup and then to
trigger the watchdog via the SPI. The trigger is processed when the CSN input becomes
HIGH after the transmission of the SPI word.
Writing ‘1’ to the watchdog trigger bit terminates the long open window and start the window
watchdog (the timing is programmable by SPI). Subsequently, the micro controller has to
serve the watchdog by alternating the watchdog trigger bit within the safe trigger area (refer
to Figure 27). A correct watchdog trigger signal is immediately start the next cycle.
After 8 watchdog failures in sequence, the V1 regulator is switched off for 200ms. If
subsequently, 7 additional watchdog failures occur, the V1 regulator is completely turned off
and the device goes into VBAT standby mode until a wakeup occurs.
In case of a watchdog failure, the outputs (RELx, OUTx, V2) are switched off and the device
enters fail-safe mode (i. e. all control registers are set to default values except the ‘OUT3
control bit’).
The following diagrams illustrate the watchdog behavior of the L99PM62. The diagrams are
split into 3 parts. First diagram shows the functional behavior of the watchdog without any
error. The second diagram covers the behavior covering all the error conditions, which can
affect the watchdog behavior. Third diagram shows the transition in and out of Flash mode.
All 3 diagrams can be overlapped to get all the possible state transitions under all
circumstances. For a better readability, they were split in normal operating, operating with
errors and Flash mode.

Figure 9. Watchdog in normal operating mode (no errors)

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22/98 Doc ID 16363 Rev 4

L99PM62XP Description

Figure 10. Watchdog with error conditions

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Figure 11. Watchdog in Flash mode

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2.4.1 Change watchdog timing

There are 4 programmable watchdog timings available, which represent the nominal trigger
time in window mode. To change the watchdog timing, a new timing has to be written by
SPI. The new timing gets active with the next valid watchdog trigger. The following figures
illustrate the sequence, which is recommended to use, changing the timing within long open
window and within window mode.

Doc ID 16363 Rev 4 23/98

Description L99PM62XP

Figure 12. Change watchdog timing within long open window

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Figure 13. Change watchdog timing within window mode

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If the device is in fail-safe mode, the control registers are locked for writing. To change the
watchdog timing out of fail-safe mode, first the fail-safe condition must be solved, respective
confirmed from the microcontroller. Afterwards the new watchdog timing can be
programmed using the sequence from Figure 14. Since the actions to remove, a fail-safe
condition can differ from the root cause of the fail safe the following diagram shows the
general procedure how to change the watchdog timing out of fail-safe mode. Figure 15
shows the procedure to change watchdog timing with a previous watchdog failure, since this
is a special fail-safe scenario.

24/98 Doc ID 16363 Rev 4

L99PM62XP Description

Figure 14. General procedure to change watchdog timing out of fail safe mode
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Figure 15. Change watchdog timing out of fail safe mode (watchdog failure)
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2.5 Fail safe mode

2.5.1 Single failures

L99PM62XP enters fail safe mode in case of:
● Watchdog failure
● V1 turn on failure
– V1 short (V1 < V1fail for t > 4 ms)
● V1 undervoltage (V1 < Vrth for t > 8 µs)
● Thermal shutdown TSD2
● SPI failure
– DI stuck to GND or VCC (SPI frame = ’00 00 00’ or ‘FF FF FF’

Doc ID 16363 Rev 4 25/98

Description L99PM62XP

The fail safe functionality is also available in V1 standby mode. During V1 standby mode the
fails safe mode is entered in the following cases:
● V1 undervoltage (V1 < Vrth for t > 8 µs)
● Watchdog failure (if watchdog still running due to IV1 > Icmp)
● Thermal shutdown TSD2
In fail safe mode the L99PM62 returns to a default. The fail safe condition is indicated to the
remaining system in the global status register. The conditions during fails safe mode are:
● All outputs are turned off
● All control registers are set to default values (except OUT3/FSO configuration)
● Write operations to control registers are blocked until the fail safe condition is cleared
(see Table 5)
● LIN and HS CAN transmitter, OpAmps and SPI remain on
● Corresponding failure bits in status registers are set.
● FSO Bit (Bit 0 global status register) is set
● OUT3/FSO is activated if configured as fail safe output
If OUT3 is configured as FSO, the internal fail safe mode can be monitored at OUT3 (high-
side driver is turned on in fail-safe mode). Self protection features for OUT3 when
configured as FSO are active (see Section 3.3: High-side driver outputs ).
OUT3 is configured as fail safe output by default. It can be configured to normal high-side
driver operation by SPI. It this case, the configuration remains until Vs power on.
If the fail safe mode was entered it keeps active until the fail safe condition is removed and
the fail safe was read by spi. depending on the root cause of the fail safe operation, the
actions to exit fail safe mode are as shown in the following table.

Table 5. Fail safe conditions and exit modes

Failure source Failure condition Diagnosis Exit from fail-safe mode

Watchdog early write Fail-safe = 1 TRIG = 1 during LOWi and

µC (oscillator)
failure or expired window WDfail = n+1 read fail-safe bit

Fail-safe = 1
Short at turn-on Read&Clear SR3 after wake
Forced Sleep TSD2/SHTV1 = 1
V1
Fail-safe = 1 V1 > Vrth
Undervoltage
V1fail = 1(1) Read Fail-safe bit
Fail-safe = 1
TW = 1 Tj < TSD2
Temperature Tj > TSD2
TSD1 = 1 Read&Clear SR3
TSD2 = 1

SPI DI short to GND or VCC Fail-safe = 1 Valid SPI command

1. if V1 < V1fail (for t >2µs)

The fail-safe bit is located in the global status register (Bit 0)
multiple failures – entering forced VBAT standby mode

If the fail-safe condition persists and all attempts to return to normal system operation fail,
the L99PM62 enters the forced VBAT standby mode in order to prevent damage to the

26/98 Doc ID 16363 Rev 4

L99PM62XP Description

system. The forced VBAT standby mode can be terminated by any regular wake-up event.
The root cause of the forced VBAT standby is indicated in the SPI status registers
The forced VBAT standby mode is entered in case of:
● Multiple watchdog failures: forced sleep WD = 1 (15x watchdog failure)
● Multiple thermal shutdown 2: forced sleep TSD2/SHTV1 = 1 (7x TSD2)
● V1 short at turn-on: forced sleep TSD2/SHTV1 = 1 (V1 < V1fail for t > 4 ms)

Table 6. Persisting fail safe conditions and exit modes

Failure source Failure condition Diagnosis Exit from fail-safe mode

Wake-up
15 consecutive Fail-safe = 1
µC (oscillator) TRIG = 1 during LOWi
watchdog failures ForcedSleepWD = 1
read & clear SR3
Fail-safe = 1
V1 short at turn-on Read&clear SR3 after wake-up
ForcedSleepTSD2/SHTV1 = 1
Fail-safe = 1
TW = 1
Temperature 7 times TSD2 TSD1 = 1 Read&clear SR3 after wake-up
TSD2 = 1
ForcedSleepTSD2/SHTV1 = 1

Figure 16. Example: exit fail safe mode from watchdog failure

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Doc ID 16363 Rev 4 27/98

Description L99PM62XP

2.6 Reset output (NRESET)

If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output
“NRESET” is pulled up by internal pull up resistor to V1 voltage after a 2 ms reset delay time.
This is necessary for a defined start of the micro controller when the application is switched
on. Since the NRESET output is realized as an open drain output it is also possible to
connect an external NRESET open drain NRESET source to the output. It must be
considered that as soon the NRESET is released from the L99PM62 the Watchdog timing
starts.
A reset pulse (2 ms) is generated in case of:
● V1 drops below Vrth (configurable by SPI) for more than 8 µs
● Watchdog failure
Note: An external pull-up resistor (1kΩ) to V1 is recommended in order to ensure ILOAD1 > Icmp
during reset condition

2.7 Operational amplifiers

The operational amplifiers are especially designed to be used for sensing and amplifying the
voltage drop across ground connected shunt resistors. Therefore the input common mode
range includes -0.2 V to 3 V.
The operational amplifiers are designed for -0.2 V to +3 V input voltage swing and rail-to-rail
output voltage range.
All pins (positive, negative and outputs) are available to be able to operate in non-inverting
and inverting mode. Both operational amplifiers are on-chip compensated for stability over
the whole operating range within the defined load impedance.
The operational amplifiers may also be used to setup an additional high current voltage
source with an external pass element. Refer to Section 2.1.3 for a detailed description.

2.8 LIN bus interface

Features:
● Speed communication up to 20 kbit/s.
● LIN 2.1 compliant (SAEJ2602 compatible) transceiver.
● Function range from +40 V to -18 V DC at LIN pin.
● GND disconnection fail safe at module level.
● Off mode: does not disturb network.
● GND shift operation at system level.
● Micro controller Interface with CMOS compatible I/O pins.
● Internal pull up resistor.
● Internal high-side switch to disconnect master pull-up resistor in case of short circuit of
bus signal.
● ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2.
● Matched output slopes and propagation delay.

28/98 Doc ID 16363 Rev 4

L99PM62XP Description

In order to further reduce the current consumption in standby mode, the integrated LIN bus
interface offers an ultra low current consumption.
Note: Use of master pull-up switch is optional.

2.8.1 Error handling

The L99PM62XP provides the following 3 error handling features which are not described in
the LIN Spec. V2.1, but are realized in different stand alone LIN transceivers / micro
controllers to switch the application back to normal operation mode.

Dominant TxDL time out

If TXDL is in dominant state (low) for more than 12 ms (typ) the transmitter is disabled, the
status bit is latched and can be read and optionally cleared by SPI. The transmitter remains
disabled until the status register is cleared. This feature can be disabled via SPI.

Permanent recessive
If TXDL changes to dominant (low) state but RXDL signal does not follow within 40 µs the
transmitter is disabled, the status bit is latched and can be read and optionally cleared by
SPI. The transmitter remains disabled until the status register is cleared.

Permanent dominant
If the bus state is dominant (low) for more than 12 ms a permanent dominant status is
detected. The status bit is latched and can be read and optionally cleared by SPI. The
transmitter is not disabled.

2.8.2 Wake up (from LIN)

In standby mode the L99PM62XP can receive a wake up from LIN bus. For the wake up
feature the L99PM62XP logic differentiates two different conditions.

Normal wake up
Normal wake up can occur when the LIN transceiver was set in standby mode while LIN
was in recessive (high) state. A dominant level at LIN for tlinbus, switches the L99PM62XP to
active mode.

Wake up from short to GND condition

If the LIN transceiver was set in standby mode while LIN was in dominant (low) state,
recessive level at LIN for tlinbus, switches the L99PM62XP to active mode.
Note: A wake up caused by a message on the bus starts the voltage regulator and the
microcontroller to switch the application back to normal operation mode.

2.8.3 LIN pull-up

The master node pull-up resistor (1 kΩ) can be connected to Vs using the internal LIN_PU
high-side switch. This high-side switch can be controlled by SPI in order to allow
disconnection of the pull-up resistor in case of LIN bus short to GND conditions.

Doc ID 16363 Rev 4 29/98

Description L99PM62XP

Figure 17. LIN master node configuration using LIN_PU (optional)

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LIN_PU high-side driver characteristics:

● Activated by default and can be turned off by SPI command (CR4).
● Remains active in standby modes.
● Switch off only in case of over temperature (TSD2 = thermal shutdown #2).
● No over current protection.
● Typical RDSon, 10 Ω.

2.9 High speed CAN bus transceiver

General requirements
● Speed communication up to 1 Mbit/s.
● ISO 11898-2 and ISO 11898-5 compliant
● SAE J2284 compliant
● Function range from +40 V to -27 V DC at CAN pins.
● GND disconnection fail safe at module level.
● GND shift operation at system level.
● Micro controller Interface with CMOS compatible I/O pins.
● ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
● Matched output slopes and propagation delay
● Split output pin for stabilizing the recessive bus level
● Receive-only mode available
In order to further reduce the current consumption in standby mode, the integrated CAN bus
interface offers an ultra low current consumption.

30/98 Doc ID 16363 Rev 4

L99PM62XP Description

2.9.1 CAN error handling

The L99PM62XP provides the following 4 error handling features which are not described in
the ISO 11898-2/ISO 11898-5, but are realized in different stand alone CAN transceivers /
micro controllers to switch the application back to normal operation mode.

Dominant TxDC time out

If TXDC is in dominant state (low) for t > tdom(TxD) the transmitter is disabled, status bit is
latched and can be read and optionally cleared by SPI. The transmitter remains disabled
until the status register is cleared.

CAN permanent recessive

If TXDC changes to dominant (low) state but CAN bus does not follow for 4 times, the
transmitter is disabled, status bit is latched and can be read and optionally cleared by SPI.
The transmitter remains disabled until the status register is cleared.

CAN permanent dominant

If the bus state is dominant (low) for t > tCAN a permanent dominant status is detected. The
status bit is latched and can be read and optionally cleared by SPI. The transmitter is not
disabled.

RXDC permanent recessive

If RXDC pin is clamped to recessive (high) state, the controller is not able to recognize a bus
dominant state and could start messages at any time, which results in disturbing the overall
bus communication. Therefore, if RXDC does not follow TXDC for 4 times the transmitter is
disabled. The status bit is latched and can be read and optionally cleared by SPI. The
transmitter remains disabled until the status register is cleared.

2.9.2 Wake up (from CAN)

When the L99PM62XP is in standby mode with CAN wake up option enabled, the CAN bus
traffic is detected. For the wake up feature the L99PM62XP logic differentiates different
conditions. During V1 Standby mode RXDC output is kept at recessive level. Independent
from the wakeup pattern selected and independent from the previous Standby mode, the
RXDC reflect immediately the bus state after the wakeup. This feature allows
implementation of a ‘partial networking’ functionality controlled by the system
microcontroller.

Normal pattern wake up

Normal pattern wake up can occur when CAN pattern wake up option is enabled and the
CAN transceiver was set in standby mode while CAN bus was in recessive (high) state or
dominant (low) state. In order to wake up the L99PM62XP, the following criteria must be
fulfilled:
● The CAN interface wake-up receiver must receive a series of two consecutive valid
dominant pulses, each of which must be longer than 2 µs
● The distance between 2 pulses must be longer than 2 µs.
● The two pulses must occur within a time frame of 1.0 ms

Doc ID 16363 Rev 4 31/98

Description L99PM62XP

Wake up from short to GND condition

Even if CAN pattern wake up option is enabled, but the CAN transceiver was set in standby
mode after a qualified permanent dominant state, recessive level at CAN, switches the
L99PM62XP to active mode.

No pattern wake up
If the CAN pattern wake up option is disabled, any transition either dominant (low) state to
recessive (high) state or recessive (high) state to dominant (low) state switches the
L99PM62XP to active mode (after a filtering time of 2 µs).
Note: A wake up caused by a message on the bus starts the voltage regulator and the
microcontroller to switch the application back to normal operation mode.

Figure 18. CAN wake up capabilities

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Note: Pictures above illustrate the wake up behaviour from V1 standby mode. For wake up from
VBAT standby mode the NRESET signal (with 2 ms timing) is generated instead of the RXDL
(Interrupt) signal.

2.9.3 CAN sleep mode

During active mode it is possible to deactivate the CAN transceiver with a dedicated SPI
command (CR4, CAN_act = 0). The CAN transceiver remains deactivated until it is
activated again. With a deactivated CAN the receiver input termination network is
disconnected from the bus and the CANH, CANL bus lines is driven to GND. The SPLIT
output is also deactivated in this case.

32/98 Doc ID 16363 Rev 4

L99PM62XP Description

2.9.4 CAN receive only mode

With the CAN_rec_only bit in control register 4 it is possible to disable the CAN transmitter
in active mode. In this mode it is possible to listen to the bus but not sending to it. The
receiver termination network is still activated in this mode.

2.9.5 CAN looping mode

If the CAN_Loop_en bit in control register 4 is set the TXDC input is mapped directly to the
RXDC pin. This mode can be used in combination with the CAN receive only mode, to run
diagnosis for the CAN protocol handler of the micro controller.

2.10 Serial peripheral interface (ST SPI standard)

A 24 bit SPI is used for bi-directional communication with the micro controller.
During active mode, the SPI
● Triggers the watchdog
● Controls the modes and status of all L99PM62XP modules (incl. input and output
drivers)
● Provides driver output diagnostic
● Provide L99PM62XP diagnostic (incl. over temperature warning, L99PM62XP
operation status)
The SPI can be driven by a micro controller with its SPI peripheral running in following
mode:
CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to micro controller with a built-in SPI. Only three CMOS-compatible
output pins and one input pin is needed to communicate with the device. A fault condition
can be detected by setting CSN to low. If CSN = 0, the DO-pin reflects the global error flag
(fault condition) of the device.

Chip select not (CSN)

The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) is in high impedance state. A low signal activates the output driver and a
serial communication can be started. The state during CSN = 0 is called a communication
frame.
If CSN = low for t > tCSNfail the DO output is switched to high impedance in order to not block
the signal line for other SPI nodes.

Serial data in (DI)

The input pin is used to transfer data serial into the device. The data applied to the DI is
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register is transferred to Data
Input Register. The writing to the selected data input register is only enabled if exactly 24
bits are transmitted within one communication frame (i.e. CSN low). If more or less clock

Doc ID 16363 Rev 4 33/98

Description L99PM62XP

pulses are counted within one frame the complete frame is ignored. This safety function is
implemented to avoid an activation of the output stages by a wrong communication frame.
Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.

Serial data out (DO)

The data output driver is activated by a logical low level at the CSN input and goes from high
impedance to a low or high level depending on the global error flag (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin transfers the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK shifts the next bit out.

Serial clock (CLK)

The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the
falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 1MHz.

34/98 Doc ID 16363 Rev 4

L99PM62XP Protection and diagnosis

3 Protection and diagnosis

3.1 Power supply fail

Over and under-voltage detection on Vs

3.1.1 Vs overvoltage
If the supply voltage Vs reaches the over voltage threshold (VSOV):
● Outputs OUTx, RELx and LIN are switched to high impedance state (load protection).
CAN is not disabled. Recovery of outputs when the overvoltage condition disappears is
depending on the setting of VLOCKOUT_EN bit in Control Register 4.
– VLOCKOUT_EN = 1: Outputs are off until read and clear SR3.
– VLOCKOUT_EN = 0: Outputs switch automatically on when overvoltage condition
disappears.
● The over voltage bit is set and can be cleared with a ‘Read and Clear’ command. The
overvoltage bit is removed automatically if VLOCKOUT_EN = 0 and the overvoltage
condition disappears.
● Outputs REL1,2 can be excluded from a shutdown in case of overvoltage by SPI
(LSOVUV_ Shutdown_en in CR4)

3.1.2 Vs undervoltage
If the supply voltage Vs drops below the under voltage threshold voltage (VSUV)
● Outputs OUTx, RELx and LIN are switched to high impedance state (load protection).
CAN is not disabled. Recovery of outputs when the undervoltage condition disappears
is depending on the setting of VLOCKOUT_EN bit.
VLOCKOUT_EN = 1: Outputs are off until read and clear SR3.
VLOCKOUT_EN = 0: Outputs switch on automatically when undervoltage condition
disappears.
● The undervoltage bit is set and can be cleared with a ‘Read and Clear’ command. The
undervoltage bit is removed automatically if VLOCKOUT_EN = 0 and the undervoltage
condition disappears
● Outputs REL1,2 can be excluded from a shutdown in case of undervoltage by SPI
(LSOVUV_shutdown_en in CR4)

Doc ID 16363 Rev 4 35/98

Protection and diagnosis L99PM62XP

Figure 19. Over voltage and under voltage protection and diagnosis

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36/98 Doc ID 16363 Rev 4

L99PM62XP Protection and diagnosis

3.2 Temperature warning and thermal shutdown

Figure 20. Thermal shutdown protection and diagnosis

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Note: The thermal state machine recovers the same state were it was before entering standby
mode. In case of a TSD2 it enters TSD1 state.

Doc ID 16363 Rev 4 37/98

Protection and diagnosis L99PM62XP

3.3 High-side driver outputs

The component provides a total of 4 high-side outputs Out1 to 4, (7 Ω typ. at @ 25°C) to
drive e.g. LED's or hall sensors and 1 high-side output OUT_HS with 1 Ω typ. at @ 25 °C).
The high-side outputs switch off in case of:
● Vs over and undervoltage
● Over current
● Overtemperature with pre warning(a)
In case of overload or over temperature (TSD1) condition, the drivers switchs off. The
according status bit is latched and can be read and optionally cleared by SPI. The drivers
remain off until the status is cleared.
In case over/under voltage condition, the drivers is switched off. The according status bit is
latched and can be read and optionally cleared by SPI. If the Vlockout bit (Control Register
4) is set to ‘1’ the drivers remain off until the status is cleared. If the Vlockout bit is set to ‘0’
the drivers switches on automatically if the error condition disappears.
In case of open-load condition, the according status register is latched. The status can be
read and optionally cleared by SPI. The high-sides not switches off.
For OUT_HS the auto recovery feature (OUTHSREC bit Control Register 4) can be
enabled. If this bit is set to ‘1’ the driver is automatically restart from a overload condition.
This overload recovery feature is intended for loads which have an initial current higher than
the over current limit of the output (e.g. Inrush current of cold light bulbs). During auto
recovery mode the over current status bit can not be read from SPI.
The device itself can not distinguish between a real overload and a non linear load like a
light bulb. A real overload condition can only be qualified by time. As an example, the micro
controller can switch on light bulbs by setting the over current recovery bit for the first 50ms.
After clearing the recovery bit, the output is automatically disabled if the overload condition
still exists.
In case of a fail safe condition, the high-side drivers are switched off. The control bits are set
to default values. (except OUT3/FSO if it is used as a high-side driver output)
Note: The maximum voltage and current applied to the high-side outputs is specified in
Section 2.1: Voltage regulators. Appropriate external protection may be required in order to
respect these limits under application conditions.

3.4 Low-side driver outputs REL1, REL2

The outputs REL1, REL2 (RDSon = 2 Ω typ. @25 °C) are specially designed to drive relay
loads.
The outputs provide an active output zener clamping (45 V typ.) feature for the
demagnetization of the relay coil, even though a load dump condition exists.
For fail-safe reasons the relay drivers are linked with the fail safe operation: in case of
entering the fail safe mode, the relay drivers switchs off and the SPI control bits are set to
default (i.e. driver is off).

a. Except OUT3 when configured as FSO.

38/98 Doc ID 16363 Rev 4

L99PM62XP Protection and diagnosis

The low-side drivers switch off in case of:

● Vs over and undervoltage
● Over current
● Overtemperature with pre warning
In case of overload or overtemperature (TSD1) condition, the drivers switches off. The
according status bit is latched and can be read and optionally cleared by SPI. The drivers
remain off until the status is cleared.
In case Vs over/undervoltage condition, the drivers is switched off. The according status bit
is latched and can be read and optionally cleared by SPI. If the Vlockout bit (Control
Register 4) is set to ‘1’ the drivers remain off until the status is cleared. If the Vlockout bit is
set to ‘0’ the drivers is switched on automatically if the error condition disappears.
With the LSOVUV_shutdown_en bit (Control Register 4) the drivers can be excluded from a
switch off in case of Vs over/undervoltage. If the bit is set to ‘1’ the driver switchs off,
otherwise the drivers remain on.

3.5 SPI diagnosis

Digital diagnosis features are provided by SPI (for details please refer to Section 6.2: SPI
registers .
● V1 reset threshold programmable
● Overtemperature including. pre warning
● Open-load separately for each output stage except REL1/REL2
● Overload status separately for each output stage
● Vs-supply over/under voltage
● V1 and V2 fail bit
● V2 output short to GND
● Status of the WU1 to 3
● Wake-up sources (CAN, LIN, SPI, Timer, WU1…3)
● chip reset bit (start from power-on reset)
● Number of unsuccessful V1 restarts after thermal shutdown
● Number of sequential watchdog failures
● LIN diagnosis (permanent recessive/dominant, dominant TxD)
● CAN diagnosis (permanent recessive/dominant, dominant TxD, recessive RXD)
● Device State (wake-up from V1 standby or VBAT standby)
● Forced VBAT standby after WD-fail, forced VBAT standby after overtemperature
● Watchdog timer state (diagnosis of watchdog)
● Fail-safe status
● SPI communication error

Doc ID 16363 Rev 4 39/98

Typical application L99PM62XP

4 Typical application

Figure 21. Typical application diagram

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40/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

5 Electrical specifications

5.1 Absolute maximum rating

Table 7. Absolute maximum rating
Symbol Parameter/test condition Value [DC voltage] Unit

VS DC supply voltage / “jump start” -0.3 to +28 V

Single pulse / tmax < 400 ms “transient load dump” -0.3 to +40 V
V1 Stabilized supply voltage, logic supply -0.3 to +5.25 V
V2 Stabilized supply voltage -0.3 to +28 V
VDI VCLK
VDO VRXDL
Logic input / output voltage range -0.3 to V1+0.3 V
VNRESET
VRXDC
VTXDC, VTXDL, VCSN Multi level inputs -0.3 to Vs+0.3 V
VREL1, VREL2, Low-side output voltage range -0.3 to +40 V
VOUT1..3, VOUT_HS High-side output voltage range -0.3 to VS+0.3 V
VWU1...4 Wake up input voltage range -0.3 to VS+0.3 V
VOP1P,VOP1M, Opamp1 input voltage range
-0.3 to V1+0.3 V
VOP2P, VOP2M, Opamp2 input voltage range
VOPOUT1,
Analog Output voltage range -0.3 to VS+0.3 V
VOPOUT2
VLIN, VLINPU LIN bus I/O voltage range -20 to +40 V
IInput Current injection into Vs related input pins 10 mA
Iout_inj Current injection into Vs related outputs 10 mA
VCANSUP CAN supply -0.3 to +5.25 V
VCANH, VCANL,
CAN bus I/O voltage range -27 to +40 V
VSPLIT

Note: All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit!
Loss of ground or ground shift with externally grounded loads: ESD structures are
configured for nominal currents only. If external loads are connected to different grounds,
the current load must be limited to this nominal current.

Doc ID 16363 Rev 4 41/98

Electrical specifications L99PM62XP

5.2 ESD protection

Table 8. ESD protection
Parameter Value Unit
(1)
All pins +/-2 kV
All output pins(2) +/-4 kV
+/-8(2)
LIN kV
+/-6(3)
+/-8(2)
CAN_H, CAN_L kV
+/-6(3)
All pins (charge device model) +/-500 V
Corner pins (charge device model) +/-750 V
All pins(4) +/-200 V
1. HBM (human body model, 100pF, 1.5 kΩ) according to MIL 883C, method 3015.7 or EIA/JESD22A114-A
2. HBM with all none zapped pins grounded.
3. EN / IEC61000-4-2 according to report from external test house.
4. Acc. machine model: C = 200 pF; R = 0 Ω.

5.3 Thermal data

Table 9. Operating junction temperature
Symbol Parameter Value Unit

Tj Operating junction temperature -40 to 150 °C

RthjA Thermal resistance junction / ambient See Figure 23 °K/W

Table 10. Temperature warning and thermal shutdown

Symbol Parameter Min. Typ. Max. Unit

Thermal over temperature warning

TW ON Tj(1) 120 130 140 °C
threshold
TSD1 OFF Thermal shutdown junction temperature 1 Tj(1) 130 140 150 °C
TSD2 OFF Tj(1) 140 155 170 °C
TSD2 ON Thermal shutdown junction temperature 2
Hysteresis 5 °C
TSD12hys
1. Non-overlapping

42/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

5.4 Package and PCB thermal data

5.4.1 PowerSSO-36 thermal data

Figure 22. PowerSSO-36 PC board

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Note: Layout condition of Rth and Zth measurements (board finish thickness 1.6 mm +/- 10% board
double layer, board dimension 129x60, board Material FR4, Cu thickness 0.070 mm (front
and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm,
Cu thickness on vias 0.025 mm).

Doc ID 16363 Rev 4 43/98

Electrical specifications L99PM62XP

Figure 23. PowerSSO-36 thermal resistance junction to ambient vs PCB copper area
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Cu=2 cm2
Cu=foot print

10

1
0.01 0.1 1 10 100 1000
Time (s)

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44/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Figure 25. PowerSSO-36 thermal fitting model (V1 ON)

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Equation 1: pulse calculation formula

Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )

where δ = tp ⁄ T

Table 11. Thermal parameter

Area/island (cm2) Footprint 2 8

R1 (°C/W) 2
R2 (°C/W) 8 4 4
R3 (°C/W) 20 15.5 10
R4 (°C/W) 36 29 18
C1 (W.s/°C) 0.01
C2 (W.s/°C) 0.1 0.2 0.2
C3 (W.s/°C) 0.8 1 1.5
C4 (W.s/°C) 2 3 6

Doc ID 16363 Rev 4 45/98

Electrical specifications L99PM62XP

5.5 Electrical characteristics

5.5.1 Supply and supply monitoring

The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin Tj = -40 °C to 130 °C, unless otherwise specified.

Table 12. Supply and supply monitoring

Symbol Parameter Test condition Min. Typ. Max. Unit

VS Supply voltage range 6 13.5 18 V

VSUV VS undervoltage threshold VS increasing / decreasing 5.11 5.81 V
Vhyst_UV Vs undervoltage hysteresis 0.0 0.1 0.15 V
VSOV VS overvoltage threshold VS increasing / decreasing 18.5 22 V
Vhyst_OV Vs overvoltage hysteresis Hysteresis 0.5 1 1.5 V
tovuv_filt Vs over/undervoltage filter time 64*Tosc
Vs = 12V
Current consumption in TxD CAN = high
IV(act) 6 12 mA
active mode TxD LIN = high
V1 = on, V2 = on
VS = 12V
Current consumption in
IV(BAT) Both voltage regulators deactivated, 8 12 28 µA
VBAT standby mode
no wake-up request(1)
VS = 12V
Current consumption in
Both voltage regulators deactivated,
IV(BAT)CS VBAT standby mode with cyclic 40 75 125 µA
sense enabled T = 50 ms, ton = 100 µs no wake-up
request(1)
VS = 12V
Current consumption in
Both voltage regulators deactivated
IV(BAT)CW VBAT standby mode with cyclic 40 75 125 µA
wake enabled During standby phase no
wake-up request(1)
VS = 12V
Current consumption in
I(V1) Voltage Regulator V1 active, 16 51 76 µA
V1-standby mode
(Iv1 < Icmp) no wake-up request(1)
1. Conditions for no wake-up request are (all conditions must be met):
2 V < LIN < (Vs-2 V)
0.4 V < (CAN_H – CAN_L) < 1,2 V
1 V < VWUth < (Vs-2 V)
The current consumption in standby modes with cyclic sense can be calculated using the following formulas:
IV(BAT)CS = IV(BAT) + 55 µA + (2 mA * (tON + 100 µs) / T)
I(V1)CS = IV1 + 55 µA + (2 mA * (tON + 100 µs) / T)

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L99PM62XP Electrical specifications

5.5.2 Oscillator
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V < VS < 28 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.

Table 13. Oscillator

Symbol Parameter Test condition Min. Typ. Max. Unit

FCLK Oscillation frequency 0.80 1.0 1.35 MHz

5.5.3 Power-on reset (Vs)

All outputs open; Tj = -40°C to 130°C, unless otherwise specified.

Table 14. Power-on reset (Vs)

Symbol Parameter Test condition Min. Typ. Max. Unit

VPOR VPOR threshold Vs increasing 3.45 4.5 V

VPOR VPOR threshold Vs decreasing(1) 2.65 3.5 V
1. This threshold is valid if Vs had already reached 7V previously

5.5.4 Voltage regulator V1

The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V < VS < 28 V; Tj = -40 °C to 130 °C, unless otherwise specified.

Table 15. Voltage regulator V1

Symbol Parameter Test condition Min. Typ. Max. Unit

V1 Output voltage 5.0 V

Output voltage tolerance ILOAD1 = 1mA to 100 mA,
V1 +/- 2 %
Active mode VS = 13.5 V
ILOAD1 = 100 mA to 250 mA,
+/- 3 %
Output voltage tolerance VS = 13.5 V
Vhc1
active mode, high current ILOAD1 = 250 mA
+/- 5% %
VS = 13.5 V
Output voltage tolerance ILOAD1 = 0 µA to 1 mA,
VSTB1 +/- 4% %
V1-standby mode VS = 13.5 V
ILOAD1 = 50 mA, VS = 5 V 0.2 0.4 V
ILOAD1 = 100 mA, V = 4.5 V 0.2 0.5 V
VDP1 Drop-out Voltage ILOAD1 = 100 mA, VS = 5 V 0.3 0.5 V
ILOAD1 = 150 mA, VS = 4.5 V 0.45 0.6 V
ILOAD1 = 150 mA, VS = 5.0 V 0.45 0.6 V
ICC1 Output current in active mode Max. continuous load current 250 mA
ICCmax1 Short circuit output current Current limitation 400 600 950 mA
Cload1 Load capacitor1 Ceramic (+/- 20%) 0.22(1) µF

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Electrical specifications L99PM62XP

Table 15. Voltage regulator V1 (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

V1 deactivation time after

tTSD 1 sec
thermal shutdown
Icmp_ris Current comp. rising thresh. Rising current 1.2 2.5 4 mA
Icmp_fal Current comp. falling threshold Falling current 0.8 1.95 2.8 mA
Icmp_hys Current comp. hysteresis 0.5 mA
V1fail V1 fail threshold V1 forced 2 V
tV1fail V1 fail filter time 2 µs
tV1short V1 short filter time 4 ms
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20 %). Capacitor must be
located close to the regulator output pin.

5.5.5 Voltage regulator V2

The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V < VS < 28 V; Tj = -40 °C to 130 °C, unless otherwise specified.

Table 16. Voltage regulator V2

Symbol Parameter Test condition Min. Typ. Max. Unit

V2 Output voltage 5,0 V

Output voltage tolerance ILOAD2 = 1 mA to 50 mA,
V2 +/- 3 %
active mode VS = 13.5 V
Output voltage tolerance ILOAD2 = 50 mA to 80 mA,
Vhc1 +/- 4 %
active mode VS = 13,5 V
Output voltage tolerance
V2 ILOAD2 = 100 mA, VS = 13,5 V +/- 6 %
active mode, high current
Output voltage tolerance ILOAD2 = 0 µA to 1 mA
VSTB2 +/-6 %
V1 standby mode VS = 13,5 V
ILOAD2 = 25 mA, Vs = 5.25 V 0.3 0.4 V
VDP2 Drop-out voltage
ILOAD2 = 50 mA, Vs = 5.25 V 0.4 0.7 V
ICC2 Output current in active mode Max. continuous load current 100 mA
ICCmax2 Short circuit output current Current limitation 200 300 500 mA
Cload Load capacitor Ceramic (+/- 20 %) 0.22(1) µF
V2fail V2 fail threshold V2 forced 2 V
tV2fail V2 fail filter time 2 µs
tV2short V2 short filter time 4 ms
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20 %). Capacitor must be
located close to the regulator output pin.

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L99PM62XP Electrical specifications

5.5.6 Reset output

The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 4.0 V < VS = 28 V; Tj = -40 °C to 130 °C, unless otherwise specified.

Table 17. Reset output

Symbol Parameter Test condition Min. Typ. Max. Unit

VRT1 Reset threshold voltage1 V1 decreasing 3.7 3.9 4.1 V

VRT2 Reset threshold voltage2 V1 decreasing 4.2 4.3 4.45 V
VRT3 Reset threshold voltage3 V1 decreasing 4.25 4.4 4.55 V
VRT4 Reset threshold voltage4 V1 decreasing 4.5 4.60 4.75 V
VRT4 Reset threshold voltage4 V1 increasing 4.7 4.8 4.9 V
V1 > 1V, IRESET =
VRESET Reset pin low output voltage 0,2 0,4 V
5 mA
RRESET Reset pull up int. resistor 80 110 150 kΩ
tRR Reset reaction time ILOAD1 = 1 mA 6 40 µs
tUV1 V1 under-voltage filter time 16 µs
Trd Reset pulse duration 1.5 2 2.5 ms

5.5.7 Watchdog
4.5 V < VS < 28 V; 4.8 V < V1 < 5.2 V; Tj = -40 °C to 130 °C, unless otherwise specified, see
Figure 26 and Figure 27.

Table 18. Watchdog

Symbol Parameter Test condition Min. Typ. Max. Unit

tLW Long open window TBD 48,75 65 81,25 ms

TEFW1 Early failure window 1 4.5 ms
TLFW1 Late failure window 1 20 ms
TSW1 Safe window 1 7.5 12 ms
TEFW2 Early failure window 2 22.5 ms
TLFW2 Late failure window 2 100 ms
TSW2 Safe window 2 37.5 60 ms
TEFW3 Early failure window 3 45 ms
TLFW3 Late failure window 3 200 ms
TSW3 Safe window 3 75 120 ms
TEFW4 Early failure window 4 90 ms
TLFW4 Late failure window 4 400 ms
TSW4 Safe window 4 150 240 ms

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Electrical specifications L99PM62XP

Figure 26. Watchdog timing (long, early, late and safe window)
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50/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Figure 27. Watchdog early, late and safe windows

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5.5.8 High-side outputs

The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tj = -40 °C to 130 °C, unless
otherwise specified.

Table 19. Output (OUT_HS)

Symbol Parameter Test condition Min. Typ. Max. Unit

Static drain source Tj = 25 °C 1,0 2 Ω

RDSON on-resistance
(IOUT_HS = 150 mA) Tj = 125 °C 1.6 3 Ω
tdON Switch on delay time 0.2 VS 5 35 60 µs
tdOFF Switch off delay time 0.8 VS 40 95 150 µs
tSCF Short circuit filter time Tested by scan chain 64*TOSC
tdARHS Auto recovery filter time Tested by scan chain 400*TOSC
dVOUT/dt Slew rate 0,18 0,5 0,8 V/µs
Short circuit shutdown
IOUT 480 900 1320 mA
current
IOLD Open-load detection current 40 80 120 mA
tOLDT Open-load detection time Tested by scan chain 64*TOSC
Loss of GND current
IFW 1 100 mA
(ESD structure)

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Electrical specifications L99PM62XP

The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tj = -40 °C to 130 °C, unless
otherwise specified.

Table 20. Outputs (OUT1...4)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Static drain source

ILOAD = 60 mA @
RDSON on-resistance 7 13 Ω
Tj = +25 °C
(IOUT_HS = 150mA)
IOUT Short circuit shutdown current 8 V < Vs < 16 V 140 235 350 mA
IOLD Open-load detection current 1 0.9 2 4.5 mA
dVOUT/dt Slew rate 0.2 0.5 0.8 V/µs
tdON Switch ON delay time 0.2 Vs 5 35 60 µs
tdOFF Switch OFF delay time 0.8 Vs 30 95 150 µs
tSCF Short circuit filter time Tested by scan chain 64*TOSC
Loss of GND current
IFW(1) 100 mA
(ESD structure)
tOLDT Open-load detection time Tested by scan chain 64*TOSC
1. Parameter guaranteed by design

5.5.9 Relay drivers

The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tj = -40 °C to 130 °C, unless
otherwise specified.

Table 21. Relay drivers

Symbol Parameter Test condition Min. Typ. Max. Unit

RDSON DC output resistance ILOAD = 100 mA @ Tj = +25 °C 2 3 Ω

IOUT Short circuit shutdown current 8 V < Vs < 16 V 250 375 500 mA
VZ Output clamp voltage(1) ILOAD = 100 mA 40 48 V
tONHL Turn on delay time to 10% VOUT 5 50 100 µs
tOFFLH Turn off delay time to 90% VOUT 5 50 100 µs
tSCF Short circuit filter time Tested by scan chain 64*TOSC
dVOUT/dt Slew Rate 0.2 2 4 V/µs
1. The output is capable to switch off relay coils with the impedance of RL = 160Ω; L = 300mH (RL = 220Ω; L = 420mH); at VS = 40V (Load
dump condition)

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L99PM62XP Electrical specifications

5.5.10 Wake up inputs (WU1... WU3)

The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; Tj = -40 °C to 130 °C, unless otherwise specified.

Table 22. Wake up inputs (WU1... WU3)

Symbol Parameter Test condition Min. Typ. Max. Unit

Wake-up negative edge threshold

VWUthp 0,4*Vs 0.45*Vs 0,5*Vs V
voltage
Wake-up positive edge threshold
VWUthn 0,5*Vs 0,55*Vs 0,6*Vs V
voltage
VHYST Hysteresis 0.05*Vs 0.1*Vs 0.15*Vs V
tWU_stat Static wake filter time 64*TOSC µs
IWU_stdby Input current in standby mode 1 V > Vin > (Vs - 2 V) 10 20 30 µA
Input resistor to Gnd in active mode
RWU_act and in standby mode during wake-up 80 160 300 kΩ
request
tWU_cyc Cyclic wake filter time 16(1) µs
1. Blanking time 80 µs or 800 µs.

5.5.11 High speed CAN transceiver(b)

The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < Vcansup. < 5.2 V; Tjunction = -40 °C to 130 °C, unless otherwise
specified.

Table 23. CAN transmit data input: pin TXDC

Symbol Parameter Test condition Min. Typ. Max. Unit
Input voltage dominant
VTXDCLOW Active mode, V1 = 5 V 1.35 1.8 V
level
Input voltage
VTXDCHIGH Active mode, V1 = 5 V 2.5 2.8 V
recessive level
VTXDCHYS VTXDCHIGH-VTXDCLOW Active mode, V1 = 5 V 0.7 1 V
RTXDCPU TXDC pull up resistor Active mode, V1 = 5 V 10 20 35 kΩ

Table 24. CAN receive data output: pin RXDC

Symbol Parameter Test condition Min. Typ. Max. Unit

VRXDCLOW Output voltage dominant level Active mode, V1 = 5 V, 2 mA 0.2 0.5 V

VRXDCHIGH Output voltage recessive level Active mode, V1 = 5 V, 2 mA 4.5 V

b. ISO 11898-2 and ISO 11898-5 compliant; SAE J2284 compliant.

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Electrical specifications L99PM62XP

Table 25. CAN bus common mode stabilization output termination: pin SPLIT
Symbol Parameter Test Condition Min. Typ. Max. Unit

Active mode;
Split output voltage, loaded 0.3* 0.5* 0.7*
VSPLIT,l VTXDC = VTXDCHIGH; V
condition (normal mode) VCANSUP VCANSUP VCANSUP
|Isplit| = 500 µA
Split output voltage,
Active mode; 0.5* 0.55*
VSPLIT,u unloaded condition (normal V
VTXDC = VTXDCHIGH; No Load VCANSUP VCANSUP
mode)
Split leakage current (low V1-standby mode;
ISPLIT 5 µA
power mode) -12 V < VSPLIT < 12 V

Table 26. CAN transmitter and receiver: pins CANH and CANL
Symbol Parameter Test Condition Min. Typ. Max. Unit

CANH voltage level in dominant Active mode;

VCANHdom state VTXDC = VTXDCLOW; 2.75 4.5 V
RL = 60 Ω
CANL voltage level in dominant Active mode;
VCANLdom state VTXDC = VTXDCLOW; 0.5 2.25 V
RL = 60 Ω
Differential output voltage in Active mode;
VDIFF,domOUT dominant state: VTXDC = VTXDCLOW; 1.5 3 V
VCANHdom - VCANLdom RL = 60 Ω
Driver symmetry: Active mode;
VCANHdom + 0VCANLdom VTXDC = VTXDCLOW; 0.9* 1.1*
VCM V V
RL = 60 Ω; VCANSUP CANSUP VCANSUP
CSPLIT = 4.7 pF
CANH voltage level in recessive Active mode;
VCANHrec state (normal mode) VTXDC = VTXDCHIGH; 2 2.5 3 V
no load
CANL voltage level in recessive Active mode;
VCANLrec state (normal mode) VTXDC = VTXDCHiGH; 2 2.5 3 V
no load
CANH voltage level in recessive V1 standby mode;
VCANHrecLP state (low power mode) VTXDC = VTXDCHIGH; -0.1 0 0.1 V
no load
CANL voltage level in recessive V1 standby mode;
VCANLrecLP state (low power mode) VTXDC = VTXDCHiGH; -0.1 0 0.1 V
no load
Differential output voltage in Active mode;
VDIFF,recOUT recessive state (normal mode): VTXDC = VTXDCHIGH; -50 50 mV
VCANHrec - VCANLrec no load
Differential output voltage in V1 standby mode;
VDIFF,recOUTL
recessive state (low power VTXDC = VTXDCHIGH; -50 50 mV
P mode): VCANHrec - VCANLrec no load

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L99PM62XP Electrical specifications

Table 26. CAN transmitter and receiver: pins CANH and CANL (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit

Common mode Bus voltage Measured with respect to

VCANHL,CM the ground of each CAN -12 12 V
node
CANH output current in Active mode;
IOCANH,dom dominant state VTXDC = VTXDCLOW; -160 -75 -45 mA
VCANH = 0 V
CANL output current in Active mode;
IOCANL,dom dominant state VTXDC = VTXDCLOW; 45 75 160 mA
VCANL = 5 V
Input leakage current Unpowered device;
ILeakage 0 250 µA
VBUS = 5 V
Internal resistance Active mode & V1
standby mode;
Rin 20 27.5 38 kΩ
VTXDC = VTXDCHIGH;
no load
Differential internal resistance Active mode & V1
standby mode;
Rin,diff 50 60 75 kΩ
VTXDC = VTXDCHIGH;
no load
Cin Internal capacitance Guaranteed by design 20 pF
Cin,diff Differential internal capacitance Guaranteed by design 10 pF
Differential receiver threshold Active mode
VTHdom voltage recessive to dominant 0.9 V
state (normal mode)
Differential receiver threshold V1 standby mode
VTHdomLP voltage recessive to dominant 1.15 V
state (low power mode)
Differential receiver threshold Active mode
VTHrec voltage dominant to recessive 0.5 V
state (normal mode)
Differential receiver threshold V1 standby mode
VTHrecLP voltage dominant to recessive 0.4 V
state (low power mode)

Table 27. CAN transceiver timing

Symbol Parameter Test condition Min. Typ. Max. Unit

Propagation delay TXDC to Active mode; 50 % VTXDC to 50 %

tTXpd,hl 0 255 ns
RXDC (high to low) VRXDC; CRXDC = 100 pF; RL = 60 Ω
Propagation delay TXDC to Active mode; 50 % VTXDC to 50 %
tTXpd,lh 0 255 ns
RXDC (low to high) VRXDC; CRXDC = 100 pF; RL = 60 Ω
twake Wake up filter time 0.5 5 µs

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Electrical specifications L99PM62XP

Table 27. CAN transceiver timing (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

tdom(TXDC) TXDC dominant time-out 700 µs

CAN permanent dominant
tCAN 700 µs
time-out

5.5.12 LIN transceiver(c)

The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tjunction = -40 °C to 130 °C unless otherwise specified.

Table 28. LIN transmit data input: pin TXD

Symbol Parameter Test condition Min. Typ. Max. Unit

VTXDLOW Input voltage dominant level Active mode; V1 = 5 V 1,35 1.8 V

VTXDHIGH Input voltage recessive level Active mode; V1 = 5 V 2.5 2.8 V
VTXDHYS VTXDHIGH-VTXDLOW Active mode; V1 = 5 V 0.7 1 V
RTXDPU TXD pull up resistor Active mode; V1 = 5 V 10 20 35 kΩ

Table 29. LIN receive data output: pin RXD

Symbol Parameter Test condition Min. Typ. Max. Unit

Active mode;
VRXDLOW Output voltage dominant level 0.2 0.5 V
V1 = 5 V, ILOAD1 = 2 mA
Output voltage recessive Active mode;
VRXDHIGH 4.5 V
level V1 = 5 V, ILOAD1 = 2 mA

Table 30. LIN transmitter and receiver: pin LIN

Symbol Parameter Test condition Min. Typ. Max. Unit

Receiver threshold voltage

VTHdom 0.4*VS 0.45*VS 0.5*VS V
recessive to dominant state
Receiver threshold voltage
VTHrec 0.5*VS 0.55*VS 0.6*VS V
dominant to recessive state
Receiver threshold hysteresis:
VTHhys 0.07*VS 0.1*VS 0.175*VS V
VTHrec -VTHdom
Receiver tolerance center
VTHcnt 0.475*VS 0.5*VS 0.525*VS V
value: (VTHrec +VTHdom)/2
Receiver wakeup threshold
VTHwkup 1.0 1.5 2 V
voltage

c. LIN 2.1 compliant for Baud rates up to 20 kBit/s

SAE J2602 compatible

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L99PM62XP Electrical specifications

Table 30. LIN transmitter and receiver: pin LIN (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Receiver wakeup threshold

VTHwkdwn VS-3.5 VS-2.5 VS-1.5 V
voltage
Dominant time for wakeup via Sleep mode;
tlinbus 64*TOSC µs
bus edge: rec-dom

Transmitter input current limit in VTXD = VTXDLOW;

ILINDomSC 40 100 180 mA
dominant state VLIN = VBATMAX = 18 V

Input leakage current at the VTXD = VTXDHIGH;

Ibus_PAS_dom -1 mA
receiver incl. pull-up resistor VLIN = 0 V; VBAT = 12 V(1)
VTXD = VTXDHIGH;
Transmitter input current in 8 V < VLIN;
Ibus_PAS_rec 20 µA
recessive state VBAT < 18 V; VLIN >= VBAT
in standby modes
GND = VS;
Input current if loss of GND at
Ibus_NO_GND 0 V < VLIN < 18 V; -1 1 mA
device
VBAT = 12 V

Input current if loss of VBAT at GND = VS;

Ibus 100 µA
device 0 V < VLIN < 18 V
Active mode;
LIN voltage level in dominant
VLINdom VTXD = VTXDLOW; 1.2 V
state
ILIN = 40 mA
Active mode;
LIN voltage level in recessive
VLINrec VTXD = VTXDHIGH; 0.8*VS 1 V
state
ILIN = 10 µA
RLINup LIN output pull up resistor VLIN = 0 V 20 40 60 kΩ
1. Slave mode.

Table 31. LIN transceiver timing

Symbol Parameter Test condition Min. Typ. Max. Unit

tRXpd = max(tRXpdr, tRXpdf);

tRXpdf = t(0.5 VRXD) - t(0.45 VLIN);
tRXpdr = t(0.5 VRXD) - t(0.55 VLIN);
Receiver propagation delay
tRXpd VS = 12 V; CRXD = 20 pF; 6 µs
time
Rbus, = 1 kΩ, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF

Symmetry of receiver tRXpd_sym = tRXpdr - tRXpdf;

tRXpd_sym propagation delay time VS = 12 V; -2 2 µs
(rising vs. falling edge) Rbus = 1 kΩ, Cbus = 1 nF

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Electrical specifications L99PM62XP

Table 31. LIN transceiver timing (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

THRec(max) = 0.744*VS;
THDom(max) = 0.581*VS;
VS = 7 V to 18 V, tbit = 50 µs;
D1 Duty cycle 1 D1 = tbus_rec(min)/(2xtbit); 0.396
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
THRec(min) = 0.284*VS;
THDom(min) = 0.422*VS;
VS = 7.6 to 18 V, tbit = 50 µs;
D2 Duty cycle 2 D2 = tbus_rec(max)/(2xtbit); 0.581
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
THRec(max) = 0.778*VS;
THDom(max) = 0.616*VS;
VS = 7 V to 18 V, tbit = 96 µs;
D3 Duty cycle 3 D3 = tbus_rec(min)/(2xtbit); 0.417
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
THRec(min) = 0.251*VS;
THDom(min) = 0.389*VS;
VS = 7.6 V to 18 V, tbit = 96 µs;
D4 Duty cycle 4 D4 = tbus_rec(max)/(2xtbit); 0.590
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
tdom(TXDL) TXDL dominant time-out 12 ms
LIN permanent recessive
tLIN 40 µs
time-out
LIN bus permanent
tdom(BUS) 12 ms
dominant time-out

Table 32. LIN pull-up: pin LINPU

Symbol Parameter Test condition Min. Typ. Max. Unit

RDSON ON resistance 10.5 16 Ω

Ileak Leakage current 1 µA

58/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Figure 28. LIN transmit, receive timing

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5.5.13 Operational amplifier

The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; Tj = -40 °C to 130 °C, unless otherwise specified.

Table 33. Operational amplifier

Symbol Parameter Test condition Min. Typ. Max. Unit

GBW GBW product 1 3.5 7.0 MHz

AVOLDC DC open loop gain 80 dB
PSRR Power supply rejection DC, Vin = 150 mV 80 dB
Voff Input offset voltage -5 +5 mV
VICR Common mode input range -0.2 0 3 V
VOH Output voltage range high ILOAD = 1 mA to Gnd VS-0.2 VS V
VOL Output voltage range low ILOAD = 1 mA to VS 0 0.2 V
ILim+ Output current limitation + DC 10 15 30 mA
Ilim- Output current limitation - DC -10 15 -30 mA
SR+ Slew rate positive 1 4 10 V/µs
SR- Slew rate negative -1 -4 -10 V/µs

Note: The operational amplifier is on-chip stabilized for external capacitive loads CL < 25 pF (all operating
conditions)

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Electrical specifications L99PM62XP

5.5.14 SPI
Input: CSN
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.

Input: CSN

Table 34. Input: CSN

Symbol Parameter Test condition Min. Typ. Max. Unit

VCSNLOW Input voltage low level Normal mode, V1 = 5 V 1.35 1.8 V

VCSNHIGH Input voltage high level Normal mode, V1 = 5 V 2 2.8 V
VCSNHYS VCSNHIGH - VCSNLOW Normal mode, V1 = 5 V 0.6 1.0 1.5 V
ICSNPU CSN pull up resistor Normal mode, V1 = 5 V 10 20 35 kΩ

CLK, DI
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.

Table 35. Input CLK, DI

Symbol Parameter Test condition Min. Typ. Max. Unit

Switching from standby to

delay time from standby active mode. Time until
tset 160 300 µs
to active mode output drivers are enabled
after CSN going to high.
Vin L input low level V1 = 5 V 1.0 2.05 2.5 V
Vin H input high level V1 = 5 V 1.5 2.8 3.5 V
Vin Hyst input hysteresis V1 = 5 V 0.4 0.75 1.5 V
pull down current at
I in Vin = 1.5 V 5 30 60 µA
input
input capacitance at
Cin(1) input CSN, CLK, DI and 0 V < V1 < 5.3 V 10 15 pF
PWM1,2
SPI input frequency at
fCLK 1 MHz
CLK
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.

DI timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.

60/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Table 36. DI timing(1)

Symbol Parameter Test condition Min. Typ. Max. Unit

tCLK Clock period V1 = 5 V 1000 - ns

tCLKH Clock high time V1 = 5 V 400 - ns
tCLKL Clock low time V1 = 5 V 400 - ns
CSN setup time, CSN low
tset CSN V1 = 5 V 400 - ns
before rising edge of CLK
CLK setup time, CLK high
tset CLK V =5V 400 - ns
before rising edge of CSN 1
tset DI DI setup time V1 = 5 V 200 - ns
thold DI DI hold time V1 = 5 V 200 - ns
Rise time of input signal
tr in V1 = 5 V - 100 ns
DI, CLK, CSN
Fall time of input signal
tf in V1 = 5 V - 100 ns
DI, CLK, CSN
1. See Figure 30.

DO
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.

Table 37. DO output pin

Symbol Parameter Test condition Min. Typ. Max. Unit

VDOL Output low level V1 = 5 V, ID = -4 mA 0.5 V

VDOH output high level V = 5 V, ID = 4 mA 4.5 V
IDOLK 3-state leakage current VCSN = V1, 0 V < VDO < V1 -10 10 µA
VCSN = V1,
CDO 2 3-state input capacitance 10 15 pF
0 V < V1 < 5.3 V

DO timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.

Table 38. DO timing(1)

Symbol Parameter Test condition Min. Typ. Max. Unit

tr DO DO rise time CL = 100 pF, ILOAD = -1 mA - 50 100 ns

tf DO DO fall time CL = 100 pF, ILOAD = 1 mA - 50 100 ns
DO enable time CL = 100 pF, ILOAD = 1 mA
ten DO tri L - 50 250 ns
from 3-state to low level pull-up load to V1

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Electrical specifications L99PM62XP

Table 38. DO timing(1) (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

DO disable time CL = 100 pF, ILOAD = 4 mA

tdis DO L tri - 50 250 ns
from low level to 3-state pull-up load to V1
DO enable time CL = 100 pF, ILOAD = -1 mA
ten DO tri H - 50 250 ns
from 3-state to high level pull-down load to GND
DO disable time CL = 100 pF, ILOAD = -4 mA
tdis DO H tri - 50 250 ns
from high level to 3-state pull-down load to GND
VDO < 0.3 V1,
td DO DO delay time VDO > 0.7 V1, - 50 250 ns
CL = 100 pF
1. See Figure 31 and Figure 32.

CSN timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.

Table 39. CSN timing(1)

Symbol Parameter Test Condition Min. Typ. Max. Unit

Minimum CSN HI Transfer of SPI-command to Input

tCSN_HI,min 6 µs
time, active mode register
tCSNfail CSN low timeout Tested by scan chain 20 35 50 ms
1. See Figure 33.

5.5.15 Inputs TxD_C and TxD_L for Flash mode

6 V ≤ Vs ≤ 18 V; 4.5 V ≤ V1 ≤ 5.3 V; Tj = -40 °C to 130 °C, voltages are referred to PGND,
all outputs open

Table 40. Inputs TxD_C and TxD_L for Flash mode

Symbol Parameter Test condition Min. Typ. Max. Unit

VFlashL Input low level (VTXDC/L rising) V1 = 5 V 6.1 7.25 8.4 V

VFlashH Input high level (VTXDC/L falling) V1 = 5 V 7.4 8.4 9.4 V
VFlashHYS Input Voltage Hysteresis V1 = 5 V 0.6 0.8 1.0 V

62/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Figure 29. SPI – transfer timing diagram

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Doc ID 16363 Rev 4 63/98

Electrical specifications L99PM62XP

Figure 31. SPI output timing (part 1)

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64/98 Doc ID 16363 Rev 4

L99PM62XP Electrical specifications

Figure 32. SPI output timing (part 2)

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Doc ID 16363 Rev 4 65/98

ST SPI L99PM62XP

6 ST SPI

6.1 SPI communication flow

6.1.1 General description

The proposed SPI communication is based on a standard SPI interface structure using CSN
(Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock)
signal lines.
At device start-up the master reads the <SPI-frame-ID> register (ROM address 3EH) of the
slave device. This 8-bit register indicates the SPI frame length (24bit) and the availability of
additional features.
Each communication frame consists of an instruction byte which is followed by 2 data bytes.
The data returned on SDO within the same frame always starts with the <Global Status>
register. It provides general status information about the device. It is followed by 2 data
bytes (i. e. ‘In-frame-response’).
For write cycles the <Global Status> register is followed by the previous content of the
addressed register.
For read cycles the <Global Status> register is followed by the content of the addressed
register.
A write command is only accepted as a valid command by the device if the counted number
of clocks is exact 24, otherwise the command is rejected.

Command byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (<Write>, <Read>, <Read and Clear>, <Read Device
Information>) and a 6 bit address. If less than 6 address bits are required, the remaining bits
are unused but are reserved.

Table 41. Command byte

MSB LSB

Op code Address
OC1 OC0 A5 A4 A3 A2 A1 A0

OCx: operating code

Ax: address

6.1.2 Operating code definition

Table 42. Operating code definition

OC1 OC0 Meaning

0 0 <Write Mode>
0 1 <Read Mode>

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L99PM62XP ST SPI

Table 42. Operating code definition (continued)

OC1 OC0 Meaning

1 0 <Read and Clear Status>

1 1 <Read Device Information>

The <Write Mode> <Read Mode> and <Read and Clear Status> operations allow access to
the RAM of the device, i. e. to write to control registers or read status information.
A <Read and Clear Status> operation addressed to a device specific status register reads
back and subsequently clear this status register.
A <Read and Clear Status> operation with address 3FH clears all status registers (including
the Global Status Register). Configuration register is read by this operation.
<Read Device Information> allows access to the ROM area which contains device related
information such as the product family, product name, silicon version, register width and
availability of a watchdog.
More detailed descriptions of the device information are available in ‘Read Device
Information’.

6.1.3 Global status register(d)

Table 43. Global status register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Global error Comm Not (chip reset VS Fail Fail

TSD2 TSD1 V1 Fail
flag (GEF) error OR comm error) (OV/UV) safe

6.1.4 Configuration register

The <Configuration> register is accessible at RAM address 3FH.
For the config register, the 8 bits are located in the low byte (LSB).
The configuration register is implemented for compliance purpose to ST SPI standard.

Table 44. Configuration register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 0 0 WD trigger

<WD trigger>: this bit is reserved to serve the watchdog.

d. See Section 6.2 for details.

Doc ID 16363 Rev 4 67/98

ST SPI L99PM62XP

Figure 34. Read configuration register

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1. The configuration register is implemented for compliance with ST standard SPI 3.0 and contains only the
watchdog trigger bit at D0

Figure 35. Write configuration register

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1. The configuration register is implemented for compliance with ST standard SPI 3.0 and contains only the
watchdog trigger bit at D0

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L99PM62XP ST SPI

6.1.5 Address mapping

Table 45. Address mapping

RAM ROM
Description Access Description Access
adress adress

3FH <Configuration> R/W 3FH Reserved N/A

13H Status register 3 R
3EH <SPI frame ID> R
12H Status register 2 R
11H Status register 1 R … Unused N/A
06H Control register 6 R/W
03H <product code 2> N/A
05H Control register 5 R/W
04H Control register 4 R/W
02H <product code 1> R
03H Control register 3 R/W
02H Control register 2 R/W
01H <silicon version> R
01H Control register 1 R/W
00H Reserved R/W
00H <ID Header> R

The RAM memory area consists of 16 bit registers.

For the device information (ROM memory area) the eight most significant bits of the memory
cell are used. The remaining 8 are zero.
All unused RAM and ROM addresses is read as ‘0’.
Note: 1 The register definition for RAM address 00H is unused. A register value of all 0 must cause
the device to enter a fail-safe state (interpreted as ‘SDI stuck to GND’ failure).
2 ROM address 3FH is unused. An attempt to access this address must be recognized as a
communication error (‘SDI stuck to VCC’ failure) and must cause the device to enter a fail-
safe state.

6.1.6 Write operation

The write operation starts with a command byte followed by 2 data bytes. The number of
data bytes is specified in the <SPI-frame-ID>.
Write command format

Table 46. Write command format: command byte

MSB LSB

Op Code Address
0 0 A5 A4 A3 A2 A1 A0

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ST SPI L99PM62XP

Table 47. Write command format: data byte 1

MSB LSB

D15 D14 D13 D12 D11 D10 D9 D8

Table 48. Write command format: data byte 2

MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

OC0, OC1: operating code (00 for ‘write’ mode)

A0 to A5: address bits
An attempt to write 00H at RAM address 00H is recognized as a failure (SDI stuck to GND).
The device enters a fail-safe state.

6.1.7 Format of data shifted out at SDO during write cycle

Table 49. Format of data shifted out at SDO during write cycle: global status
register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Global error Comm Not (chip reset VS Fail Fail

TSD2 TSD1 V1 Fail
flag (GEF) error or comm error) (OV/UV) safe

Table 50. Format of data shifted out at SDO during write cycle: data byte 1
MSB Previous content of addressed register LSB

D15 D14 D13 D12 D11 D10 D9 D8

Table 51. Format of data shifted out at SDO during write cycle: data byte 2
MSB Previous content of addressed register LSB

D7 D6 D5 D4 D3 D2 D1 D0

Failures are indicated by activating the corresponding bit of the <Global Status> register.
The returned data byte(s) represent(s) the previous content of the accessed register.

70/98 Doc ID 16363 Rev 4

L99PM62XP ST SPI

Figure 36. Format of data shifted out at SDO during write cycle

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6.1.8 Read operation

The read operation starts with a command byte followed by 2 data bytes. The number of
data bytes is specified in the <SPI-frame-ID>. The content of the data bytes is ‘don’t care’.
The content of the addressed register is shifted out at SDO within the same frame (‘in-frame
response’).

Read command format

Table 52. Read command format: command byte

MSB LSB

Op Code Address
0 1 A5 A4 A3 A2 A1 A0

Table 53. Read command format: data byte 1

MSB LSB

0 0 0 0 0 0 0 0

Table 54. Read command format: data byte 2

MSB LSB

0 0 0 0 0 0 0 0

OC0, OC1: operating code (01 for ‘read’ mode)

A0 to A5: address bits

Doc ID 16363 Rev 4 71/98

ST SPI L99PM62XP

6.1.9 Format of data shifted out at SDO during read cycle

Table 55. Format of data shifted out at SDO during read cycle: global status
register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Global error Comm Not (chip reset VS Fail Fail

TSD2 TSD1 V1 Fail
flag (GEF) error or comm error) (OV/UV) safe

Table 56. Format of data shifted out at SDO during read cycle: data byte 1
MSB Previous content of addressed register LSB

D15 D14 D13 D12 D11 D10 D9 D8

Table 57. Format of data shifted out at SDO during read cycle: data byte 2
MSB Previous content of addressed register LSB

D7 D6 D5 D4 D3 D2 D1 D0

Failures are indicated by activating the corresponding bit of the <Global Status> register.
The returned data byte(s) represent(s) the content of the register to be read.

Figure 37. Format of data shifted out at SDO during read cycle

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6.1.10 Read and clear status operation

The ‘Read and Clear Status’ operation starts with a command byte followed by 2 data bytes.
The number of data bytes is specified in the <SPI-frame-ID>. The content of the data bytes

72/98 Doc ID 16363 Rev 4

L99PM62XP ST SPI

is ‘don’t care’. The content of the addressed status register is transferred to SDO within the
same frame (‘in-frame response’) and is subsequently cleared.
A ‘Read and Clear Status’ operation with address 3FH clears all status registers (incl. the
<Global Status> register). The configuration register is read by this operation.

Read and clear status command format

Table 58. Read and clear status command format: command byte
MSB LSB

Op Code Address
1 01 A5 A4 A3 A2 A1 A0

Table 59. Read and clear status command format: data byte 1
MSB LSB

0 0 0 0 0 0 0 0

Table 60. Read and clear status command format: data byte 2
MSB LSB

0 0 0 0 0 0 0 0

OC0, OC1: operating code (10 for ‘read and clear status’ mode)
A0 to A5: address bits

Format of data shifted out at SDO during read and clear status operation

Table 61. Format of data shifted out at SDO during read and clear status: global
status register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Global error Comm Not (chip reset VS Fail Fail

TSD2 TSD1 V1 Fail
flag (GEF) error or comm error) (OV/UV) safe

Table 62. Format of data shifted out at SDO during read and clear status:
data byte 1
MSB Previous content of addressed register LSB

D15 D14 D13 D12 D11 D10 D9 D8

Table 63. Format of data shifted out at SDO during read and clear status:
data byte 2
MSB Previous content of addressed register LSB

D7 D6 D5 D4 D3 D2 D1 D0

Doc ID 16363 Rev 4 73/98

ST SPI L99PM62XP

Failures are indicated by activating the corresponding bit of the <Global Status> register.
The returned data byte(s) represent(s) the content of the register to be read.

Figure 38. Format of data shifted out at SDO during read and clear status operation

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6.1.11 Read device information

The device information is stored at the ROM addresses defined below and is read using the
respective operating code.

Table 64. Read device information

Op code ROM
Device information Value
OC1 OC0 address

1 1 3FH Reserved 00

<SPI frame ID>

1 1 3EH 42 Hex
includes frame width and availability of watchdog

1 1 04H to 3DH unused 00

<product code 2>

1 1 03H 4E Hex
unique product identifier
<product code 1>
1 1 02H 44 Hex
unique product identifier

<silicon version> According to

1 1 01H silicon
indicates Design Version version
<ID Header>
1 1 00H 43 Hex
device family max adress of device information

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L99PM62XP ST SPI

The <ID-Header> (ROM address 00H) indicates the product family and specifies the highest
address which contains product information

Table 65. ID-header

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 1 0 0 0 0 1 1
Family Identifier Highest address containing device information

<Family Identifier>: 01 Hex (BCD)

<Highest address>: 03 Hex

Table 66. Family identifier

Bit 7 Bit 6 Meaning

0 0 VIPower
0 1 BCD
1 0 VIPower hybrid
1 1 Tbd

The <Product Code 1> (ROM address 02H) and <Product Code 2> (ROM address 03H)
represents a unique code to identify the product name.
<Product Code 1> 44 Hex
<Product Code 2> 4E Hex
The <Silicon Version> (ROM address 01H) provides information about the silicon version
according to the table below:

Table 67. Silicon version identifier

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved Silicon version

The <SPI-frame-ID> (ROM address 3EH) provides information about the register width (1,
2, 3 bytes) and the availability of ‘Burst Mode Read’ and watchdog.

Table 68. SPI-frame-ID

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 1 0 0 0 0 1 0
BR WD X X X 32-bit 24-bit 16-bit

BR: burst-mode read (1 = burst-mode read is supported)

WD: watchdog (1 = available, 0 = not available)
32-bit, 24-bit, 16-bit: width of SPI frame (see table below)

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ST SPI L99PM62XP

<Burst Mode>: not supported

<Watchdog>: available
<Frame Width>: 24 bit

6.2 SPI registers

6.2.1 Overview
Overview command byte

Table 69. SPI register: command byte

Read/write Address

x x x x x x x x

Table 70. SPI register: mode selection

Read/write Mode selection

0 0 Write
0 1 Read
1 0 Read and clear
1 1 Read device info

Table 71. SPI register: CTRL register selection

CTRL register 1…6 CTRL register selection

0 0 0 0 0 1 CTRL register1
0 0 0 0 1 0 CTRL register2
0 0 0 0 1 1 CTRL register3
0 0 0 1 0 0 CTRL register4
0 0 0 1 0 1 CTRL register5
0 0 0 1 1 0 CTRL register6

Table 72. SPI register: STAT register selection

STAT register. 1…3 STAT register selection

0 1 0 0 0 1 STAT register1
0 1 0 0 1 0 STAT register2
0 1 0 0 1 1 STAT register3

Overview of control register data bytes

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L99PM62XP ST SPI

6.2.2 Control registers

Table 73. Overview of control registers data bytes

1st data byte <15:8> 2nd data byte <7:0>

Control register 1, data

Defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OUT OUT OUT OUT OUT OUT OUT OUT REL REL Stby Go
Function V2 V2 Res Trig
HS HS 4 4 HS_EXT 3 2 1 2 1 sel Stby

Group HS control LS Output, V2 and mode control

Control register 2, data

Defaults 0 0 0 0 0 0 0 0 0 0 1 1 1

Inp. Inp. Inp. Inp. Inp. Inp. Input Input Input WU WU WU

Function Res Res Res Res
Filt 3 Filt 3 Filt 2 Filt 2 Filt 1 Filt1 Pu/Pd 3 Pu/Pd 2 Pu/Pd 1 EN 3 EN 2 EN 1

Group Wake-up control Wake-up control

Control register 3, data

Defaults 0 0 0 0 0 0 0 0 1 1 0 0

LIN CAN Wake Wake

T1 T1 T1 T2 T2 T2 WD WD
Function Res Res Res Res WU WU timer Timer
On Per Per On Per Per time time
En En En Select

Group Timer Settings Watchdog and cyclic wake up settings

Control register 4, data

Defaults 0 0 1 1 0 0 1 1 1 1 0 1 1 0

LS V1 V1
Lin CAN
OutHS Vlock LIN CAN CAN CAN
OV/UV TxD CAN Patt.
Function Res ICMP Rec Out Res Reset Reset Pu Res Loop split Rec
shut Tout ACT wake
En En Level Level En En On Only
down_en En En

Group Control (other) Transceiver settings

Control register 5, data

Defaults 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 PWM2

PWM PWM1 PWM1 PWM1 PWM1 PWM1 PWM1 PWM1
Function Res Off- Off- Off- Off- Off- Off- Off-
Freq ON-DC ON-DC ON-DC ON-DC ON-DC ON-DC ON-DC
DC DC DC DC DC DC DC

Group PWM2 setting PWM1 setting

Control register 6, data

Defaults 1 1 1 1 1 1 1 0 0 0 0 0 0 0

PWM4 PWM4 PWM3 PWM3 PWM3 PWM3 PWM3 PWM3 PWM3

PWM4 PWM4 PWM4 PWM4 PWM4
Function Res Off- Off- Res ON- ON- ON- ON- ON- ON- ON-
Off-DC Off-DC Off-DC Off-DC Off-DC
DC DC DC DC DC DC DC DC DC

Group PWM4 setting PWM3 setting

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ST SPI L99PM62XP

Control register 1

Table 74. Control register 1: command and data bytes

Command byte 1st data byte 2nd data byte

Read/write Address
x x 0 0 0 0 0 1 Data, 8bit Data, 8 bit

Table 75. Control register 1, data bytes

1st data byte <15:8> 2nd data byte <7:0>
Defaults 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OUT OUT OUT OUT OUT OUT OUT OUT REL REL Stby Go
Function V2_2 V2_1 Res Trig
HS_2 HS_1 4_2 4_1 HS_EXT 3 2 1 2 1 sel Stby

Group HS control LS Output, V2 and mode control

Table 76. Control register 1, bits

Bit Name Comment

15 OUTHS Select mode of OUTHS

14 OUTHS_EXT OUTHS_2 OUTHS_1 Mode

0 0 0 HS off
0 0 1 HS cyclic on with timer 1
0 1 0 HS controlled by PWM4 Active and
0 1 1 HS cyclic on with Timer 2 standby mode

1 1 0 PWM3(1)
1 x 1 HS on

1) PWM4 (CR6) must be unequal 0% in order to enable PWM3

To turn off OUT4, we recommend to use the setting 'HS Off' (OUT4_1 = 0, OUT4_2 = 0)

13 OUT4 Select mode of OUT4

12 OUT4_2 OUT4_1 Mode

0 0 HS off
0 1 HS on
HS controlled Active and standby mode
1 0
by PWM4
HS cyclic on
1 1
with Timer 2

11 OUTHS_EXT Extended function of OUTHS; see table OUTHS

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Table 76. Control register 1, bits (continued)

Bit Name Comment

10 OUT3 Select mode of OUT3

OUT3 Mode

Active and
0 Select FSO
standby mode
1 Select PWM3

9 OUT2 Select mode of OUT2

OUT2 Mode

0 Select PWM2 Active and

1 Select timer2 standby mode

8 OUT1 Select mode of OUT1

OUT1 Mode

0 Select PWM1 Active and

1 Select timer1 standby mode

7 REL2 Select mode of REL2

REL2 Mode

Active and
0 REL2 off
standby mode
1 REL2 on Active mode

6 REL1 Select mode of REL1

REL1 Mode

Active and
0 REL1 off
standby mode
1 REL1 on Active mode

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ST SPI L99PM62XP

Table 76. Control register 1, bits (continued)

Bit Name Comment

5 V2

4 V2_2 V2_1

0 0 V2 OFF in all modes

V2 ON in active mode; OFF in V1/VBAT
0 1
standby mode
V2 ON in Active/V1 standby mode; OFF in
1 0
VBAT standby mode
1 1 V2 ON in all modes

3 RES Reserved
2 STBY_SEL Select standby mode
0 VBAT standby mode
1 V1standby mode

1 GO_STBY Execute standby mode

0 No action
1 Execute standby mode

0 TRIG Trigger Bit for Watchdog

Control register 2

Table 77. Control register 2: command and data bytes

Command byte 1st data byte 2nd data byte

Read/write Address
x x 0 0 0 0 1 0 Data, 8bit Data, 8 bit

Table 78. Control register 2, data bytes

1st data byte <15:8> 2nd data byte <7:0>
Defaults 0 0 0 0 0 0 0 0 0 1 1 1

Wu3 Wu3 WU2 WU2 WU1 WU1 WU3 WU2 WU1 WU3 WU2 WU1
Function Res Res Res Res
Filt_MSB Filt_LSB Filt_MSB Filt_LSB Filt_MSB Filt_LSB Pu/Pd Pu/Pd Pu/Pd EN EN EN

Group Wakeup control Wakeup control

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L99PM62XP ST SPI

Table 79. Control register 2, bits

Bit Name Comment

15 Res Reserved
14 Res Reserved
13, 12 WU3_Filt Wakeup filter configuration

11, 10 WU2_Filt MSB LSB

9, 8 WU1_Filt 0 0 Static, 64 µs
0 1 Enabled with timer 2; 80 µs blank
1 0 Enabled with timer 2; 800 µs blank
1 1 Enabled with timer 1; 800 µs blank

7 Res Reserved
6 WU3_Pu/Pd Pull up or pull down configuration
5 WU2_Pu/Pd 0 Pull down
4 WU1_Pu/Pd 1 Pull up

3 Res Reserved
2 WU3_EN Enable Wake up source
1 WU2_EN 0 Disable
0 WU1_EN 1 Enable

Control register 3

Table 80. Control register 3: command data bytes

Command byte 1st data byte 2nd data byte

Read/write Address
x x 0 0 0 0 1 1 Data, 8bit Data, 8 bit

Table 81. Control register 3, data bytes

1st data byte <15:8> 2nd data byte <7:0>
Defaults 0 0 0 0 0 0 0 0 0 1 1 0 0

T1 T1 T2 T2 WD WD LIN CAN Wake Wake

T1 T2
Function Res Per Per Res Per Per Res Res time time WU WU timer timer
On On
MSB LSB MSB LSB MSB LSB En En En select

Group Timer Settings Watchdog and cyclic wake up settings

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ST SPI L99PM62XP

Table 82. Control register 3, bits

Bit Name Comment

15 RES Reserved
14 T1_On Timer 1 “ON” time selections
0 10 ms
1 20 ms

13 T1_Per_MSB Timer 1 period selection

12 T1_Per_LSB

MSB LSB

0 0 1s
0 1 2s
1 0 3s
1 1 4s
Timer 1 is restarted with a valid write command to control register 3
11 Res
10 T2_On Timer 2 “ON” time selection
0 0.1 ms
1 1 ms

9 T2_Per_MSB Timer 2 period selection

8 T2_Per_LSB

MSB LSB

0 0 10 ms
0 1 50 ms
1 0 100 ms
1 1 200 ms
Timer 2 is restarted with a valid write command to control register 3
7 Res Reserved
6 Res Reserved

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L99PM62XP ST SPI

Table 82. Control register 3, bits (continued)

Bit Name Comment

5 WD_time_MSB Trigger window selection

4 WD_time_LSB

MSB LSB

0 0 10 ms
0 1 20 ms
1 0 50 ms
1 1 200 ms

3 LIN_WU_En Enable LIN as wake up source

0 Disabled
1 Enabled

2 CAN_WU_En Enable CAN as wake up source

0 Disabled
1 Enabled

Enable wake up by timer from V1 standby mode (Interrupt) or VBAT standby Mode
1 Wake_timer_En
(Nreset)
0 Disabled
1 Enabled

0 Wake_timer_select Timer selection for timer interrupt / wake-up of µC by timer

0 Timer 2
1 Timer 1

Control register 4

Table 83. Control register 4: command and data bytes

Command byte 1st data byte 2nd data byte

Read/Write Address
x x 0 0 0 1 0 0 Data, 8bit Data, 8 bit

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ST SPI L99PM62XP

Table 84. Control register 4, data bytes

1st data byte <15:8> 2nd data byte <7:0>
Defaults 0 0 1 0 1 0 0 1 1 1 1 0 1 1 0

LS Lin CAN
OutHS Vlock V1 V1 LIN CAN CAN CAN
OV/UV TxD CAN Patt.
Function RES ICMP Rec Out_en RES Reset Reset Pu Res Loop split Rec
shut Tout ACT wake
En Lev_2 Lev_1 En En On only
down_en En En

Group Control (other) Transceiver settings

Table 85. Control register 4, bits

Bit Name Comment

15 Res Reserved; must be set to zero

14 Icmp V1 load current supervision
Enabled; Watchdog is disabled in V1 Standby when the
0
V1loadcurrent < Icmpthreshold
Disabled; Watchdog is automatically disabled when V1
1
standby is entered

13 OUTHS_rec_en Overcurrent Auto recovery mode for OUTHS

0 Disabled
1 Enabled

12 Vlock_out_en Voltage lock out: OV/UV status

Over/under voltage status recovers automatically when
0
condition disappears
Over/under voltage status is latched until a read and clear
1
command is performed

11 Res Reserved
LS_OV/UV
10 Shutdown of low-side drivers in case of over-/under voltage
shut_down_en
0 No shutdown of low-sides in case of over/under voltage
1 Shutdown low-sides in case of over/under voltage

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L99PM62XP ST SPI

Table 85. Control register 4, bits (continued)

Bit Name Comment

9 V1Reset_level_1 Select reset level

8 V1Reset_level_2

V1RSTlev_2 V1RSTlev_1 V1 reset level

0 0 4.6 V

0 1 4.35 V

1 0 4.1 V

1 1 3.8 V

7 LIN_PU_EN Enable internal Lin pull up

0 No LIN master pull-up
1 LIN master pull-up

6 Res Must be written to ‘1’

5 Lin_TxD_Tout_En Enable / disable monitoring via TxD
0 No TxD monitoring
TxD monitoring; LIN transmitter is switched off if TXDL is
1
dominant for t > 12 ms

4 CAN_ACT Activate CAN transceiver

0 CAN transceiver deactivated
Active mode
1 CAN transceiver activated

3 CAN_Loop_En Enable looping of CANTX to CANRXD in V1 standby0

0 No looping
1 TXDC is looped to RXDC in V1 standby

2 CAN_Patt_wake_En Enable pattern wake up for CAN

0 No pattern wake up
1 Pattern wake up

1 CAN_split_On Enable SPLIT termination for CAN

0 Split termination disabled
Active mode
1 Split termination enabled

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ST SPI L99PM62XP

Table 85. Control register 4, bits (continued)

Bit Name Comment

0 CAN_Rec_only Enable CAN receive only mode

0 CAN in transceiver mode
Active mode
1 CAN in receive only mode

Control register 5

Table 86. Control register 5: command and data bytes

Command byte 1st data byte 2nd data byte

Read/write Address
x x 0 0 0 1 0 1 Data, 8bit Data, 8 bit

Table 87. Control register 5, data bytes

1st data byte <15:8> 2nd data byte <7:0>
Defaults 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 PWM2

PWM PWM1 PWM1 PWM1 PWM1 PWM1 PWM1 PWM1
Function Res Off- Off- Off- Off- Off- Off- Off-
Freq ON-DC ON-DC ON-DC ON-DC ON-DC ON-DC ON-DC
DC DC DC DC DC DC DC

Group PWM2 setting PWM1 setting

Table 88. Control register 5, bits

Bit Name Comment

15 RES Reserved; must be set to zero

PWM2_
14
Off_DC_6

PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 PWM2

PWM2_
13 OFF_ OFF_ OFF_ OFF_ OFF_ OFF_ OFF_ PWM duty cycle
Off_DC_5
DC_6 DC_5 DC_4 DC_3 DC_2 DC_1 DC_0

PWM2_
12 1 1 1 1 1 1 1 0%, HS OFF
Off_DC_4
PWM2_
11 ...
Off_DC_3
PWM2_
10 0 0 0 0 0 1 0 98.5%
Off_DC_2
PWM2_
9 0 0 0 0 0 0 1 99.25%
Off_DC_1
PWM2_
8 0 0 0 0 0 0 0 100% HS ON
Off_DC_0

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L99PM62XP ST SPI

Table 88. Control register 5, bits (continued)

Bit Name Comment

PWM_
7 Select PWM frequency
FREQ
0 128 Hz
1 256 Hz

PWM1_
6
ON_DC_6

PWM1 PWM1 PWM1 PWM1 PWM1 PWM1 PWM1

PWM1_
5 ON_ ON_ ON_ ON_ ON_ ON_ ON_ PWM duty cycle
ON_DC_5
DC_6 DC_5 DC_4 DC_3 DC_2 DC_1 DC_0

PWM1_
4 1 1 1 1 1 1 1 100%, HS ON
ON_DC_4
PWM1_
3 ...
ON_DC_3
PWM1_
2 0 0 0 0 0 1 0 1.5%
ON_DC_2
PWM1_
1 0 0 0 0 0 0 1 0.75%
ON_DC_1
PWM1_
0 0 0 0 0 0 0 0 0% HS OFF
ON_DC_0

Control register 6

Table 89. Control register 6: command and data bytes

Command byte 1st data byte 2nd data byte

Read/Write Address
x x 0 0 0 1 1 0 Data, 8bit Data, 8 bit

Table 90. Control register 6, data bytes

1st data byte <15:8> 2nd data byte <7:0>
Defaults 1 1 1 1 1 1 1 0 0 0 0 0 0 0

PWM4 PWM4 PWM4 PWM4 PWM4 PWM4 PWM4 PWM3 PWM3 PWM3 PWM3 PWM3 PWM3
PWM3
Function Res Off_ Off_ Off_ Off_ Off_ Off_ Off_ Res ON_ ON_ ON_ ON_ ON_ ON_
ON-DC_3
DC_6 DC_5 DC_4 DC_3 DC_2 DC_1 DC_0 DC_6 DC_5 DC_4 DC_2 DC_1 DC_0

Group PWM4 setting PWM3 setting

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ST SPI L99PM62XP

Table 91. Control register 6, bits

Bit Name Comment

15 RES Reserved; must be set to zero

PWM4_
14
Off_DC_6

PWM4 PWM4 PWM4 PWM4 PWM4 PWM4 PWM4

PWM4_
13 OFF_ OFF_ OFF_ OFF_ OFF_ OFF_ OFF_ PWM4 duty cycle
Off_DC_5
DC_6 DC_5 DC_4 DC_3 DC_2 DC_1 DC_0

PWM4_
12 1 1 1 1 1 1 1 0%, HS OFF
Off_DC_4
PWM4_
11 ...
Off_DC_3
PWM4_
10 0 0 0 0 0 1 0 98.5%
Off_DC_2
PWM4_
9 0 0 0 0 0 0 1 99.25%
Off_DC_1
PWM4_
8 0 0 0 0 0 0 0 100% HS ON
Off_DC_0

7 RES Reserved; must be set to zero

PWM3_
6
ON_DC_6

PWM3 PWM3 PWM3 PWM3 PWM3 PWM3 PWM3

PWM3_
5 ON_ ON_ ON_ ON_ ON_ ON_ ON_ PWM3 duty cycle
ON_DC_5
DC_6 DC_5 DC_4 DC_3 DC_2 DC_1 DC_0

PWM3_
4 1 1 1 1 1 1 1 100%, HS ON
ON_DC_4
PWM3_
3 ...
ON_DC_3
PWM3_
2 0 0 0 0 0 1 0 1.5%
ON_DC_2
PWM3_
1 0 0 0 0 0 0 1 0.75%
ON_DC_1
PWM3_
0 0 0 0 0 0 0 0 0% HS OFF
ON_DC_0

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L99PM62XP ST SPI

6.2.3 Status registers

Table 92. Overview of status register data bytes

1st data byte <15:8> 2nd data byte <7:0>

Status register 1, data <15:0>

OL OL OL OL OL V2 V2 OC OC OC OC OC OC OC
Function UV OV
HS OUT4 OUT3 OUT2 OUT1 fail short HS Out4 Out3 OUT2 Out1 Rel2 Rel1

Group Diagnosis 1 Diagnosis 2

Status register 2, data <15:0>

Wake LIN LIN LIN CAN CAN CAN CAN
WU3 WU2 WU1 WU3 WU2 WU1 Wake Wake
Function Timer perm. TxD perm. RxD perm. perm. TxD
state state state wake wake Wake CAN LIN
int dom. perm dom. rec. perm rec. rec. dom. perm dom

Group Diagnosis 3 Diagnosis 4

Status register 3, data <15:0>

Forced
Forced WD WD
Device Device V1 V1 V1 V1 WD WD WD WD sleep
Function TSD1 TW sleep timer timer
state state fail restart restart restart fail fail fail fail TSD2
WD state state
SHTV1

Group Diagnosis 5 Diagnosis 6

Table 93. Global status register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
NOT (chip reset or
Communication

i.e. cold start (3)

comm. error)
Global error

Fail safe(6)
Hex
Vs fail(5)
(OV/UV)
TSD2(4)
error(2)

V1 Fail
flag(1)

TSD1

value

Active high/low High High Low High High High High High
Default value in
normal mode -
after correct WD
0 0 1 0 0 0 0 0 20
trigger or after
read & clear on
error flags

Power ON 1 0 0 0 0 0 0 0 80

Power ON
1 0 0 0 0 0 1 0 82
weak battery(7)
Communication
1 1 0 0 0 0 0 0 C0
error
Vs over or
1 0 1 0 0 0 1 0 A2
under-voltage

WD failure 1 0 1 0 0 0 0 1 A1

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ST SPI L99PM62XP

Table 93. Global status register (continued)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

NOT (chip reset or

Communication

i.e. cold start (3)

comm. error)
Global error

Fail safe(6)
Hex

Vs fail(5)
(OV/UV)
TSD2(4)
error(2)

V1 Fail
flag(1)

TSD1
value

SPI error (DI

1 0 1 0 0 0 0 1 A1
stuck)

TSD1 1 0 1 0 1 0 0 0 A8

TSD2 1 0 1 1 1 0 0 1 B9

V1 fail 1 0 1 0 0 1 0 0 A4

Other device
1 0 1 0 0 0 0 0 A0
failure(8)
1. The following status bits are reported in the global error flag:
Global status register: Bits 0 - 6
Status register 1: Bits 0 – 10
Status register 3: Bits 2, 3, 15
2. Invalid CLOCK COUNT.
3. Cleared with CLR command on SR3.
4. Cleared with “READ and CLEAR” on SR3 (-> TSD1).
5. Diagnosis bit only, Vs Fail is not a fail-safe event; cleared by read&clear. Bit is automatically cleared at (Vs > VsUV) and.
(Vs < VsOV) if Vlock_out_en = 0.
6. Cleared with a valid WD trigger (WD fail) or by clearing the corresponding status register related to failure.
7. Slow Vs ramp-up (Vs undervoltage is filtered with 64 µs after Power-on reset).
8. The global error flag is raised due to a failure condition which is not reported in the global status register. The Failure is
reported in the status registers 1 – 3.

Status register 1

Table 94. Status register 1: command and data bytes

Command byte 1st data byte 2nd data byte

Read/write Address Bit <15:8> Bit<7:0>

x x 0 1 0 0 0 1 Data, 8bit Data, 8 bit

Table 95. Status register 1, data bytes

1st data byte <15:8> 2nd data byte <7:0>
OL OL OL OL OL V2 V2 OC OC OC OC OC OC OC
Function UV OV
HS OUT4 OUT3 OUT2 OUT1 fail short HS Out4 Out3 OUT2 Out1 Rel2 Rel1

Group Diagnosis 1 Diagnosis 2

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L99PM62XP ST SPI

Table 96. Status register 1, bits

Bit Name Comment Information storage

15 OL_HS
14 OL_OUT4
Open-load event occurred
13 OL_OUT3 Bit is latched until a “read and clear” access
since last read out
12 OL_OUT2
11 OL_OUT1
10 UV

VLOCKOUTEN
Information storage
(CR4)
Under voltage event on VS automatically reset when UV
occurred since last read out 0
condition disappears
Bit is latched until a “read and clear”
1
access

V2 fail (V2 < 2 V for t> 2 µs)

9 V2_fail event occurred since last Bit is latched until a “Read and clear” access
readout
V2 short (V2 < 2 V for t > 4ms
8 V2_short during start up) event Bit is latched until a “Read and clear” access
occurred since last readout
7 OV

VLOCKOUTEN
Information storage
(CR4)
Over voltage event on VS automatically reset when OV
occurred since last read out 0
condition disappears
Bit is latched until a “read and clear”
1
access

6 OC_HS
5 OC_OUT4
4 OC_OUT3
Over current event occurred
3 OC_OUT2 Bit is latched until a “read and clear” access
since last read out
2 OC_OUT1
1 OC_REL2
0 OC_REL1

Doc ID 16363 Rev 4 91/98

ST SPI L99PM62XP

Status register 2

Table 97. Status register 2: command and data bytes

Command byte 1st data byte 2nd data byte

Read/write Address Bit <15:8> Bit<7:0>

x x 0 1 0 0 1 0 Data, 8bit Data, 8 bit

Table 98. Status register 2, data bytes

1st data byte <15:8> 2nd data byte <7:0>

WU3 WU2 WU1 WU3 WU2 WU1 Wake Wake Wake LIN LIN LIN CAN CAN CAN CAN
Function Timer perm. TxD perm. RxD perm. perm. TxD
state state state wake wake wake CAN LIN
int dom. perm dom. rec. perm rec. rec. dom. perm dom

Group Diagnosis 3 Diagnosis 4

Table 99. Status register 2, bits

Bit Name Comment Information storage

15 WU3_state
14 WU2_state State of WUx input; “Live bits” not clearable
13 WU1_state
12 WU3_wake
11 WU2_wake
10 WU1_wake
Shows wake up source (‘1’ = wake-up)
9 WAKE_CAN
8 WAKE_LIN
7 Wake_TIMER_int
6 LIN_perm_DOM LIN bus is dominant for t > 12 ms
TxDL pin is dominant for t > 12 ms;
5 LIN_TxD_perm_DOM Bits are latched until a “Read and
Transmitter is disabled
clear” access
LIN bus does not follow TxDL within
4 LIN_perm_REC
40 µs; Transmitter is disabled
RxDC has not followed TxDC for 4 times;
3 CAN_RxD_perm_rec
Transmitter is disabled
CAN has not followed TxDC for 4 times;
2 CAN_perm_REC
Transmitter is disabled
1 CAN_perm_DOM CAN bus is dominant for t > 700 µs
TxDC pin is dominant for t > 700 µs;
0 CAN_TxD_perm_DOM
Transmitter is disabled

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L99PM62XP ST SPI

Status register 3

Table 100. Status register 3: command and data bytes

Command byte 1st data byte 2nd data byte

Read/write Address Bit <15:8> Bit<7:0>

x x 0 1 0 0 1 1 Data, 8bit Data, 8 bit

Table 101. Status register 3, data bytes

1st data byte <15:8> 2nd data byte <7:0>
Forced
Forced WD WD
Device Device V1 V1 V1 V1 WD WD WD WD sleep
Function TSD1 TW sleep timer timer
state_2 state_1 fail restart_2 restart_1 restart_0 fail_3 fail_2 fail_1 fail_0 TSD2
WD state_1 state_0
SHTV1

Group Diagnosis 5 Diagnosis 6

Table 102. Status register 3, bits

Bit Name Comment Information storage

15 TSD1 Bit is latched until a

Thermal warning / shutdown1 occurred since last readout
14 TW “read and clear access”

13 State from which the device woke up

State from Bit is latched until a

which the “read and clear access”
12 Device state_2 Device state_1 after a “read and clear
device woke
up access”, the device
state is updated
Device_state 0 0 Active after a wake up, device
0 1 V1 standby state is
01: V1 standby
1 0 VBAT standby
or
1 1 Flash 10: VBAT standby

Bit is latched until a

11 V1_fail V1 fail (V1 < 2 V for t > 2 µs) event occurred since last read out
“read and clear access”
10 V1_restart_2 Bits are not clearable;
Number of TSD2 events which caused a restart of V1 is cleared automatically
9 V1_restart_1 regulator if no additional TSD2
(7 TSD2 events forces the device into VBAT standby) event occurs within 1
8 V1_restart_0
min.
7 WD_fail_3
6 WD_fail_2 Number of missing watchdog triggers Bits are not clearable;
(15 missing watchdog trigger forces the device into VBAT is cleared with a proper
5 WD_fail_1 standby) Watchdog trigger
4 WD_fail_0

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ST SPI L99PM62XP

Table 102. Status register 3, bits (continued)

Bit Name Comment Information storage

Device was forced to VBAT standby mode because of multiple

3 Forced_sleep_WD
watchdog errors
Device was forced to VBAT standby or multiple thermal Bits are latched until a
Forced_sleep_TSD shutdown events read and clear access
2
2_SHTV1 or
a short on V1 during startup.
1 WD_timer_state_1 Status of watchdog counter of selected watchdog timing
0 WD_timer_state_0

WD_timer_state_1 WD_timer_state_0 Counter

0 0 0 – 33% Bits are not clearable

0 1 33 – 66%
1 1 66 – 100%

94/98 Doc ID 16363 Rev 4

L99PM62XP Package and packing information

7 Package and packing information

7.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

7.2 PowerSSO-36 package information

Figure 39. PowerSSO-36 package dimensions

AG00066V1

Doc ID 16363 Rev 4 95/98

Package and packing information L99PM62XP

Table 103. PowerSSO-36 mechanical data

Millimeters
Symbol
Min. Typ. Max.

A 2.15 — 2.45

A2 2.15 — 2.35

a1 0 — 0.1

b 0.18 — 0.36

c 0.23 — 0.32

D 10.10 — 10.50

E 7.4 — 7.6

e — 0.5 —

e3 — 8.5 —

F — 2.3 —

G — — 0.1

H 10.1 — 10.5

h — — 0.4

k 0° — 8°

L 0.55 — 0.85

M — 4.3 —

N — - 10°

O — 1.2 —

Q — 0.8 —

S — 2.9 —

T — 3.65 —

U — 1.0 —

X 4.1 — 4.7

Y 6.5 — 7.1

96/98 Doc ID 16363 Rev 4

L99PM62XP Revision history

8 Revision history

Table 104. Document revision history

Date Revision Change

14-Dec-2009 1 Initial release.

Updated Table 5: Fail safe conditions and exit modes.
Table 12: Supply and supply monitoring:
– Updated IV(BAT)CS and IV(BAT)CW max value from 110µA to 125µA
Table 19: Output (OUT_HS):
– Updated tdON min value from 10µs to 5µs.
18-Dec-2009 2
Table 20: Outputs (OUT1...4):
– Updated IOLD min value from 1mA to 0.9mA and max value from
4mA to 4.5mA
Table 39: CSN timing:
– Added tCSNfail parameter.
Updated footnote on Table 21: Relay drivers
29-Nov-2011 3 Updated Figure 39: PowerSSO-36 package dimensions
Updated Table 103: PowerSSO-36 mechanical data
19-Sep-2013 4 Updated disclaimer.

Doc ID 16363 Rev 4 97/98

 L99PM62XP

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