Licenciado para - Instructiva - 30547439000108 - Protegido por Eduzz.

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ESMT/EMP AD82588
2x15W Stereo / 1x 30W Mono
Digital Audio Amplifier with 18 Bands EQ

Features z LV Under-voltage shutdown and HV Under-voltage

2
z 16/18/20/24-bits input with I S, Left-alignment detection
and Right-alignment data format z Short-circuit protection
z PSNR & DR(A-weighting) z Over-temperature protection
Loudspeaker: 94dB (PSNR), 103dB (DR) @24V z Power saving mode
z Multiple sampling frequencies (Fs) z Support initial EEPROM setting
32kHz / 44.1kHz / 48kHz and
64kHz / 88.2kHz / 96kHz and Applications
128kHz / 176.4kHz / 192kHz z CD and DVD
z System clock = 64x, 128x, 192x, 256x, 384x, z TV audio
512x, 576x, 768x, 1024x Fs z Car audio
64x~1024x Fs for 32kHz / 44.1kHz / 48kHz z Boom-box
64x~512x Fs for 64kHz / 88.2kHz / 96kHz z MP3 docking systems
64x~256x Fs for 128kHz / 176.4kHz / 192kHz z Powered speaker
z Supply voltage z Wireless audio
3.3V for digital circuit
10V~26V for loudspeaker driver Description
z Loudspeaker output power for stereo at 24V AD82588 is a digital audio amplifier capable of
15W x 2CH into 4Ω @0.17% THD+N driving a pair of 8Ω, 15W or a single 4Ω, 30W
z Loudspeaker output power for mono at 24V operating at 24V supply.
30W x 1CH into 4Ω @0.095% THD+N
AD82588 can provide advanced audio processing
z Sound processing including：
capabilities, such as volume control, 18 bands speaker
18 bands parametric speaker EQ
EQ, audio mixing, 3D surround and Dynamic Range
Volume control (+24dB~-103dB, 0.125dB/step),
Control (DRC). These functions are fully
Dynamic range control 2
programmable via a simple I C control interface.
Power Clipping
Robust protection circuits are provided to protect
3D surround sound
AD82588 from damage due to accidental erroneous
Channel mixing
operating condition. AD82588 is more tolerant to noise
Automatic Zero-detection mute and noise gate
and PVT (Process, Voltage, and Temperature)
Bass/Treble tone control
variation than the analog Class-AB or Class-D audio
Bass management crossover filter
amplifier counterpart implemented by analog circuit
DC-blocking high-pass filter
design. AD82588 is pop free during instantaneous
z Anti-pop design
power switch because of its built-in, robust anti-pop
z Over-temperature protection
circuit.
z I2C control interface with selectable device
address
The output stage is flexibly configurable for stereo
z Support hardware and software reset
channel or mono applications.
z Internal PLL

Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc. Publication Date: Dec. 2012
Revision: 0.2 1/52
Licenciado para - Instructiva - 30547439000108 - Protegido por Eduzz.com

ESMT/EMP AD82588
Pin Assignment

SDATA1 1 36 LINEIN
MS 2 35 LREX
PLL 3 34 RESET
CFG0 4 33 ERROR
CFG1 5 32 PD
CLK_OUT 6 31 DVDD
DGND 7 30 DGND
DVDD 8 29 DEF
SDATA0 9 28 SA1
LRCIN 10 27 SA0
BCLK 11 26 SCL
MCLK 12 25 SDA

Pin Description

PIN NAME TYPE DESCRIPTION CHARACTERISTICS

1 SDATA1 I Serial audio data input 1 Schmitt trigger TTL input buffer
2 MS I EEPROM selection Schmitt trigger TTL input buffer
3 PLL I PLL enable, low active Schmitt trigger TTL input buffer
4 CFG0 I Stereo/Mono configuration pin Schmitt trigger TTL input buffer
5 CFG1 I Stereo/Mono configuration pin Schmitt trigger TTL input buffer
6 CLK_OUT O Clock output from PLL TTL output buffer
7 DGND P Digital Ground
8 DVDD P Digital Power
9 SDATA0 I Serial audio data input 0 Schmitt trigger TTL input buffer
10 LRCIN I Left/Right clock input (Fs) Schmitt trigger TTL input buffer
11 BCLK I Bit clock input (64Fs) Schmitt trigger TTL input buffer
12 MCLK I Master clock input Schmitt trigger TTL input buffer
13 N.C.
14 VDDS1 P Subwoofer1 channel supply
15 N.C. O
16 GNDS1 P Subwoofer1 channel ground
17 N.C. O
18 VDDS1 P Subwoofer1 channel supply
19 VDDS2 P Subwoofer2 channel supply

Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc. Publication Date: Dec. 2012
Revision: 0.2 2/52
Licenciado para - Instructiva - 30547439000108 - Protegido por Eduzz.com

ESMT/EMP AD82588
20 N.C. O
21 GNDS2 P Subwoofer2 channel ground
22 N.C. O
23 VDDS2 P Subwoofer2 channel supply
24 N.C.
25 SDA I/O I2C bi-directional serial data Schmitt trigger TTL input buffer
2
26 SCL I/O I C serial clock input Schmitt trigger TTL input buffer
2
27 SA0 I I C select address 0 Schmitt trigger TTL input buffer
28 SA1 I I2C select address 1 Schmitt trigger TTL input buffer
Initial default volume setting
29 DEF I Schmitt trigger TTL input buffer
(1:Un-Mute ; 0:Mute)
30 DGND P Digital Ground
31 DVDD P Digital Power
32 PD I Power down, low active Schmitt trigger TTL input buffer
33 ERROR O Error status, low active Open-drain output
34 RESET I Reset, low active Schmitt trigger TTL input buffer
Left/Right channel exchange
35 LREX I Schmitt trigger TTL input buffer
(0:Unchanged ; 1:Exchanged)
Select input data
36 LINEIN I Schmitt trigger TTL input buffer
(0:SDATA0 ; 1:SDATA1)
37 N.C.
38 VDDRA P Right channel supply A
39 RA O Right channel output A
40 GNDR P Right channel ground
41 RB O Right channel output B
42 VDDRB P Right channel supply B
43 VDDLB P Left channel supply B
44 LB O Left channel output B
45 GNDL P Left channel ground
46 LA O Left channel output A
47 VDDLA P Left channel supply A
48 N.C.

Elite Semiconductor Memory Technology Inc./Elite MicroPower Inc. Publication Date: Dec. 2012
Revision: 0.2 3/52