Course code: ECEP2 1407
M.Tech (VLSI&ES) – 2nd Semester
Semester End Regular Examination
SEPT. 2013
LOW POWER VLSI DESIGN
M.Tech (VLSI & Embedded Systems)
Time: Three hours Maximum: 60 marks
Section I : Answer all questions.
Section II & III: Answer any TWO questions from each section and all questions carry equal marks with equal
division of marks.
SECTION I
(Covering all 8 Units of syllabus)
1. (6x2M=12M)
a “BiCMOS Technology is preferable for low power design” justify it 2M
b Consider threshold voltage of n-channel MOSFET is 2V . if boron is added to the substrate, 2M
threshold voltage increases or decreases. Justify your answer.
c What is the difference between butted and non-butted emitter devices. 2M
d What are static and dynamic hazards. 2M
e Mention the sources of software power dissipation. 2M
f Draw the CMOS logic gate for 3-input NOR gate. 2M
SECTION II
(Covering 1st, 2nd, 3rd & 4th Units of syllabus)
Questions can have 1 or max of 2 bits of 6M each
a What are the limitations of low power design? Explain it in detail
2 12M
b Explain the process sequence to obtain high performance BiCMOS digital circuits.
a MOSFET is effected by the hot-carrier effect, how this can be reduced?
3 12M
b Explain the role of LOCOS in isolation techniques.
Draw the structure of poly emitter high performance BiCMOS structure and explain the same.
4 12M
Give the process flow for the same.
a What is the use of transistor reordering and transistor sizing in low power synthesis? Explain it.
5 12M
b Explain the circuit topology of precharged high DCSL.
SECTION III
(Covering 5th, 6th, 7th & 8th Units of syllabus)
Questions can have 1 or max of 2 bits of 6M each
a Draw and explain the circuit topology of 4T SRAM cell.
6 12M
b Explain about energy recovery circuit design.
a Explain the operation of emitter follower driver configuration.
7 b How do you get full swing in CMOS/Bipolar logic circuits? Explain the methods to get full 12M
swing.
a Draw the circuits and explain about two types of feedback type BiCMOS digital circuits.
8 12M
b Explain about ESD free BiCMOS digital circuit.
a Explain about the optimization and performance themes of latches.
9 12M
b What are the quality measures for latches and flip-flops.
