EEE2039 Analogue Electronic Design

Module E Class
Final Exam 1 SOLUTIONS

Assoc. Prof. Daniel W. O‘Hagan

2nd Semester 2015
 Contents

 SOLUTIONS

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QUESTION 1
SOLUTION 1
Question 1

4
Question 1 continued

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(1.1) Formation of the Depletion Region

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 (1.1) Formation of the Depletion Region
 The free electrons in the n region randomly drift in all directions.
 The instant that the pn junction forms, the free electrons near the junction in the n
region begin to diffuse across the junction into the p region where they combine
with holes near the junction region.
 When the pn junction is formed, the n region loses free electrons as they diffuse
across the junction. This creates a layer of positive charges (pentavalent ions)
near the junction.
 As the electrons move across the junction, the p region loses holes as the
electrons and holes combine. This creates a layer of negative charges (trivalent
ions) near the junction.
 These two layers of positive and negative charges form the depletion region.
 The term depletion refers to the fact that the region near the pn junction is
depleted of charge carriers (electrons and holes) due to diffusion across the
junction.
 After the initial surge of free electrons across the pn junction, the depletion region
has expanded to a point where equilibrium is established and there is no further
diffusion of electrons across the junction

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(1.2) Circuit Representation of Forward Bias

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(1.3) Basic rectifier Circuit

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(1.4) Solving for the Forward Biased Diode

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(1.5) Bridge Rectifier

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 (1.5) PIV

Vp(out) = Vp(sec) – 1.4 = 17 – 1.4 = 15.6 V

PIV = Vp(out) + 0.7 = 15.6 + 0.7 = 16.3 V

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QUESTION 2
SOLUTION 2
 (2.1) BJT Basic Operation of npn
 The heavily doped n-type emitter region has a very high density of
conduction-band (free) electrons.
 These free electrons easily diffuse through the forward-based BE junction into
the lightly doped and very thin p-type base region.
 The base has a low density of holes, which are the majority carriers.
 Most of the free electrons that have entered the base do not recombine with
holes because the base is very thin.
 As the free electrons move toward the reverse-biased BC junction, they are
swept across into the collector region by the attraction of the positive collector
supply voltage.
 The free electrons move through the collector region, into the external circuit,
and then return into the emitter region along with the base current.
 The emitter current is slightly greater than the collector current because of the
small base current that splits off from the total current injected into the base
region from the emitter.

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(2.1) BJT Basic Operation of npn

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 (2.2) Regions of Operation

(i) Saturation Region: Is the sloping part of the characteristic curve where the
voltage across the transistor, VCE, rises from 0 V to a few tenths of a Volt. In this
region, both BC and BE junctions are forward-biased and the collector diode has
insufficient positive voltage to collect the free-electrons injected from the emitter
in to the base.

(ii) Cutoff Region: When the base current, IB = 0. both the BC and BE
junctions are reverse-biased. Under this condition, there is a very small amount
of collector leakage current, ICEO, which is often neglected so that VCE = VCC.

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(2.3) DC Equivalent Circuit

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(2.3) DC Collector Voltage
(2.4) AC Equivalent Circuit
(2.5) AC Collector Voltage
(2.5) AC Collector Voltage
QUESTION 3
SOLUTION 3
 (3.1) D-MOSFET

 The drain and source are diffused into the substrate material and then
connected by a narrow channel adjacent to the insulated gate.

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 (3.1) D-MOSFET

 The D-MOSFET can operate with either

positive or negative gate voltages.
 This is indicated on the general n-
channel MOSFET transfer characteristic
curve.
 The point on the curves where VGS = 0
corresponds to IDSS.
 The point where ID = 0 corresponds to
VGS(off).
 As with the JFET, VGS(off) = VP.
 The square-law expression for the JFET
curve also applies to the D-MOSFET
curve.

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 (3.2 i) JFET Drain Characteristic Curve

 Pinch-Off Voltage: For VGS = 0 V, the value of VDS at which ID becomes essentially
constant (point B) is the pinch-off voltage, VP. For a given JFET, VP has a fixed value.
 Breakdown: As shown in the graph in (b), breakdown occurs at point C when ID begins
to increase very rapidly with any further increase in VDS.

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 (3.2 ii) E-MOSFET Drain Characteristic Curve

 The E-MOSFET uses only channel

enhancement.
 Therefore, an n-channel device requires a
positive VGS, and a p-channel device
requires a negative VGS.
 Shown is the general transfer characteristic
curve for the n-type E-MOSFET.
 There is no drain current when VGS = 0.
 Notice also that there is ideally no drain
current until VGS reaches a certain non-zero
value called the threshold voltage, VGS(th).

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(3.4) Basic operation of n-channel E-MOSFET

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 (3.5 i) Complementary MOS CMOS

 NAND Gate: Additional MOSFETs and a second input are added to the CMOS pair to
create a digital circuit known as a NAND gate.
 Q4 is connected in parallel with Q1, and Q3 is connected in series with Q2.
 When both inputs, VA and VB, are 0, Q1 and Q4 are on while Q2 and Q3 are off,
making Vout = VDD.
 When both inputs are equal to VDD, Q1 and Q4 are off while Q2 and Q3 are on,
making Vout = 0.
 You can verify that when the inputs are different, one at VDD and the other at 0, the
output is equal to VDD.
 The operation is summarised in the table of and can be stated:
 When VA AND VB are high, the output is low; otherwise, the output is high.

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(3.5 ii) Complementary MOS CMOS – NAND Gate

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QUESTION 4
SOLUTION 4
(4 i) Low Freq AC Equivalent Circuit
(4 ii) Input RC Circuit
(4 iii) Output RC Circuit
(4 iv) Bypass RC Circuit
(4 v) Midband Gain
QUESTION 5
SOLUTION 5
 (5.1) The Ideal Op-amp

 To illustrate what an op-amp is, let’s consider its ideal characteristics.

 A practical op-amp, of course, falls short of these ideal standards, but it is much easier
to understand and analyse the device from an ideal point of view.
 First, the ideal op-amp has infinite voltage gain and infinite bandwidth.
 Also, it has an infinite input impedance (open) so that it does not load the driving
source.
 Finally, it has a zero output impedance.
 Op-amp characteristics are illustrated in (a) on next page.
 The input voltage, Vin, appears between the two input terminals, and the output voltage
is AvVin, as indicated by the internal voltage source symbol.
 The concept of infinite input impedance is a particularly valuable analysis tool for the
various op-amp configurations.

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(5.1) The Ideal Op-amp

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 (5.2) The Practical Op-amp

 Op-amps have both voltage and current limitations.

 Peak-to-peak output voltage, for example, is usually limited to slightly less than the two
dc supply voltages.
 Output current is also limited by internal restrictions such as power dissipation and
component ratings.
 Characteristics of a practical op-amp are very high voltage gain, very high input
impedance, and very low output impedance.
 Another practical consideration is that there is always noise generated within the op-
amp.
 Noise is an undesired signal that affects the quality of a desired signal.
 Today, circuit designers are using smaller voltages that require high accuracy, so low-
noise components are in greater demand.

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(5.2) The Practical Op-amp

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(5.3) Closed loop voltage gain

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(5.4) Finding output

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(5.5) Adder circuit

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 Thank you!
Daniel W. O’Hagan
[email protected]

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