MOSFETS

Metal Oxide Semiconductor FET

Device Structure

 p-type substrate (body).

 n-type regions: (n+ source and n+ drain).
 thin layer of silicon dioxide (SiO2): insulator, acts as a dielectric.
 Metal layer on top of the oxide layer: Gate electrode.
 Metal contacts to the source, drain and body regions: to facilitate current flow.

Operation With No Gate Voltage

With no bias voltage applied to the gate, no current flows between drain and source, because of the back-
to-back connected pn junctions: n+(source) to p and p to n+(drain).
Channel Creation
With source and drain grounded, free holes under the gate
region are repelled by the positive voltage, creating a
depletion region of bound negative charge.

Electrons in the source and drain regions are forced into

the channel, creating an n region under the gate terminal
which connects the source and drain regions.

The value of vGS at which a sufficient number of mobile

electrons accumulate in the channel region to form a
conducting channel is called the threshold voltage Vt.
Drain-Source Voltage VDS Applied

A small positive voltage vDS is applied between drain

and source. This causes a small current to flow in the
induced channel. Current is carried by free electrons
traveling from source to drain.
The magnitude of iD depends on the density of
electrons in the channel, which in turn depends on the
magnitude of vGS.
For vGS = Vt channel is just induced; the current
conducted is still negligibly small. (vGS  Vt): excess
gate voltage, overdrive voltage.

The iD–vDS characteristics of the MOSFET. When the voltage applied

between drain and source, vDS, is kept small. The device operates as
a linear resistor whose value is controlled by vGS.

Current-Voltage Characteristics
Circuit Symbol

(a) Circuit symbol for the n-channel enhancement-type MOSFET.

(b) Modified circuit symbol with an arrowhead on the source terminal to distinguish it from the drain and to
indicate device polarity (i.e., n channel).
(c) Simplified circuit symbol to be used when the source is connected to the body or when the effect of the
body on device operation is unimportant.
The iD-vDS Characteristics

The Cutoff Region: vGS  Vt iD  0

Triode region: vGS  Vt and vDS  vGS  Vt or vGD  vGS  vDS  Vt

W 1 2 
iD  kn   vGS  Vt  vDS  vDS 
L 2 

kn  n Cox : MOSFET transconductance

C ox : capacitance per unit gate area ;  n : electron mobility

For sufficiently small vDS:

W
iD kn  vGS  Vt  vDS : MOSFET operates as a linear resistance.
L

vDS 1
rDS  
iD vGS VGS
W
kn VGS  Vt 
L

Saturation region: vGS  Vt and vDS  vGS  Vt or vGD  Vt (Pinched-off channel)

At the boundary between the triode and saturation regions: vDS  vGS  Vt

1 W
iD  kn  vGS  Vt  vGS  Vt
2

2 L
The iD–vGS characteristic for an enhancement-type NMOS transistor in saturation (Vt = 1 V, kn’ W/L = 1.0 mA/V2).

Large-signal equivalent-circuit model of an n-channel

MOSFET operating in the saturation region.

Finite Output Resistance in Saturation

Channel length modulation:

As vDS is increased beyond vDssat = vGS-Vt , the channel pinch-off

point is moved away from the drain. The additional voltage
appears as a voltage drop across the narrow region between the
channel and the drain.

The drain current taking into account channel modulation

1 W
iD  kn  vGS  Vt  (1   vDS )
2
 is a process-technology parameter.
2 L

Effect of vDS on iD in the saturation region. The MOSFET

parameter VA depends on the process technology and, for
a given process, is proportional to the channel length L.
 1 1
 i   1 W 2 1
Output Resistance: ro   D    kn VGS  Vt   
 vDS  vGS constant  2 L   ID

where ID is the drain current without channel length modulation.

Example:

I D  0.4 mA, VD  0.5 V, Vt =0.7 V, n Cox  100  A/V 2

L  1  m, W  32  m,   0

Solution:
vDS  vDG  vGS  vGS  Vt  vDG  Vt for saturation

vDG  vD  vG  0.5 V >  0.7 V  transistor operates in saturation.

1 W 1 32
iD  nCox VGS  Vt   400  100   VOV  VOV  0.5 V
2 2

2 L 2 1
VGS  VOV  Vt  0.5  0.7  1.2 V

VS  VSS
VGS  VG  VS  VS  VS  1.2 V ID 
RS
VS  VSS 1.2  (2.5)
 RS    3.25 k
ID 0.4

VDD  VD 2.5  0.5

VD  0.5 V  RD    5 k
ID 0.4
Example: Find R in the circuit to obtain a current of 80 A. Find also the drain voltage VD.

I D  80  A, Vt =0.6 V,  n Cox  200  A/V 2

L  0.8  m, W  4  m,   0

Solution:

vD  vG  vDG  0  Vt  saturation

1 W 1 4
iD  nCox VOV 2   200   VOV
2
 80  A  VOV  0.4 V
2 L 2 0.8

3  VD
VGS  1.0 V  VD  VGS  1.0 V  R   25 k
80  A

Example: Design the circuit to establish a drain voltage of 0.1 V. Vt = 1.0 V, kn (W / L)  1 mA/V2 .

Solution:
VDG  00.1  5  4.9 V  Vt  triode region

W
 vGS  Vt VDS  VDS2   1 (5  1)  0.1  (0.1)2   0.395 mA
1 1
I D  kn 
L 2   2 

VDD  VD 5  0.1 VDS

RD    12.4 k Effective rDS   253 
ID 0.395 ID

Example: Determine the voltages at all nodes and currents in all branches.

Vt =1.0 V, kn (W / L)  1 mA/V2 ,   0

RG 2 1
Solution: VG  VDD   10  5 V
RG1  RG 2 2
Assume the transistor operates in the saturation region.

1 W 1
VGS  5  6I D  I D  kn VGS  Vt   1 (5  6I D  1)2  8  24I D  18I D2
2

2 L 2

18I D2  25I D  8  0  I D  0.89 mA, 0.5 mA

I D  0.89 mA  VGS  5  6  0.89  0.34 V < Vt  cutoff, cannot be the solution

I D  0.5 mA  VGS  5  6  0.5  2 V  VD  10  6 I D  7 V

Check: VDG  7  5  2 V >  1 V saturation

THE MOSFET AS AN AMPLIFIER AND AS A SWITCH

1. Large Signal Operation

Graphical derivation of the transfer characteristic.

1 1
vDS  VDD  RD iD  iD  VDD  vDS : the load-line equation.
RD RD

When the load-line equation is superimposed on the characteristic corresponding to the applied vGS  vI ,
the operating point of the MOSFET is obtained. As the applied voltage is varied, the operating point moves
along the load-line giving different output voltages vO  vDS . When vO is plotted against v I the transfer
characteristic of the circuit is obtained.
Operation as a Switch
As a switch, the MOSFET is operated either in the cutoff state (switch closed, no drain current), or in the
triode region with a small vO. Usually vI = VDD is used to make vO as small as possible (at point C).

Operation as an Amplifier
The transfer characteristic is highly nonlinear, but has an almost linear region in the middle of the part
corresponding to transistor saturation.
Operation as an amplifier requires that a Quiescent (Q) point is chosen that corresponds to the DC value
VIQ of the input voltage. Q is chosen in such a way that the output voltage range on the almost linear part
is maximized.

vI  VIQ  vi vi : the small-signal component of the input voltage.

vO  VOQ  vo vo : the small-signal component of the output voltage.

The voltage gain of the amplifier:

dvO
Av  : the slope of the line tangent to the transfer characteristic at Q
dvI Q

Two wrong choices for the Q-point.

Q1: Output voltage range on the positive side is very limited
(  VDD  VOQ ).

Q2: Output voltage range on the negative side is very limited

(  VOQ  (VIQ  Vt ) ).

Analytical Expressions for the Transfer Characteristic

The Cutoff Region Segment, XA: vI  Vt vO  VDD

The Saturation-Region Segment, AQB: vI  Vt vO  vI  Vt

Neglecting channel-length modulation, iD is given by

1 W
iD  nCox  vI  Vt 
2

2 L

1 W
vO  VDD  RDiD  vO  VDD  RD nCox  vI  Vt 
2
KVL:
2 L
Incremental voltage gain,

Av 
dvO
dvI
  RD n Cox
W
L
VIQ  Vt 
vI VIQ

2(VDD  VOQ )
VOQ  VDD  RD n Cox VIQ  Vt   VDD  Av VOV
1 W 2 1
At the Q-point:  Av  
2 L 2 VOV

The Triode-Region Segment, BC: vI  Vt vO  vI  Vt

W
 vI  Vt  vO  vO2 
1
iD  n Cox 
L 2 
 W
 vI  Vt  vO  vO2 
1
KVL: vO  VDD  RD iD  VDD  RD nCox nonlinear equation for vO
L  2 

Over the segment where vO is small, vO2 may be neglected. Solving for vO

VDD
vO 
W
1  RD n Cox  vI  Vt 
L

VDD rDS
In terms of rDS, vO   VDD voltage division equation
1  D rDS  RD
R
rDS

BIASING IN MOS AMPLIFIER CIRCUITS

Biasing by Fixing VGS
With VGS fixed, the bias value of the drain current is

1 W
I D  nCox VGS  Vt 
2

2 L
Because of the variability of the device parameters among
devices, and their temperature dependence, the drain current
may vary widely from device to device.
Not a good biasing technique.

Biasing by Fixing VG and Connecting a Resistance in the Source

Instead of fixing VGS, VG is fixed.

VGS  VG  RS I D

Variability of ID is greatly
reduced.

(c) Practical implementation

using a single supply.
 (d) coupling of a signal source to the gate using a
capacitor CC1.
(e) practical implementation using two supplies.

Example: Design the circuit to establish ID = 0.5 mA.

MOSFET: Vt =1.0 V, kn (W / L)  1 mA/V2 ,   0

Calculate the percentage change in ID when MOSFET is replaced with another having the

same kn (W / L) but Vt =1.5 V .

Rule of thumb: VDD is divided equally between RD, VDS and RS.

VDD = 15 V  VD = 10 V, VS = 5 V.

VDD  VD 15  10
RD    10 k
ID 0.5

VS 5
RS    10 k
I D 0.5

To find VG:

1 W 2
I D  kn VOV  VOV  1 V  VGS  2 V  VG  VGS  RS I D  7 V
2 L
 RG 2 RG 2 7
VG  VDD  7 V   Choose RG1  8 M, RG 2  7 M
RG1  RG 2 RG1  RG 2 15

NOTE: Gate resistances are usually chosen very large to minimize power loss.

1
Transistor replaced: I D  1 (VGS  Vt )2 Vt  1.5 V
2

1
VGS  VG  RS I D  7  10 I D  I D  (7  10I D  1.5)2 quadratic eqn. for ID
2

 100I D2  112I D  30.25  0

ID for the new device: I D  0.455 mA Therefore, I D  0.455  0.5  0.045 mA

Output voltage range:

Positive signal swing = 15  10 = 5 V (when iD approaches zero)

Negative signal swing: when transistor operates at the boundary between triode and saturation,

VDG  Vt  VD  VG  Vt  6 V swing = 6 – 10 =  4 V

Total swing = 9 V.

Biasing Using a Drain-to-Gate Feedback Resistor

(Gate current is zero)

VGS  VDS  VDD  RD I D load-line equation for the iD – vGS characteristic

Similar to the case with resistance connected to source.

Biasing Using a Constant-Current Source

ID is determined by the dc current source I.

Mostly used in integrated circuits.
Current source is implemented using a circuit
called a current mirror, where I  I D 2

SMALL SIGNAL OPERATION OF MOSFETs

The DC Bias Point

The DC bias current ID can be found by setting vgs = 0

1 W
I D  kn VGS  Vt 
2

2 L
Drain voltage, VD  VDD  RD I D

For operation in the saturation region we require that VDS  VD  VGS  Vt

Let vGS  VGS  vgs vgs : small-signal component

Total instantaneous drain current,

iD  kn VGS  vgs  Vt   kn VGS  Vt   kn VGS  Vt  vgs  kn vgs2
1 W 2 1 W 2 W 1 W
2 L 2 L L 2 L
The first term on the right-hand side is the bias value of ID, and the third term is a nonlinear distortion term.

Also, iD  I D  id id : small-signal component of the drain current.

W 1 W
id  kn VGS  Vt  vgs  kn vgs2
L 2 L
The second term can be neglected if
2
vgs 2 VGS  Vt  vgs small-signal condition

W
 id  kn VGS  Vt  vgs
L
Small-signal component of the drain current is proportional to the small-signal input voltage.

id W
 kn VGS  Vt  gm  id  g m vgs gm : the transconductance of the MOSFET.
vgs L

gm can be computed as

iD
gm 
vGS VGS
The Voltage Gain

Total instantaneous drain voltage:

vD  VDD  RD iD  VDD  RD ( I D  id )  VD  RD id  VD  vd

 vd   RD id   g m RD vgs

vd
Av    g m RD
vgs

Small-Signal Equivalent Circuit

Small-signal models for the MOSFET:

(a) neglecting the dependence of iD on vDS in saturation (the channel-length modulation effect);

(b) including the effect of channel-length modulation, modeled by output resistance ro = |VA| /ID.

Example: Determine the small-signal voltage gain, the input resistance and the largest allowable input
signal of the Common-Source amplifier. Coupling capacitors are very large.

Vt =1.5 V, kn (W / L)  0.25 mA/V2 , VA  50 V

A DC analysis must be performed to determine the DC bias point.

Equivalent circuit for DC operation (small-signal input is suppressed, capacitors open-circuit)

+15 V
1
I D   0.25  VGS  1.5
2
10 k
2
VGS  VD  15  10 I D
RG
8I D  13.5  10I D   I D  1.06 mA, VD  4.4 V
VD 2
0A

+ (Note: the other solution for ID gives VGS  Vt )

VGS
-

Calculation of small-signal parameters:

VA 50
g m  0.25  (4.4  1.5)  0.725 mA/V ro    47 k
ID 1.06

Small-signal equivalent circuit of the amplifier:

The coupling capacitors are short-circuited.

All DC sources are turned off (voltage

sources are shorted and current sources are
opened)

Because RG = 10 M is very large, ii  0

vo   g m vgs (ro || RD || RL )  0.725  (47 ||10 ||10)vi  Av  3.3 V/V

vi vi  vo vi  Av vi RG 10 M
Input resistance: Rin  ii    Rin    2.33 M
ii RG RG 1  Av 1  3.3

Largest allowable signal:

vDS  vGS  Vt for operation in the saturation region.

vDS ,min  vGS ,max  Vt  VDS  Av Vˆi  VGS  Vˆi  Vt VDS  VGS
 4.3Vˆi  Vt  Vˆi  0.34 V
 SINGLE-STAGE MOSFET AMPLIFIERS
The Basic Structure

Basic structure used to realize single-stage MOS amplifier

configurations.
Constant current source biasing is used.

Characteristic Parameters of Amplifiers

A general amplifier circuit, showing input and

output currents and voltages.

Definitions:

vi
Input resistance with no load: Ri 
ii RL 

vi
Input resistance: Rin  (includes the effect of the load resistance)
ii

vo
Open-circuit voltage gain: Avo 
vi RL 

vo
Voltage gain: Av  (includes the effect of the load resistance)
vi
io
Short-circuit current gain: Ais 
ii RL  0

io
Current gain: Ai 
ii
Calculation of output resistance:

To calculate (or measure) the output resistance of the amplifier

model itself (without the input source), the input terminals are short-
circuited and a current source ix is connected to the output. The
voltage at the output terminals is calculated (or measured).
v
Ro  x
ix v 0
i

Overall output resistance when the signal source is connected is

calculated as:
vx
Rout 
ix vsig  0

The Common-Source Amplifier (CS Amplifier)

This configuration is called the Common-Source (CS) configuration, because the source terminal of the
MOSFET is common to the input (between gate and ground) and the output (between drain and ground).
The source terminal of the MOSFET is connected to the ground through CS, called the by-pass capacitor,
the capacitance of which is large enough so that it behaves like a short-circuit in small-signal operation.
The function of this capacitor is to by-pass the biasing current source in small-signal operation (otherwise
the source terminal would be left floating with no small-signal current path).
The input signal source (vsig) is connected between the input terminal of the amplifier (the gate of the
MOSFET) and the ground through a large capacitor CC1, called the coupling capacitor.
The function of this capacitor is to isolate (or decouple) the DC biasing circuit from the input signal source
resistance Rsig so that the biasing conditions are not modified when an arbitrary source resistance is
connected. (A capacitor is an open circuit at DC).
The capacitance of CC1 is large enough so that at the frequencies of the signal to be amplified it behaves
1
like a short-circuit (the impedance of a capacitor is ZC  , so that when C is large the magnitude of
j C
the impedance is small; in other words, given the signal frequency , C is chosen such that magnitude of
ZC is small compared to RG).
Similarly the load resistance RL is connected between the drain of the MOSFET and the ground through a
large capacitor CC2 (coupling capacitor), the function of which is to isolate (or decouple) the DC biasing
circuit from the load so that the biasing conditions are not modified when an arbitrary load resistance is
connected.
The analysis of the amplifier is performed in two stages:
1- The DC biasing calculations to determine the quiescent values. The coupling and by-pass capacitors are
open-circuited.

2- AC or small-signal analysis to determine the voltage/current gains and input/output resistances. The
MOSFET is replaced by its small-signal model. The coupling and by-pass capacitors are taken as short-
circuits. The DC sources are turned off: voltage sources are shorted, and the current source is opened.

The small-signal equivalent circuit of the amplifier is drawn and analyzed:

Voltage gains:

vo   g m vgs (ro || RD || RL )

vo
Voltage gain: vgs  vi  Av    g m (ro || RD || RL )
vi

vo
Open-circuit voltage gain: Avo    g m (ro || RD )
vi RL 

vo vo vi RG RG
Overall voltage gain: Gv   vi  vsig  Gv  Av
vsig vi vsig RG  Rsig RG  Rsig

Usually RG Rsig  Gv  Av

A disadvantage of this amplifier configuration is that the voltage gain depends on the parameter gm, which
makes it susceptible to changes in the operating conditions (temperature etc.) and device replacement.

Input Resistance:

ig  0  Rin  RG

Output Resistance:
1. Set vsig = 0.
2. Apply a test source to the output (current or voltage).
3. Find Rout  vt / it .

vsig  0  vgs  0  controlled current source becomes open-circuit.  Rout  ro || RD

(no need for connecting a test source in this case, because the result is already obvious)
The Common-Source Amplifier with a Source Resistance

To stabilize the voltage gain and make it less

dependent on device parameters, a resistance
(RS) is placed in the source circuit.

Small-signal equivalent circuit of the amplifier:

Rsig Rout
G D
vo The output resistance of the
+
+ gmvgs MOSFET, ro, may be neglected
+ vgs to simplify the analysis (ro is
vsig _ vi RG RD RL
Rin  S usually much larger than RD
 and RL)

RS

Voltage gains:

vo   g m vgs ( RD || RL )

vi
Voltage gain: vi  vgs  vs  vgs  g m vgs Rs  vgs 
1  g m RS

g m ( RD || RL ) vo g ( R || R )
vo   vi  Av   m D L
1  g m RS vi 1  g m RS

vo g m RD
Open-circuit voltage gain: Avo  
vi RL 
1  g m RS
 vo vo vi RG RG
Overall voltage gain: Gv   vi  vsig  Gv  Av
vsig vi vsig RG  Rsig RG  Rsig

The voltage gain Av is reduced by the factor (1  g m RS ) compared to the voltage gain without source
resistance (RS). Let’s write the voltage gain in the form

( RD || RL )
Av  
(1/ g m )  RS

( RD || RL )
Usually, (1 / g m ) RS so that Av   independent of the MOSFET parameter.
RS

Input Resistance: Rin  RG

Output Resistance: vsig  0  vi  0  vgs  0

The controlled current source becomes open circuit. Rout  RD

The Common-Gate Amplifier

Signal to be amplified is applied through the source

terminal of the MOSFET.
Output is taken from the drain terminal.
Gate terminal of the MOSFET is common to the
input and output.
Small-signal equivalent circuit

Rin Rout
Rsig S gmvgs D
+ - + Output resistance, ro, of the MOSFET is
ii vgs
vsig +
_ vi RD RL vo neglected to simplify the analysis.

 G -

Voltage gains:

vo   g m vgs ( RD || RL )

vo
Voltage gain: vgs  vi  Av   g m ( RD || RL ) positive gain
vi

vo
Open-circuit voltage gain: Avo   g m RD
vi RL 

Overall voltage gain:

KVL around the input loop,

vsig
vsig  Rsig ii  vgs  0 ii   g mvgs  vgs  
1  gm Rsig

g m ( RD || RL ) vo g ( R || RL )
vo  vsig  Gv   m D
1  g m Rsig vsig 1  g m Rsig

vi 1
Input Resistance: Rin  vi  vgs ii   g m vgs  Rin 
ii gm

Output Resistance:

Rout  RD because vgs  0 when vsig = 0 (the dependent current source becomes open)
The Common-Drain (Source Follower) Amplifier

Signal to be amplified is applied through

the gate terminal of the MOSFET.
Output is taken from the source terminal.
Drain terminal of the MOSFET, which is
connected to the ground in small-signal
operation), is common to the input and
output.

Small-signal equivalent circuit

Rin
Rsig G D

+ + gmvgs
vsig + vgs ro
_ RG vi
 S


vo
RL
Rout

Voltage gains:

vo  g m vgs (ro || RL ) (ro and RL are parallel)

Voltage gain: KVL over the loop (ground  RG  GS  RL  ground)

vi
vi  vgs  vo  0  1  gm (ro || RL ) vgs  vi  vgs 
1  g m (ro || RL )

g m (ro || RL ) g m (ro || RL )
vo  vi  Av  1 (voltage gain is less than but close to 1)
1  g m (ro || RL ) 1  g m (ro || RL )

vo g m ro
Open-circuit voltage gain: Avo  
vi RL 
1  g m ro
Overall voltage gain:
RG RG
vi  vsig  Gv  Av
RG  Rsig RG  Rsig

Input Resistance: Rin  RG

Output Resistance: We apply the procedure given before.

1. Set vsig = 0.
2. Apply a test source to the output (current or voltage).
3. Find Rout  vt / it .

Rsig G D

+ + gmvgs
vgs ro
RG vi
 S


it
+
_ vt

vG  0 vS  vt vG  vgs  vt  vgs  vt

vt  1 vt ro
KCL at S: it  g m vgs   0  it   g m   vt  Rout  
ro  ro  it 1  g m ro
 FREQUENCY RESPONSE OF MOSFET AMPLIFIERS

The High-Frequency MOSFET Model

A simplified high-frequency equivalent circuit model

for the MOSFET.

The capacitances in the model are due to the gate

capacitive effect.

Frequency Response of the CS Amplifier

The three frequency bands in the

frequency response of the
amplifier.
Small-signal Equivalent Circuit in the High Frequency Range

 The DC sources are turned off (voltage sources are short-circuited, current sources are
open-circuited).
 DC coupling and bypass capacitors are short-circuited (having very large capacitances,
they become nearly short-circuits at high frequencies).
 The MOSFET is replaced by its high-frequency model.

Analysis
The circuit can be analyzed in the frequency domain to derive the transfer function of the amplifier. The
analysis can be simplified if the input circuit, including RG, is replaced by its Thevenin equivalent.

Rsig Rth
G
G

+
Vsig +
_ RG Vth _

RG
Vth  Vsig Rth  RG || Rsig
RG  Rsig

Also, the resistances at the output can be combined

RL  ro || RD || RL
Approximate analysis:

Vo   g m RLVgs because I gd  g mVgs

The gate-drain current: I gd  sCg d (Vgs  Vo )  sCg d (Vgs  g m RLVgs )  sCg d (1  g m RL )Vgs

The input current: I i  sCg sVgs  sCg d (1  g m RL )Vgs   sCg s  sCg d (1  g m RL )  Vgs

 I i  s C g s  Ceq  Vgs where Ceq  (1  g m RL )C gd

 
 Vth  1  Vth
Vgs     where Cin  C g s  Ceq
R  1   sCin  1  sCin Rth
 th sC 
 in 

 
 RG  1 
Vo   g m RL 
 RG  Rsig   Vsig
1 
s

  
 0 

Overall voltage gain in the s-domain (for frequency domain s = j )

  
V  RG  1  AM
Gv ( s )  o   g m RL 
 RG  Rsig   
1  1 s
Vsig s

   0
 0 

 RG  1  1
AM   g m RL   : midband gain; 0  : upper cutoff frequency ( f H  0  )
R R Cin Rth 2 2 Cin Rth
 G sig 

AM AM
Gv ( j )  Gv ( j ) 
 1  ( / 0 ) 2
1 j
0
 AM 
Gv ( j ) dB  20 log10  
 1  ( /  ) 2 
 0 
 0 Gv ( j ) dB  20 log10 ( AM )
 0 Gv ( j ) dB  20 log10  AM   20 log10 1  ( / 0 ) 2  20 log10  AM   20 log10 ( / 0 )
Gv ( j ) dB  20 log10  AM   20 log10 ( )  20 log10 (0 )

 A 
  0 Gv ( j0 ) dB  20 log10  M   20 log10  AM   20 log10  2
 2 
 20 log10  AM   3 dB