ECT 202: Analog Circuits Module III

MODULE III

MOSFET amplifiers: MOSFET circuits at DC, MOSFET as an amplifier, Biasing of discrete

MOSFET amplifier, small signal equivalent circuit. Small signal voltage and current gain, input and
output impedance of CS configuration. CS stage with current source load, CS stage with diode-
connected load.

Multistage amplifiers - effect of cascading on gain and bandwidth. Cascode amplifier.

INTRODUCTION

FIELD EFFECT TRANSISTORS

FET is semiconductor device in which the current is controlled by electric field existing at the depletion
region of a reverse biased PN junction. The operation of FET depends only on the flow of majority
carriers and hence they are unipolar devices.

The main difference between FETs and BJTs are

i) BJT is bipolar where FET is unipolar.

ii) BJTs are current controlled devices where as FETs are voltage-controlled devices.
iii) BJTs have relatively low input resistance, whereas FETs have high input impedance.
iv) FETs have better thermal stability
v) FETs have relatively small gain bandwidth product in comparison with BJT.

MOSFET

➢ Voltage controlled device

➢ High input resistance
➢ More efficient compared to BJT

Types:

Enhancement Type – Normally Off type

Depletion Type – Normally ON type

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ECT 202: Analog Circuits Module III

Enhancement MOSFET

The symbol of N and P channel Enhancement MOSFET is given below.

Structure

The transistor is fabricated on P-type substrate.

With positive voltage on the drain,

electrons from source cannot reach
drain because of the absence of
conducting channel. Thus
enhancement MOSFET remain
normally OFF. It can be seen from the
structure that the gate and body form
two plates of a capacitor with SiO2 as
the dielectric. When a positive
voltage is applied on the Gate,
concentration of electrons near the
SiO2 layer increases. As the amount
of positive voltage on the gate is increased more and more negative charges are induced which
increases the effective conducting area of the channel, and hence drain current increases.

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ECT 202: Analog Circuits Module III

For a particular value of VDS drain current is negligible with zero bias on the gate. As the gate is made
more and more positive a negative channel is induced in the substrate and the drain current increases.

Region of Operation of Enhancement mode PMOS Transistor

1. Cut-off region
2. Triode Region
3. Saturation region

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ECT 202: Analog Circuits Module III

Depletion type MOSFET

The depletion type MOSFET has a physically implanted channel between the source and the drain.
The structure of N channel depletion MOSFET is shown below.

On a P substrate a heavily doped N regions act

as Source and Drain. Over this a thin layer of
SiO2 is coated and aluminium contacts are
taken for Source, Gate and Drain. Between
Source and Drain a negative channel is
implanted in the substrate.

Because of the presence of N type implanted

channel between S and D, the device can
conduct with usual biasing. This channel provides the path for movement of electrons from S to D.
Therefore, D-MOSFET remains normally ON.

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ECT 202: Analog Circuits Module III

To reduce conductivity and

to control drain current, a
negative voltage is applied
to the Gate. Due to
capacitor action positive
charges are induced in the
N-type diffused channel,
which depletes the
negative charges. As the
amount of negative voltage
on the gate is increased,
more and more positive
charges are induced which
almost depletes the n-
channel. Now the over all
conductivity in reduced
and drain current falls off.

With VGS =0, the device conducts normally with a

finite drain voltage. As the gate is made more and
more negative, more positive charges are induced
which depletes the available n-channel as a result
the drain current reduces.

𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 [1 − ]
𝑉𝑃

Or

𝑉𝐺𝑆
𝑔𝑚 = 𝑔𝑚𝑜 [1 − ]
𝑉𝑃
2𝐼𝐷𝑆𝑆
Where 𝑔𝑚𝑜 = |𝑉𝑃 |

MOSFET CIRCUITS AT DC

Design the circuit given in figure and determine the values of RD and RS so
that the transistor operates at ID = 0.4mA and VD = +0.5V. The NMOS
transistor has Vt = 0.7V, μnCox =100μA/V2,L = 1μm and W = 32μm. Neglect
the channel length modulation effect.

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ECT 202: Analog Circuits Module III

Since VD = 0.5V is greater than VG, NMOS transistor is operating in the saturation region, then

We note that the gate is at ground potential. Thus, the source must be at −1.2 V,

Figure shows an NMOS transistor with its drain and gate terminals connected together. Find the
i-v relationship of the resulting two terminal device (diode connected transistor) in terms of the
𝑾
MOSFET parameters 𝒌𝒏 = 𝒌′𝒏 ( 𝑳 ) and 𝑽𝒕𝒏 . Neglect channel-length modulation.

Since VD = VG implies operation in the saturation mode

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ECT 202: Analog Circuits Module III

Input impedance of MOS is very high so gate current can be taken as zero. Then

𝑖 = 𝑖𝐷 and 𝑣 = 𝑣𝐺𝑆 thus

1 𝑊
𝑖𝐷 = 2 𝑘𝑛′ [ 𝐿 ] (𝑉𝐺𝑆 − 𝑉𝑡𝑛 )2

Design the circuit in figure to establish a drain voltage of 0.1V. What is the effective resistance
𝑾
between drain and source at this operating point. Let 𝑽𝒕𝒏 = 𝟏𝑽 and 𝒌′𝒏 ( 𝑳 ) = 𝟏𝒎𝑨/𝑽𝟐 .

From figure 𝑉𝐺 = 5𝑉 = 𝑉𝐺𝑆 & given 𝑉𝐷 = 0.1𝑉

Since drain voltage is lower than the gate voltage and 𝑉𝑡𝑛 = 1𝑉 , the MOSFET is operating in the
triode region.

Thus Drain current

Substituting the given values, iD = 0.0395mA

𝑉𝐷𝐷 − 𝑉𝐷 5 − 0.1
𝑅𝐷 = = = 12.4𝐾Ω
𝑖𝐷 0.0395𝑚

Since transistor is operating in the triode region with small VDS, the effective drain to source resistance

𝑉𝐷𝑆
𝑟𝐷𝑆 = = 253Ω
𝑖𝐷

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ECT 202: Analog Circuits Module III

Analyze the circuit shown in Fig. to determine the voltages at all nodes and the currents through

𝑾
all branches. Let 𝑽𝒕𝒏 = 𝟏V and 𝒌′𝒏 ( 𝑳 ) = 𝟏𝒎𝑨/𝑽𝟐 .Neglect the channel-length modulation effect

Since gate current is zero, the voltage at the gate is simply determined by the voltage divider by the
two 10MΩ resistors

With this positive voltage at the gate, the NMOs transistor will be turned on. Assume the transistor is
operating in the saturation region.

Since the voltage at the gate is 5V and the voltage at source is 𝐼𝐷 (𝑚𝐴) × 6𝑘 = 6𝐼𝐷 we have

Drain current is given by

Which results in the following quadratic equation

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ECT 202: Analog Circuits Module III

This equation yields two values for ID = 0.89 mA and 0.5 mA. The first value results in a source voltage
of which is greater than the gate voltage and does not make physical sense as it would imply that the
NMOS transistor is cut off. Thus,

MOSFET AS AN AMPLIFIER

When operated in saturation, the MOSFET functions as

voltage-controlled current source: The gate-to-source voltage
controls the drain current.

A voltage controlled current source can serve as a

transconductance amplifier whose input signal is voltage and
output is a current. A simple way to convert transconductance
amplifier to a voltage amplifier is to pass the output current
through resistor and take the voltage across the resistor as the
output.

Here VGS is the input voltage, RD (load resistance) converts

drain current iD to a voltage and VDD is the supply voltage that
powers up the amplifier and together with RD establishes operation in saturation region.

The output voltage is given by

𝑣𝐷𝑆 = 𝑉𝐷𝐷 − 𝑖𝐷 𝑅𝐷 ----(1)

Thus it is an inverted version of 𝑖𝐷 𝑅𝐷 that is shifted by constant value of the supply voltage 𝑉𝐷𝐷 .

Voltage Transfer Characteristic (VTC)

This is a plot of output voltage 𝑣𝐷𝑆 versus input voltage 𝑣𝐺𝑆 .

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ECT 202: Analog Circuits Module III

For 𝑣𝐺𝑆 < 𝑣𝑡 the transistor is cut

off, 𝑖𝐷 = 0 and from (1)

𝑣𝐷𝑆 = 𝑉𝐷𝐷

As 𝑣𝐺𝑆 exceeds 𝑣𝑡 the transistor

turns on and 𝑣𝐷𝑆 decreases.
However, since initially 𝑣𝐷𝑆 is still
high, the MOSFET will be
operating in saturation. This
continues as 𝑣𝐺𝑆 is increased until

𝑣𝐷𝑆 = 𝑣𝐺𝑆 − 𝑣𝑡 at point B. For

𝑣𝐺𝑆 greater than that at point B, the
transistor operates in the triode
region and 𝑣𝐷𝑆 decreases more
slowly.

An expression for the segment AB

can be obtained by substituting for
iD in Eq. (1) by its saturation-region value

we get,

------ (2)

This is a nonlinear relationship. By using biasing techniques, it can be made linear.

BIASING THE MOSFET TO OBTAIN LINEAR AMPLIFICATION

Biasing enables us to obtain almost-linear amplification from the MOSFET. A dc voltage 𝑉𝐺𝑆 is
selected to obtain operation at a point Q on the segment AB of the VTC. The coordinates of Q are the
dc voltages 𝑉𝐺𝑆 and 𝑉𝐷𝑆 related by

------ (3)

Q point is known as bias point or dc operating point. Since at Q no signal component is present, it is
also known as quiescent point.

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ECT 202: Analog Circuits Module III

The signal to be amplified 𝑣𝑔𝑠 , a function of time t, is superimposed on the bias voltage 𝑉𝐺𝑆 . Thus the
total instantaneous value of 𝑣𝐺𝑆 becomes

𝑣𝐺𝑆 (𝑡) = 𝑉𝐺𝑆 + 𝑣𝑔𝑠 (𝑡) --- (4)

The resulting 𝑣𝐷𝑆 (𝑡) can be

obtained by substituting for 𝑣𝐺𝑆 (𝑡)
into (2). If the input signal is kept
small, the corresponding signal at
the output will be nearly
proportional with constant of
proportionality being the slope of
the almost -linear segment of VTC
around Q.

Shorter the segment, the greater the

linearity achieved.

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ECT 202: Analog Circuits Module III

BIASING TECHNIQUES FOR DEPLETION MODE MOSFET

Depletion mode MOSFET requires negative voltage on the Gate. So stays normally ON. The drain
current for depletion mode is given by

𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑃

Different biasing schemes are

1. Fixed bias
2. Source self-bias
3. Voltage divider bias

Fixed Bias

Depletion mode NMOSFET is given. Fixed voltage is applied to the Gate

terminal using another power supply VGG. Since Gate is reverse biased or
isolated Gate current is zero. Then gate voltage VG = - VGG. Source is
connected to ground. Then gate source voltage VGS = VG-VS = - VGG. --- (1)

Considering Drain loop,

𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑉𝐷𝑆

Or 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 ---(2)

From (1) & (2) Q point can be determined.

Disadvantage: 2 power sources are required.

Source Self-Bias

Here we do not require additional power source. Using single power

supply the required negative voltage can be ensured at the Gate with
respect to Source by using a Source resistance.

Here 𝑉𝐺 = 0, 𝑉𝑆 = 𝐼𝐷 𝑅𝑆

Then 𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = −𝐼𝐷 𝑅𝑆 ---(1)

Considering Drain loop,

𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑉𝐷𝑆 + 𝐼𝐷 𝑅𝑆 or

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝐼𝐷 𝑅𝑆 --- (2)

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ECT 202: Analog Circuits Module III

Voltage Divider Bias

𝑉 𝑅
The voltage at gate is 𝑉𝐺 = 𝑅 𝐷𝐷+𝑅𝐺2
𝐺1 𝐺2

Source voltage 𝑉𝐺 = 𝐼𝐷 𝑅𝑆
𝑉 𝑅
Then 𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = 𝑅 𝐷𝐷+𝑅𝐺2 − 𝐼𝐷 𝑅𝑆 ---- (1)
𝐺1 𝐺2

Select 𝑅𝐺1 & 𝑅𝐺2 , so that 𝑉𝐺𝑆 is negative.

Drain loop equation is, 𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑉𝐷𝑆 + 𝐼𝐷 𝑅𝑆

Or 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝐼𝐷 𝑅𝑆 --- (2)

BIASING TECHNIQUES FOR ENHANCEMENT MODE MOSFET

Enhancement MOSFET conducts only when the applied voltage exceeds the threshold voltage and
forms a channel. So this is normally OFF transistor. Enhancement mode MOSFFET requires a positive
voltage on the Gate.
𝑊 𝑊
The drain current is given by 𝐼𝐷 = 𝐾(𝑉𝐺𝑆 − 𝑉𝑡 )2 where 𝐾 = 𝐾𝑛′ = 𝜇𝑛 𝐶𝑜𝑥
𝐿 𝐿

Different biasing schemes are

1. Voltage divider bias

2. Drain to Gate bias
3. Modified Drain to Gate bias

Voltage Divider Bias

𝑉 𝑅
The voltage at gate is 𝑉𝐺 = 𝑅 𝐷𝐷+𝑅𝐺2
𝐺1 𝐺2

Source voltage 𝑉𝐺 = 𝐼𝐷 𝑅𝑆
𝑉 𝑅
Then 𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = 𝑅 𝐷𝐷+𝑅𝐺2 − 𝐼𝐷 𝑅𝑆 ---- (1)
𝐺1 𝐺2

We have to make sure that 𝑉𝐺𝑆 is positive. So that select 𝑅𝐺1 & 𝑅𝐺2
in such a way that 𝑉𝐺 > 𝑉𝑆

Drain loop equation is, 𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑉𝐷𝑆 + 𝐼𝐷 𝑅𝑆

Or 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝐼𝐷 𝑅𝑆 --- (2)

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ECT 202: Analog Circuits Module III

Drain to Gate Bias

This is a simple biasing scheme in which Gate bias is applied from Drain
terminal. Since Gate is isolated Gate current is zero. Therefore the Gate
voltage is 𝑉𝐺 = 𝑉𝐷𝑆 , 𝑉𝑠 = 0 . Then

𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = 𝑉𝐷𝑆 ---(1)

From Drain loop, 𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑉𝐷𝑆

Or 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 ----- (2)

Modified Drain to Gate Bias

In previous scheme 𝑉𝐺𝑆 = 𝑉𝐷𝑆 . In certain applications, this may

not be always equal.

Here 𝑉𝐺𝑆 ≠ 𝑉𝐷𝑆

𝑉 𝑅
The gate voltage 𝑉𝐺 = 𝑅 𝐷𝑆+𝑅𝐺2 and source voltage 𝑉𝑠 = 0
𝐺1 𝐺2

𝑉 𝑅
Then 𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = 𝑅 𝐷𝑆+𝑅𝐺2 ----(1)
𝐺1 𝐺2

From Drain loop equation

𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑉𝐷𝑆

Or 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 ----- (2)

SMALL SIGNAL MODEL OF MOSFET

In order to draw the small signal model, consider the simple circuit.
The circuit is biased in such a way that its operating point is in
saturation region by using VDC. So the circuit act as amplifier. The
input AC voltage Vi is also applied. In saturation region the drain
current is given by

1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑂𝑋 (𝑉𝐺𝑆 − 𝑉𝑡 )2
2 𝐿

The gate source voltage is given by 𝑉𝐺𝑆 = 𝑉𝑖 + 𝑉𝐷𝐶

Then

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ECT 202: Analog Circuits Module III

1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑂𝑋 (𝑉𝑖 + 𝑉𝐷𝐶 − 𝑉𝑡 )2
2 𝐿

We can see the relation between input voltage 𝑉𝑖 and drain current 𝐼𝐷 is no-linear. If 𝑉𝑖 is very small,
the change in drain current is linearly proportional to input voltage. Then in that case MOSFET can be
replaced by small signal model. i.e when 𝑉𝑖 ≪ 𝑉𝐷𝐶 − 𝑉𝑡 , drain current becomes,

1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑂𝑋 [(𝑉𝑖 )2 + 2𝑉𝑖 (𝑉𝐷𝐶 − 𝑉𝑡 ) + (𝑉𝐷𝐶 − 𝑉𝑡 )2 ]
2 𝐿

Since 𝑉𝑖 ≪ 𝑉𝐷𝐶 − 𝑉𝑡 , we can neglect (𝑉𝑖 )2

Then
𝑊 1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑂𝑋 𝑉𝑖 (𝑉𝐷𝐶 − 𝑉𝑡 ) + 𝜇𝑛 𝐶𝑂𝑋 (𝑉𝐷𝐶 − 𝑉𝑡 )2
𝐿 2 𝐿

This can be rewritten as

1 𝑊 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑂𝑋 (𝑉𝐷𝐶 − 𝑉𝑡 )2 + 𝜇𝑛 𝐶𝑂𝑋 𝑉𝑖 (𝑉𝐷𝐶 − 𝑉𝑡 )
2 𝐿 𝐿

Here we can see that the first term contains only DC component. Then 𝐼𝐷 = 𝐼𝐷𝑂 + 𝑔𝑚 𝑉𝑖
𝑊
Where 𝜇𝑛 𝐶𝑂𝑋 𝐿 (𝑉𝐷𝐶 − 𝑉𝑡 ) = 𝑔𝑚 is the transconductance and 𝐼𝐷𝑂 is the DC drain current. 𝑔𝑚 𝑉𝑖
represents the change in drain current due to input signal. So the total response is the summation of
AC and DC responses.

The small signal without considering channel length modulation(λ=0) is given by

In saturation drain current depends on VDS. This is modelled by a finite resistance r0 between drain and
source where

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ECT 202: Analog Circuits Module III

where is a MOSFET parameter that is either specified or can be measured.

SMALL SIGNAL ANALYSIS OF CS AMPLIFIER

Here the input signal is applied across source and gate and output is measured between source and
drain terminal.

We are analysing the transistor in mid-frequency region. So the capacitors are treated as short circuits.

To draw AC equivalent model DC source is set to zero. Then circuit is modified as given below.

R1 and R2 is in parallel, so lets take 𝑅𝐺 = 𝑅1 || 𝑅2

Now the transistor is replaced by small signal model.

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ECT 202: Analog Circuits Module III

Input Resistance

Looking from input side, 𝑅𝑖𝑛 = 𝑅𝐺 = 𝑅1 ||𝑅2

Output Resistance

Load resistance is not considered here.

𝑅𝑂 = 𝑟0 ||𝑅𝐷

Voltage Gain

Input voltage 𝑉𝑖 = 𝑉𝑔𝑠

Output voltage 𝑉0 = −𝑔𝑚 𝑉𝑔𝑠 (𝑟0 ||𝑅𝐷 ||𝑅𝐿 )

𝑉
Then gain is given by 𝐴𝑣 = 𝑉 𝑖 = −𝑔𝑚 (𝑟0 ||𝑅𝐷 ||𝑅𝐿 )
𝑂

MOSFET AMPLIFIER WITH ACTIVE LAOD

Active Load:

Active loads are commonly used in

integrated circuits where power
consumption and size are major concern.
So in such cases resistors are replaced by
active components like transistor. Such
loads are called active loads.

In the above figure, the gain is given by

𝐴𝑣 = −𝑔𝑚 𝑅𝐷 neglecting channel length modulation effect.

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ECT 202: Analog Circuits Module III

In order to increase the gain,

i) increase value of RD OR

ii) increase transconductance gm

But we cannot increase value of RD indefinitely, because voltage drop across it also increases. Hence
available voltage across drain reduces.
2𝐼𝐷
We have 𝑔𝑚 = 𝑉 . in order to increase gm we need to increase ID. But power dissipation also
𝐺𝑆 −𝑉𝑇
𝑊
increases. Transconductance is given by 𝑔𝑚 = √2𝜇𝑛 𝐶𝑂𝑋 𝐼
𝐿 𝐷

𝑊
As we increase 𝐿 we can increase 𝑔𝑚 . But again the size of MOSFET increases and requires more
area. This can be solved by replacing resistor by a current source and current source act as active load.

(1) CS MOSFET AMPLIFIER WITH CURRENT SOURCE LAOD

Here active load is current source. Consider an ideal current source replacing the resistor RD.

The gain of the original circuit is given by 𝐴𝑣 = −𝑔𝑚 𝑅𝐷 . RD is replaced by current source.

Advantages of such sources are

i) biasing current of the circuit is independent of temperature as well as device parameters won’t
affect the current.
ii) During small signal analysis ideal current source is replaced by open circuit. Then the output
resistance becomes infinite and hence gain also becomes infinite.

The CS amplifier with current source is given here:

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ECT 202: Analog Circuits Module III

For AC analysis DC power supply and DC voltage is grounded.

Then AC equivalent of the circuit becomes:

In small signal analysis, current source is replaced by open circuit. Then the small signal model
becomes

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ECT 202: Analog Circuits Module III

Here 𝑉𝑖𝑛 = 𝑉𝑔𝑠 and

Output 𝑉0 = −𝑔𝑚 𝑉𝑔𝑠 𝑟0

𝑉
Then gain 𝐴𝑣 = 𝑉 𝑖 = −𝑔𝑚 𝑟0
𝑂

We can see that there is significant improvement in gain and is known as intrinsic voltage gain, which
is the maximum obtainable gain for CS MOSFET amplifier. This is attained when we use ideal current
source.

But when we use actual current source, it will have finite output resistance.

Hence the small signal model becomes

𝑟01 – output resistance of transistor, 𝑟02 – output resistance of current source

Then the output voltage is 𝑉0 = −𝑔𝑚 𝑉𝑔𝑠 (𝑟01 ||𝑟𝑜2 )

𝑉
Then gain becomes : 𝐴𝑣 = 𝑉 𝑖 = −𝑔𝑚 (𝑟01 ||𝑟𝑜2 )
𝑂

This is less than intrinsic voltage gain. But its greater than gain with RD.

Current source using MOSFET

MOSFET can be used as current source in saturation region. In saturation region drain current is a
function of VGS.

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ECT 202: Analog Circuits Module III

1 𝑊
𝐼𝐷 = 𝜇𝑛 𝐶𝑂𝑋 (𝑉𝐺𝑆 − 𝑉𝑡 )2 = 𝑘(𝑉𝐺𝑆 − 𝑉𝑡 )2
2 𝐿

By making VGS constant we can operate MOSFET as current source.

We are using P type MOSFET when we are using MOSFET in

between supply and circuit.

Source terminal is connected to VDD and Gate is connected to

fixed voltage VBias . At drain terminal remaining circuit is
connected. The MOSFET should be operating in saturation region.
Then 𝑉𝑆𝐷 ≥ 𝑉𝐺𝑠 − 𝑉𝑡

We are using N type MOSFET when we are using MOSFET in between circuit and ground.

Source is connected to grounded. VBias is the fixed voltage. circuit connected at drain terminal.

Condition for saturation is 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑠 − 𝑉𝑡

AC Equivalent model

In order to draw equivalent model DC voltages are grounded.

Hence in PMOS the gate and source terminals are grounded. Then VGS = 0 . Hence there is only the
output resistance r01.

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ECT 202: Analog Circuits Module III

Then circuit becomes

In circuit VDC also grounded. Then small signal model becomes

Here 𝑉𝑖𝑛 = 𝑉𝑔𝑠 and

Output 𝑉0 = −𝑔𝑚 𝑉𝑔𝑠 (𝑟01 ||𝑟𝑜2 )

𝑉
Then gain becomes : 𝐴𝑣 = 𝑉 𝑖 = −𝑔𝑚 (𝑟01 ||𝑟𝑜2 )
𝑂

Output resistance 𝑅0 = (𝑟01 ||𝑟𝑜2 )

Input resistance 𝑅𝑖𝑛 = ∞

Because of finite output resistance of PMOS, gain will be always less that intrinsic gain. If 𝑟01 = 𝑟𝑜2
gain will be half of intrinsic gain.

(2) CS STAGE WITH DIODE CONNECTED LOAD

To make NMOS diode connected load, Gate and drain terminals connected to VDD. Similarly, to make
PMOs diode connected load, Gate and Drain to ground.

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ECT 202: Analog Circuits Module III

When we need moderate gain we use diode connected load.

Fig: NMOS with diode connected Load Fig: Simplified circuit

If we are not considering channel length modulation, then 𝑟01 & 𝑟𝑜2 can be neglected.

Then the small signal model becomes

DRAW

Gain equation for CS configuration with RD is given by 𝐴𝑣 = −𝑔𝑚 𝑅𝐷

1
Here we can write it as: 𝐴𝑣 = −𝑔𝑚1
𝑔𝑚1

considering the equations for transconductance we can write

𝑊 𝑊
√2𝜇𝑛 𝐶𝑂𝑋 ( 𝐿 ) 𝐼𝐷 √( 𝐿 )
1 1
𝐴𝑣 = 𝑊
= 𝑊
√2𝜇𝑛 𝐶𝑂𝑋 ( 𝐿 ) 𝐼𝐷 √( 𝐿 )
2 2

Gain depends on width to length ratio of transistors and is independent of process parameters 𝜇𝑛 𝐶𝑂𝑋

and drain current.

More accurate expression for gain can be calculated by considering channel length modulation effect.

DRAW

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ECT 202: Analog Circuits Module III

Then input voltage Vi = Vgs

1
Output voltage 𝑉0 = −𝑔𝑚1 𝑉𝑔𝑠 (𝑟01 || 𝑔 ||𝑟02 )
𝑚2

1
gain becomes𝐴𝑣 = −𝑔𝑚1 (𝑟01 || 𝑔 ||𝑟02 )
𝑚2

1
Output resistance 𝑅𝑜 = (𝑟01 || 𝑔 ||𝑟02 )
𝑚2

But when we use diode load in BJT the gain becomes almost unity and hence its not commonly used
in BJT.

CS Stage With Diode Connected PMOS Device

M1 serve as diode connected load.

Equivalent diagram becomes

DRAW

Then input voltage Vi = Vgs

1
Output voltage 𝑉0 = −𝑔𝑚2 𝑉𝑔𝑠 (𝑟01 || 𝑔 ||𝑟02 )
𝑚1

1
gain becomes𝐴𝑣 = −𝑔𝑚2 (𝑟01 || 𝑔 ||𝑟02 )
𝑚1

1
Output resistance 𝑅𝑜 = (𝑟01 || 𝑔 ||𝑟02 )
𝑚1

CASCADED AMPLIFIERS

Cascade means objects are connected in series or sequence. Cascade Amplifiers means amplifiers are
connected in series. Cascading amplifiers improve parameters like voltage gain, current gain, input
resistance, output resistance etc.

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ECT 202: Analog Circuits Module III

Effect of cascading on Gain

Consider n- stage cascading amplifier with individual gain as shown in block diagram.

𝑉
Then for the first stage, 𝑉1 = 𝐴1 < 𝜃1
𝑖

𝑉
For second stage , 𝑉2 = 𝐴2 < 𝜃2
1

𝑉
For the last stage , 𝑉 𝑛 = 𝐴𝑛 < 𝜃𝑛
𝑛−1

𝑉𝑛 𝑉 𝑉𝑛−1 𝑉 𝑉
Therefore , the over all gain , 𝐴𝑉 = =𝑉𝑛 … . . 𝑉2 𝑉1
𝑉𝑖 𝑛−1 𝑉𝑛−2 1 𝑖

= 𝐴𝑛 < 𝜃𝑛 ∗ 𝐴𝑛−1 < 𝜃𝑛−1 … … … 𝐴2 < 𝜃2 ∗ 𝐴1 < 𝜃1

= 𝐴𝑛 𝐴𝑛−1 … 𝐴2 𝐴1 < 𝜃𝑛 + 𝜃𝑛−1 … … … + 𝜃2 + 𝜃1

Thus for a cascaded amplifier, the magnitude of overall gain is the product of magnitude o gain of
individual stages and phase angle of over all gain is the sum of phase angles of individual stages.

Effect of cascading on Bandwidth

Assume n-identical stages are cascaded with fL as lower cut off frequency and fH as upper cut-off
frequency. We know that gain decreases in low frequency and high frequency region and the gain
almost remains same during medium frequency region.

𝐴𝑀
The gain at low frequency is given by 𝐴𝐿 (𝑓) = 𝑓
(1−𝑗 𝐿 )
𝑓

𝑛
𝐴𝑀
If n-such stages are cascaded then the over all gain is 𝐴𝐿𝑛 (𝑓) = [ 𝑓 ]
(1−𝑗 𝐿 )
𝑓

𝐴𝑀 𝑛 𝐴𝑀 𝑛
Magnitude of gain is |𝐴𝐿𝑛 (𝑓)| = 𝑛 =
2 𝑛/2
𝑓
𝑓 2 [1+( 𝐿) ]
(√1+( 𝑓𝐿 ) ) 𝑓

𝐴𝑀 𝑛
Let the overall lower cutoff frequency be fLO. At this frequency over all gain becomes
√2

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ECT 202: Analog Circuits Module III

𝐴𝑀 𝑛 𝐴𝑀 𝑛
i.e 2 𝑛/2
=
𝑓 √2
[1+( 𝐿 ) ]
𝑓𝐿𝑂

𝑛
2 2
𝑓𝐿 1⁄
then [1 + (𝑓 ) ] = √2 = 2 2
𝐿𝑂

𝑛 2/𝑛
2 2
𝑓𝐿 1⁄ 2/𝑛
lets re-arrange as {[1 + (𝑓 ) ] } = (2 2)
𝐿𝑂

2
𝑓 1⁄
[1 + (𝑓 𝐿 ) ] = 2 𝑛
𝐿𝑂

2
𝑓𝐿 1⁄
( ) =2 𝑛 –1
𝑓𝐿𝑂

𝑓𝐿 1
= √2 ⁄𝑛 – 1
𝑓𝐿𝑂

𝑓𝐿
Then 𝑓𝐿𝑂 =
√21⁄𝑛 – 1

𝟏⁄
Lower cut-off frequency is increased by a factor √𝟐 𝒏 –𝟏

𝐴𝑀
Similarly for upper cut off frequency gain is given by 𝐴𝐻 (𝑓) = 𝑓
(1+𝑗 )
𝑓𝐻

𝑛
𝐴𝑀
For n such stages: 𝐴𝐻𝑛 (𝑓) = [ 𝑓
]
(1+𝑗 )
𝑓𝐻

𝐴𝑀 𝑛 𝐴𝑀 𝑛
Then |𝐴𝐻𝑛 (𝑓)| = 𝑛 =
2 𝑛/2
2 𝑓
𝑓
(√1+( ) ) [1+( ) ]
𝑓𝐻
𝑓𝐻

𝐴𝑀 𝑛
Let the overall upper cutoff frequency be fHO. At this frequency, over all gain becomes
√2

𝑛/2
𝑓 2 1
[1 + (𝑓 ) ] = 2 ⁄2
𝐻

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ECT 202: Analog Circuits Module III

𝑛 2/𝑛
2 2
𝑓 1⁄ 2/𝑛
{[1 + ( 𝑓𝐻𝑂) ] } = (2 2)
𝐻

2
𝑓 1⁄
[1 + ( 𝑓𝐻𝑂) ] = 2 𝑛
𝐻

𝑓𝐻𝑂 1
= √2 ⁄𝑛 – 1
𝑓𝐻

the over all upper cut off frequency is given by

1
𝑓𝐻𝑂 = 𝑓𝐻 √2 ⁄𝑛 – 1
𝟏⁄
Upper cut-off frequency is decreased by a factor √𝟐 𝒏 –𝟏

Resultant Bandwidth = 𝐵𝑊𝑛 = 𝑓𝐻𝑂 − 𝑓𝐿𝑂

But 𝑓𝐿𝑂 is not going to affect over all bandwidth much, since its value is low. So the over bandwidth
depends mainly on 𝑓𝐻𝑂 . Hence we can say that the overall bandwidth is shrinked by a factor
√𝟐𝟏⁄𝒏 – 𝟏

SMALL SIGNAL ANALYSIS OF TWO STAGE MOS CASCADED AMPLIFIERS

Two CS amplifier stage are connected in series, where output of first stage is fed as input to second
stage.

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ECT 202: Analog Circuits Module III

To draw AC equivalent diagram, DC power supply is short circuited. The coupling capacitors and
bypass capacitors are also short circuited. Let R1||R2 = RG then circuit becomes

Then the small signal model becomes

Input Resistance: Looking from input side 𝑅𝑖 = 𝑅𝐺

Voltage Gain:

Without considering source resistance

𝑉𝑂
𝑜𝑣𝑒𝑟 𝑎𝑙𝑙 𝑔𝑎𝑖𝑛 𝐴𝑉 =
𝑉𝑔𝑠1

𝑉
Gain for second stage 𝐴𝑉2 = 𝑉 𝑂
𝑔𝑠2

Output voltage 𝑉𝑂 = −𝑔𝑚 𝑉𝑔𝑠2 (𝑟𝑑 ||𝑅𝐷2 ||𝑅𝐿 )

𝑉
Then gain 𝐴𝑉2 = 𝑉 𝑂 = −𝑔𝑚 (𝑟𝑑 ||𝑅𝐷2 ||𝑅𝐿 )
𝑔𝑠2

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ECT 202: Analog Circuits Module III

𝑉𝑔𝑠2
Gain for first stage 𝐴𝑉1 = 𝑉
𝑔𝑠1

Where 𝑉𝑔𝑠2 = −𝑔𝑚 𝑉𝑔𝑠1 (𝑟𝑑 ||𝑅𝐷1 ||𝑅𝐺 )

𝑉𝑔𝑠2
Then 𝐴𝑉1 = 𝑉 = −𝑔𝑚 (𝑟𝑑 ||𝑅𝐷1 ||𝑅𝐺 )
𝑔𝑠1

Then over all gain can be written as 𝐴𝑉 = 𝐴𝑉1 ∗ 𝐴𝑉2

𝑖 𝑅
Considering Source Resistance, Gain 𝐴𝑉𝑆 = 𝐴𝑉 𝑅 +𝑅 ′
𝑖 𝑆

Output Resistance

Looking from Output side 𝑅𝑂 = 𝑟𝑑 ||𝑅𝐷2

Lower cut-off frequency

𝑓𝐿 𝑓𝐿
𝑓𝐿𝑂 = 1
=
√2 ⁄𝑛 –1 √21⁄2 – 1

Upper cut-off frequency

1
𝑓𝐻𝑂 = 𝑓𝐻 √2 ⁄2 – 1

CASCODE AMPLIFIER

Here we use 2 MOSFET transistor. The bottom transistor M1 acts as

amplifying transistor and is connected in CS configuration. The upper
transistor M2 is known as cascode transistor where a fixed DC is
applied to Gate, but in AC equivalent it will be grounded so it is in
common gate configuration.

The over all output is measured at drain of common gate

configuration.

Advantages : High output resistance, high intrinsic gain, large

bandwidth

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ECT 202: Analog Circuits Module III

Need for Cascode Amplifier

Intrinsic gain (typically -20 to 50) of CS amplifier is 𝑔𝑚 𝑟𝑜 where 𝑟𝑜 is the output resistance of
MOSFET which can be attained by using ideal current source. But when we use actual current source
this gain reduces. By increasing output resistance we can increase gain. In cascode amplifier the output
resistance, which increases gain.

The AC equivalent can be drawn like

Then the small signal

model becomes:

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ECT 202: Analog Circuits Module III

Output resistance

Connect voltage source at output side and short circuit input voltage.

Here 𝑉𝑔𝑠1 = 0, 𝑖𝑑1 = 0 hence it acts as open circuit

Then circuit becomes :

𝑉𝑥
Output resistance 𝑅𝑂 = 𝐼𝑥

𝐼𝑥 = 𝑖 + 𝑖𝑑2 or 𝑖 = 𝐼𝑥 − 𝑖𝑑2 = 𝐼𝑥 − 𝑔𝑚2 𝑉𝑔𝑠2

𝑉𝑥 = 𝑖𝑟𝑂2 + 𝐼𝑥 𝑟𝑂1 = (𝐼𝑥 − 𝑔𝑚2 𝑉𝑔𝑠2 )𝑟𝑂2 + 𝐼𝑥 𝑟𝑂1 = 𝐼𝑥 𝑟𝑂2 − 𝑔𝑚2 𝑉𝑔𝑠2 𝑟𝑂2 + 𝐼𝑥 𝑟𝑂1

𝑉𝑔𝑠2 = −𝑉𝑑𝑠1 = 𝐼𝑥 𝑟𝑂1

Then
𝑉𝑥 = 𝐼𝑥 𝑟𝑂2 + 𝑔𝑚2 𝐼𝑥 𝑟𝑂1 𝑟𝑂2 + 𝐼𝑥 𝑟𝑂1
𝑉𝑥
Output resistance 𝑅𝑂 = = 𝑟𝑂1 + 𝑟𝑂2 + 𝑔𝑚2 𝑟𝑂1 𝑟𝑂2
𝐼𝑥

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ECT 202: Analog Circuits Module III

𝑔𝑚2 𝑟𝑂1 𝑟𝑂2 ≫ 𝑟𝑂1 + 𝑟𝑂2

Then Output resistance 𝑅𝑂 = 𝑔𝑚2 𝑟𝑂1 𝑟𝑂2

Voltage Gain:

Intrinsic gain = −𝐺𝑚 𝑅𝑂

𝑑𝐼𝑜𝑢𝑡 𝑑𝐼𝐷
𝐺𝑚 = = = 𝑔𝑚1 since we need to consider 𝑔𝑚 of transistor where input is applied.
𝑑𝑉𝑖 𝑑𝑉𝑔𝑠

Then gain 𝐴𝑉 = −𝑔𝑚1 𝑔𝑚2 𝑟𝑂1 𝑟𝑂2

If 𝑔𝑚1 = 𝑔𝑚2 , 𝑟𝑂1 = 𝑟𝑂2 then 𝐴𝑉 = −(𝑔𝑚 𝑟𝑂 )2

Significant improvement in gain for cascode amplifier.

Cascode amplifier with resistive load

Gain = −𝐺𝑚 (𝑅𝑂 ||𝑅𝐷 )

𝑅𝑂 ≫ 𝑅𝐷 hence Gain = −𝑔𝑚1 𝑅𝐷

This can be improved by using active load

Cascode amplifier with ideal current source load

𝑅𝐷 is replaced with ideal current source which can be treated as open circuit in AC analysis.

Then gain = intrinsic gain = −𝐺𝑚 𝑅𝑂

Or 𝐴𝑉 = −𝑔𝑚1 𝑔𝑚2 𝑟𝑂1 𝑟𝑂2

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ECT 202: Analog Circuits Module III

Cascode amplifier with actual current source load

Then the gain 𝐴𝑉 = −𝐺𝑚 (𝑅𝑂 ||𝑟𝑂 )

= −𝑔𝑚1 (𝑔𝑚2 𝑟𝑂1 𝑟𝑂2 ||𝑟𝑂 )

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ECT 202: Analog Circuits Module III

Dept of ECE, MBITS Page | 34

ECT 202: Analog Circuits Module III

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