UNIT-3

MOSFET CONSTRUCTION, OPERATION,

CHARACTERISTICS, AC EQUIVALENT CIRCUIT,
MOSFET AS AN AMPLIFIER, CMOS INVERTER,
NAND GATE AND NOR GATE, BASIC PRINCIPLES
AND ADVANTAGES OF NEGATIVE FEEDBACK
INTRODUCTION:
The field effect transistor (FET) is a three terminal device
used for a variety of applications similar to BJT. There are
certain similarities as well as a few differences between the
two types of transistors i.e, BJT and FET. The primary
difference being BJT is a current controlled device whereas
FET is a voltage controlled device. Just as there are npn and
pnp bipolar transistors there are n-channel and p-channel field
effect transistors. However BJT is bipolar device where both
charge carriers electrons and holes contribute to conduction
whereas FET is a unipolar device where conduction is due to
either electrons or holes. FET's one of the most important
characteristic is it has high input impedance. Also FETs are
more temperature stable than BJTs and FETS are usually
smaller than BJTs making them particularly useful in
integrated circuits (IC) chips.
Differences between BJT and MOSFET:
BJT MOSFET
Current controlled device Voltage controlled device
Bipolar Unipolar
Less input impedance High input impedance
compared to MOSFET
Takes more area on an Less area on an Integrated
Integrated circuit circuit
More fabrication cost Less fabrication cost
No terminals are Source and Drain terminals
interchangeable are interchangeable.
Gain is high Gain is comparatively less
No terminals isolated Gate terminal is isolated by
SiO2 layer

There are three types of FETs: Junction Field Effect

Transistor (JFET), Metal-oxide Semiconductor Field Effect
Transistor (MOSFET), and Metal Semiconductor Field Effect
Transistor (MESFET).
Symbols of MOSFET:
CONSTRUCTION OF MOSFET:
MOSFET has become one of the most important devices
used in the design and construction of integrated circuits. Its
thermal stability and other general characteristics make it
extremely popular in integrated circuit design. MOSFETs are
further classified into depletion type and enhancement type
which define the basic mode of operation. We study only
enhancement type in our syllabus.
Enhancement type MOSFET construction: The basic
construction of the n-channel enhancement MOSFET is
shown in the Figure 1. It has three terminals namely source,
gate and drain. A slab of p-type material is formed from a
silicon base and is referred to as substrate. This substrate may
be internally connected to the source terminal or can be used
as a fourth terminal to externally control its potential level.
Over the substrate two n type regions are formed as shown in
Figure1. These regions form source and drain terminals
which are connected through metallic contacts. Over this
substrate a very thin layer of silicon dioxide is formed and a
metallic contact is formed which becomes the gate terminal.
The silicon dioxide (insulator/dielectric) layer is present to
isolate the gate metallic platform from the region between the
source and the drain. The built in potential between source
and gate is referred to as threshold voltage(Vth).

Figure 1: n- channel enhancement type MOSFET(Cross

sectional view)
BASIC OPERATION AND CHARACTERISTICS:

Figure 2: Bias conditions of n- channel enhancement type

MOSFET
Operations of N-MOSFET are as follows:
Case 1: VGS < Vth and VDS >0: With VDS some positive
voltage and VGS at 0V, There are two reverse biased pn
junctions between n doped regions and p substrate to oppose
any significant current flow between drain and source. Hence
current in the device is effectively nil. Hence the device is in
cut-off condition.

Case 2: VGS > Vth and VDS < VGS - Vth: With VDS and VGS
set at some positive voltage, the positive potential at the gate
will pressure the holes in the p-substrate (majority carriers)
along the edge of sio2 layer to leave the area and enter into
deeper regions of the p-substrate. However the electrons in
the p substrate (minority carriers) will be attracted to the
positive gate and accumulate in the region near the surface of
sio2 layer. The sio2 layer's insulating properties will prevent
these electrons from getting absorbed at the gate terminal. As
VGS increases in magnitude, the concentration of electrons
near the sio2 surface increases until eventually the induced n
type region can support a measurable amount of current flow
between source and drain. This n type region between source
and drain is called channel. The level of VGS that results in
formation of the channel and hence significant increase in
drain current (ID) is called threshold voltage (Vth).Figure 2
shows the formation of the channel between drain and source.
Under this condition, the device will operate in linear or
ohmic or triode region. Eqn.2 represents the N-MOSFET
current equation in ohmic region, where K is a constant
representing process parameter.

Where K is the process parameter in A/V2

Case 3: VGS>Vth and VDS= VGS-Vth: If VGS is held constant
at some voltage greater than Vth and increase the level of VDS
the drain current will eventually reach a saturation level. The
levelling off of ID is due to pinching off process as shown in
the Figure 3 at the drain end of the induced channel since
drain is more reverse biased than the source.
 Figure 3: Pinch off proces

Also if VGS is fixed and VDS is increased, according to eqn 2,

the gate will become less and less positive with respect to
drain and hence there is reduction in channel width.
Eventually the channel will be reduced to the point of pinch-
off and a saturation region is established. The saturation level
of VDS is related to the level of applied VGS by,
VDS sat >= VGS-Vth

After pinch-off, further increase in VDS does not cause any

increase in ID attaining saturation. The eqn 3 represents the
N-MOSFET current equation in saturation region.

Where K is the process parameter in A/V2

TRANSFER CHARACTERISTICS (ID Vs VGS for a fixed
VDS):
OUTPUT CHARACTERISTICS ( ID Vs VDS for a fixed
VGS):

Figure 4: Drain characteristics

As shown in the Figure 4, there are three regions in the drain
characteristics of MOSFET namely ohmic /triode region
where VGS> Vth and ID is increasing, saturation region where
ID gets saturated by increasing levels of VDS and cut-off
region where ID is zero as VGS<Vth.

MOSFET AS AN AMPLIFIER:
The Figure 6 shows N-MOSFET in voltage divider
configuration used for amplification along with the DC-load
line on its input characteristics.
Note: Circuit analysis is similar to BJT.
 Figure 6: N-MOSFET as an amplifier

Figure 7: Small signal (AC) equivalent model of CS-

amplifier
Input Impedance Zi= R1||R2

Output Impedance Z0= ro||RD

Transconductance gm K (VGS-Vth ) or
2ID /(VGS-Vth) or
√2ID. 𝐾

rds for small value of VDS rds= 1/ K (VGS-Vth )

Gain (without load Av= -gm*RD

resistance)
Gain (with load resistance) Av= -gm*(RD||RL)
CMOS inverter: A very effective logic circuit with high
input impedance, fast switching speeds, and lower operating
power levels can be obtained by constructing p channel and n
channel MOSFETS on a same substrate. This configuration is
called complementary MOSFET arrangement. A
complementary MOS (CMOS) inverter is implemented as the
series connection of a p-device and an n-device, as shown in
Figure 8. Note that the source and the substrate of the p -
device is tied to the VDD rail, while the source and the
substrate(VSS or GND) of the n-device are connected to the
ground bus and drain terminals of both devices are connected
to the output Vo.

Figure 8:CMOS Inverter

An inverter is a circuit that inverts the applied signal. That is,
if the logic levels of operation are 0V and 5V, an input level
of 5V will result in output level of 0V and vice versa. For
logic levels defined above, application of 5V at the input VIN,
VGS of Qn=5V and Qn is on, resulting in low resistance
between drain and source. Since VIN and VSS are at 5V,
VGS of Qp=0V, and hence Qp is off. The resulting resistance
level between drain and source is quite high for Qp. Hence
Vo becomes 0V establishing inversion process. For an applied
voltage VIN of 0V, VGSN=0V and Qn will be off and
VGSP=-5V, turning on the p channel MOSFET. The result is
that Qp will present a small resistance , Qn a high resistance
level, and Vo= 5V.

THE CMOS NAND GATE:

The schematic diagram of a 2-input CMOS NAND gate is
shown in Figure.9. It can be seen that in this structure, the n-
type driving transistors are connected in series while the p-
type load transistors are connected in parallel. Transistors are
a driven in n-type cum p-type pairs with one transistor ON
while the other is OFF. A table of the conducting states of the
transistors for all logic combinations of the inputs is given
below.

Figure 9 CMOS NAND gate

THE CMOS NOR GATE:
The schematic diagram of a 2-input CMOS NOR gate is
shown in Figure.10. It can be seen that similar to NAND gate
structure, the n-type driving transistors are connected in
parallel while the p-type load transistors are connected in
Series. Transistors are a driven in n-type cum p-type pairs
with one transistor ON while the other is OFF. A table of the
conducting states of the transistors for all logic combinations
of the inputs is given below.

Figure 10 CMOS NOR gate

A B T1 T2 T3 T4 OUT
LO LO OFF ON OFF ON HI
LO HI OFF ON ON OFF LO
HI LO ON OFF OFF ON LO
HI HI ON OFF ON OFF LO

Negative Feedback
The block diagram of a feedback amplifier is shown in fig2.1.

Fig2.1: Simple block diagram of feedback amplifier.

Gain with feedback:
Gain stability with feedback:

Advantages of negative feedback amplifiers:

1. Input impedance increases by a factor of 1+Aβ
2. Output impedance decreases by a factor of 1+Aβ
3. Bandwidth increases by a factor of 1+Aβ
4. Distortion decreases by a factor of 1+Aβ
5. Noise decreases by a factor of 1+Aβ
6. Stability of the gain improves by a factor of 1+Aβ