Andy Howard 2018.09.

20
Applications Engineer / Keysight Technologies
High speed power conversion can help drive new levels of power densities. However, these
designs are plagued with physical design issues. These are not easily understood and not
easily troubleshot in the lab due to measurement limitations. This results in multiple design
spins. Traditional design methodologies are no longer enough.

Ground bounce

Modern EDA toolsets now have the capability to analyze and

provide valuable insights into layout parasitic mechanisms.
Controlling Parasitic Effects 2
 T R AD I T I O N AL D E S I G N M E T H O D S AR E N O T E N O U G H

GaN and SiC devices offer high efficiencies due to their ability to reduce switching loss.

The high speed switching capability comes at a cost. Designs are often plagued with physical
design issues which dominate performance, produce failures, and are not easily understood.

Today, high frequency layout techniques and modern EDA toolsets allow the user to achieve
predictive performance and first pass success.
Controlling Parasitic Effects 3
P H Y S I C A L PA R A S I T I C E F F E C T S – C A U S E S , I M PA C T, R E M E D I E S
TH E M Y TH I C AL C I R C U I T GR OU N D
T R O U B L E S H O O T I N G PA R A S I T I C E F F E C T S

Controlling Parasitic Effects 4

C AU S E S , I M PAC T, R E M E D I E S

Controlling Parasitic Effects 5

W H AT I S I T ?

Definition: The characteristic of AC current such that the

current density within a conductor is largest near the
surface of a conductor, and decreases with greater
conductor depth

Cause: Induced counter

EMF which produces eddy
currents (Ie) that oppose
current flow

Magnetic field (H)

Controlling Parasitic Effects 6

C H AR AC T E R I S T I C S

Current Density Skin Depth Calculation

Current density J Skin depth is highly dependent
decreases exponentially on the angular frequency Skin Depth vs Frequency
by the ratio of physical Frequency microns mils
depth/skin depth from the
10 KHz 654 25.6
surface current density Js
100 KHz 207 8.15
1 MHz 65 2.56
10 MHz 21 0.82
100 MHz 7 0.26

Controlling Parasitic Effects 7

I M PAC T: I N C R E AS E D C O N D U C T I O N L O S S

In many physical structures, skin resistance is a relevant parasitic, and

is dominant at higher switching or harmonic frequencies

Skin Resistance vs Frequency PCB Via Hole Skin Resistance

1
Frequency mohms 0.9

Skin Resistance, Ohms

0.8
1 MHz 5
0.7
10 MHz 12 0.6 66 mil
0.5 height
100 MHz 40
0.4
1000 MHz 224 0.3
0.2
0.1
ADS computation
0
12.7 mm (500 mil) x 1.25 mm (50 mil) trace 0 0.5 1 1.5 2 2.5 3
Frequency, GHz

Vias can be a significant contributor to ground bounce

Controlling Parasitic Effects 8
O B S E R V AT I O N S

• Hand calculations for trace resistance are relevant only for DC

• Thickening a trace to reduce conduction loss may not help much
• At frequencies where the thickness of the plated via metalization is
greater than the skin depth, solid vias do not help much
• An electrical model for a donut via approaches that of a solid via

=
• Skin effect resistance can help dampen circuit behavior.

Controlling Parasitic Effects 9

W H AT I S I T ?

Definition: With multiple conductors in proximity carrying AC current (I), magnetic

fields (H) across the conductors produce eddy currents (Ie). This causes current
crowding in the adjacent conductor furthest away from a given conductor

Cause: Induced
counter EMF which
produces eddy
currents (Ie) that
oppose current flow

Magnetic field (H)

Controlling Parasitic Effects 10

REMEDIES

Traces
Increase trace width and decrease
the length). Increasing thickness
may not help reduce skin effects.

Vias
A group of smaller vias offers more
surface area and less skin
resistance than one larger via

Wires
Litz wire provides more surface
area, insulation and variable radial
position reduce proximity effect

Controlling Parasitic Effects 11

W H AT I S I T ?

Definition: The generation of a voltage spike from the

Right before
collapse of an magnetic field in an inductor. It is governed by switch opens
the equation v(t) = L (di/dt), the inductance multiplied by the
change in current versus time.
Current I(ts-) = 5 amps
Mechanism:
The magnetic field in inductors opposes any instantaneous
change in current. Current tries to remain the same at the
instant of switching.

Right after
switch
opens
I
Inductor tries to keep I(ts+) = 5 amps
What happens?
Controlling Parasitic Effects 12
C A L C U L AT I N G T H E P E A K V O L T A G E

The magnitude of the spike voltage is proportional to the load presented to

the inductor when the load is instantaneously changed (ie switch activated)

Inductor
dis-charging

Switch
Inductor “on”
Inductor signal
charging dis-charged

Max surge voltage = I (ts-) x load (ts+)

= 5 amps x (100+20 ohms)
= 600 V
Controlling Parasitic Effects 13
R E S I S T I V E L O AD I N G E F F E C T S

• Unloaded surge voltage can be extremely high

• Voltages can easily exceed device parameters
• Loading an inductive circuit helps prevent
excessive voltage when current is switched

Is = 5A
Rswopen = 120 ohms Is = 5A Is = 5A
Tr = 1 ps Rswopen = 10k ohms Rswopen = 1M ohms
Tr = 1 ps Tr = 1 ps

Controlling Parasitic Effects 14

C APAC I T I V E L O AD I N G E F F E C T S

Rswopen = 100 ohms Rswopen = 100 ohms Rswopen = 100 ohms

Cload = 1 pF Cload = 100 pF Cload = 1000 pF

Capacitive loading can reduce surge voltage, but

stored energy is conserved
Controlling Parasitic Effects 15
S U R G E V O L T A G E G E N E R AT I O N I N L AY O U T T R A C E S

ΔV waveform
ΔV
L
R C
C is often small
and not dominant

L： inductance
i i R： resistance

di Level is proportional
V  Ri  L
dt to inductance

Change in current
versus time Controlling Parasitic Effects 16
M O R E AT T E N T I O N T O L AY O U T I N T H E S E A R E A S

Controlling Parasitic Effects 17

L O W E R I N G I M P E D A N C E T H R U L AY O U T T E C H N I Q U E S

• A simple trace is modeled as a distributed RLC network (a transmission line)

• Resistance, trace inductance, and capacitance varies with geometry
➢ The capacitance is often neglected but it cancels the inductance!

Trace Characteristics vs Trace Width Matched impedance: Coax Example

(mil/mm)
25

Inductive region
20 20.2

15 Shorter, wider traces are better! Resistive line

10 10.3
50 ohms
9.08

5 5.38 5.74
4.55 3.97 3.94
2.27
3.35
2.78 2.44
2.48 Capacitive region
1.94 1.78
1.38 1.2
0 0.76
5 10 20 50 100 200
0.127 0.254 0.508 1.27 2.54 5.08
R, mohm L, nH C, pF x 10
61 cm (24 in) long 50 ohm
Controlling Parasitic Effects matched coax example 18
AN E X AM P L E U S I N G S - PAR AM E T E R S

Reducing impedance can reduce parasitic inductance and reduce high speed reflections

Microstrip equivalent
Non-optimized trace

Applying RF/high speed design techniques

Red: non-optimized trace Improved trace route Grounded CPW

Blue: improved trace route

Characteristic impedance 1 +0j ohms

* 0.5x5mm trace on 1.67 mm FR4 PCB
Added ground plane to
increase capacitance

Controlling Parasitic Effects Low impedance grounded CPW structure 19

R C S N U B B E R S – U S E D AS A L AS T R E S O R T

Definition: A circuit which reduces spike voltage and parasitic

oscillations. Parasitic oscillations occur when the surge voltage impulse
excites an LC circuit.

Snubbing circuits are usually placed across high dv/dt switching nodes

RC snubbers always decrease efficiency.

• Rsnub dissipates heat directly
• Csnub stores energy= ½ x Csnub x V2 which is dissipated every cycle
Controlling Parasitic Effects 20
R C S N U B B E R D E S I G N : C O M P U T AT I O N A L M E T H O D S

There are several methods to design a snubber circuit.

1. Hand computational methods: Determining Tring requires a
knowledge of parasitic L & C which is likely not known.
Tring = 2 x pi x SQRT (Lparasitic x Cparasitic) Both L & C are not easily
known.

Lparasitic is unknown.
Cparasitic ~ Device output capacitance ~ Coss …but Coss can vary 100:1
or more!
2. Graphical methods: require a calculation of current factor, initial
energy, damping factor, etc. and require complicated graphs.
Parasitic L & C are not likely known.

Note: Rsnub should be sized to dissipate energy stored in the capacitor

Pdiss = ½ x Csnub x Vsupply2 x Fsw Controlling Parasitic Effects 21
RING FREQUENCY DESIGN MET HODOLOGY

Frequency ringing method: Choose Rsnub, determine frequency

of ringing, back solve for Csnub.

Csnub = 3 x Tring/Rsnub

Tring can be found by simulation. Use results determined from EM Co-simulation!

Schematic only EM Co-simulation

A more accurate result

Tring
Controlling Parasitic Effects 22
 A P P LY I N G T H E R I N G F R E Q U E N C Y D E S I G N M E T H O D

(1) (2)
Schematic only EM Co-sim w/o snubber

(3)

EM Co-sim w/snubber

Controlling Parasitic Effects 23

T R A C E L AY O U T , S N U B B I N G

Trace layout:
Lower L di/dt by widening
traces, shrinking route length,
increasing capacitance,
careful via placement

Loading/snubbing:
Resistive/capacitive loads and
snubbing circuits can be used to
control surge voltage, but sacrifices
efficiency

Controlling Parasitic Effects 24

E V E R Y T H I N G I S R E L AT I V E

Controlling Parasitic Effects 25

NOT SO SIMPLE!

?
?
?

?
?

• In simplistic terms, a ground symbol on a schematic can define ground.

• In reality grounds on a circuit board float
• For high speed physical design, every ground point is different!
• Defining a ground reference is Controlling
therefore Parasiticarbitrary
Effects 26
G AI N I N G I N S I G H T S I N T O T H E D E S I G N

• When the grounds of a logic gate contain noise, the noise immunity of the gate decreases.
• The logic gate sees the signal appearing at its input pin with respect to its local ground.

5V
5V
High
3.5V
0V Noise margin = 1.5V – 1V

Low 1.5V
0V
1V

Controlling Parasitic Effects 27

V O LT AG E VAR I AN C E AC R O S S A G R O U N D P L AN E

VS2 VS3 VS4

0.2 volts/ 0.3 volts/ 0.5 volts/
rectgnd 8 volts 55 volts 80 volts
capgnd
0.5 volts/
DC voltage (white) 150 volts
AC voltage (red)

Each point on a power plane or trace has:

• IR drop (DC component)
• di/dt (AC component)
• Different amplitude
• Not necessarily coherent

Each point is different!

28
Controlling Parasitic Effects 28
E V E R Y T H I N G I S R E L AT I V E !

• It is important to understand the relative voltages around a component.

• Signals going into or out of a device are referenced to the local ground
• Noise levels are different across a ground plane and not necessarily coherent

Gnd

These signals
Gate
are relative to
driver IC local gate
driver ground
MOSFET
Gate

PWM signal
PWMin relative to local
PWM ground
Schematic only EM Co-simulation
Controlling Parasitic Effects 29
E M C O - S I M U L AT I O N H E L P E D W I T H D I A G N O S I S

2) 2) 2)
1) 1) 1)

3)

1) Gate driver grounds

2) Ground plane connecting the power transistors
3) PWM ground

Root cause: Excessive ground path from the PWM to

the gate drivers, grounds are mismatched along path
Controlling Parasitic Effects 30
P H Y S I C A L L AY O U T R E M E D I E S

Trace layout:
Reduce IR drop & di/dt by
widening traces, shrinking
route length. Reduce high
current loops

Ground tying: gnd2

gnd1 gnd2 gnd1 gnd1 gnd2
Adjust routing to balance V1 V2 trace
nodes un- Common tie Ground
ground between critical capbalanced cap
point pour
cap
nodes (V1 & V2)

Low ESL capacitors: V+ V+

Add where large switching Switching Switching

transients are generated and device Bypass device
Low Bypass
cap ESL
between critical components cap
cap

Controlling Parasitic Effects 31

H I G H V O LT AG E , L O W E S R C APAC I T O R S

Consider a 2.2 uF, 600V poly film low ESR capacitor

• 33 mOhm ESR
• 18 nH lead inductance!

Observations:
• Higher voltage capacitors have more lead inductance
• Fast switching glitches: rise times are only a few nS!
• Lead inductance may prevent the capacitor from Spike voltage not suppressed
functioning properly

Controlling Parasitic Effects 32

S TA G G ER ED B Y PAS S C A PA C ITO RS

2.2 uF 470 uF
.56 uF
Vsupply VOut

Gnd
Switching • Lowest ESL • Low ESL
node • • Higher ESL
• Lowest ESR Low ESR
• • Higher ESR
• Lowest value Low value
capacitor • High value
capacitor
capacitor

Low ESL capacitors:

Stagger capacitor types between the switching node and the
output with lowest ESL capacitors nearest the switching node

Controlling Parasitic Effects 33

B I G G E R I S N O T N E C E S S A R I LY B E T T E R

Switching trace, no Apply 2.2 uF, 33

bypass capacitor mOhm capacitor. No
lead inductance

Ground
Apply 2.2 uF, 33 mOhm Apply 0.56 uF, 33
capacitor. 18 nH lead mOhm capacitor. 10 nH
inductance lead inductance

Controlling Parasitic Effects 34

T OOLS, T ECHNIQUES, POST PROCESSING

Controlling Parasitic Effects 35

 U S I N G A D S F O R E M C O - S I M U L AT I O N

Layout and
schematic are
tied together

• EM technologies can be applied to • Simulation can be switched

the layout between a schematic and EM co-
• Method of Moments EM provides sim view
the best balance of speed and • EM is utilized with transient or
accuracy for planar designs harmonic balance circuit simulation
* EM Co-simulation is covered in detail as a separate topic
Controlling Parasitic Effects 36
P R O B E S A R E E A S I LY P L A C E D I N T H E L AY O U T

Insert ports by clicking here

• Probes can be placed at any critical

voltage node (like FET gate, drain,
gate driver inputs, gnd, etc.)
• Probes can also be placed along a
trace plane at different spots to gain
di/dt insights

Controlling Parasitic Effects 37

D AT A D I S P L AY I S A P O W E R F U L T O O L

Multiple measurements
can be conveniently
displayed at once.
This can include: switching
waveforms, ground
bounce, EMI, di/dt trace
drop etc.

Controlling Parasitic Effects 38

C U S T O M M E AS U R E M E N T S

• ADS provides flexibility to

measure just about anything
Measured vs
• Embedded measurements
simulated result
• Individual measurement of
layout probe points
• Custom scripted
measurements
• Measured vs simulated results
Custom scripted
measurements

Controlling Parasitic Effects 39

U S I N G D AT A D I S P L AY M A R K E R S

Line marker (m4)

Marker palette

Peak marker (m3)

• Markers make it easier to measure data

• Markers are inserted to measure points
of interest
• Markers can be used to measure the
period of ringing, rise times, or
differential timing

Controlling Parasitic Effects 40

G R O U N D B O U N C E E X AM P L E S

Ground bounce reduces converter Ground bounce near a voltage reference or

efficiency, produces common mode gate driver can degrade noise performance.
noise, and degrades noise immunity.
This performance is good
This performance is good
Controlling Parasitic Effects 41
d I / d T E X AM P L E – V O LT AG E D R O P AC R O S S A T R AC E

Probes placed along traces can be subtracted from each other to gain insights
• Where high current loops drive L di/dt effects
• Impact on switching efficiency

Controlling Parasitic Effects 42

E M E X C I T AT I O N E X A M P L E

• EM excitation provides current or voltage density to troubleshoot “hot spots”

• Visualization can be manipulated to provide different views
Controlling Parasitic Effects 43
• Parasitic effects degrade performance and can cause failure
• All physical implementations include parasitics and their impact may not be
seen with a schematic-only simulation
• Spiking, noise, ringing, oscillations, false triggering, etc.
• Every ground point on a physical design is different!
• Ground differences reduces noise immunity - a reliability concern
• Modern EDA tools and high speed design techniques can be used to verify,
troubleshoot, and optimize a design

Controlling Parasitic Effects 44