Lecture 15
Physical Design, Part 1
Xuan ‘Silvia’ Zhang
Washington University in St. Louis
http://classes.engineering.wustl.edu/ese461/
ASIC Construction
• System partitioning
– goal: partition a system into a
number of modules
– objectives: minimize the
number of external
connections; keep each
module smaller than max size
• Floorplanning
– goal: calculate the sizes of all
the blocks and assign them
locations
– objectives: keep the highly
connected blocks physically
close to each other
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ASIC Construction
• Placement
– goal: assign the interconnect
areas and the location of all the
logic cells within the flexible
blocks
– objectives: minimize the area and
the interconnect density
• Global routing
– goal: determine the location of all
the interconnect
– objective: minimize total
interconnect area
• Detailed routing
– goal: completely route the chip
– objective: minimize total length
of the interconnect
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Floorplanning
• Mapping between logical and physical design
– interconnect delay dominates gate delay
– center of ASIC backend design operation
– timing-driven floorplanning
• Goals
– arrange the blocks on a chip
– decide the location of the I/O pads
– decide the location and number of the power pads
– decide the location and type of clock distribution
• Objectives
– minimize chip area and delay
– how to measure?
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Floorplanning
• Relative position, orientation
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Floorplanning
• Aspect ratio
• Initial seeding
– hard seed, soft seed
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Measurement of Delay
• Gate delay vs interconnect delay
• Predict interconnect delay
– does not know interconnect capacitance or resistance
– have to infer based on fanout (FO)
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Predicted-Capacitance Tables
• Predict capacitance with FO and logic size
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Worst-Case Interconnect Delay
• Interconnect delay trends
– fixed chip size
– coast-to-coast interconnect
– increased worst-case delay at smaller technology nodes
9
Channel Definition
• Assign the areas between blocks for interconnect
• Channel ordering
– stem first, bar second
– slicing floorplan (T junction)
– slicing tree
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Cyclic Constraints
• No slicing the floorplan without breaking blocks
• Merge
• Selective flattening
• Routing order
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I/O Pad Planning
• Pad-limited and core-limited chip
• Pad slot and pad pitch
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Power Planning
• Power distribution
• Pad slot and pad pitch
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Clock Planning
• Clock spine (fish-bone clock distribution)
• Clock latency and skew
• Clock buffer
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Clock Tree
• Minimum delay when taper ratio is e=2.7
• need to balance the delays through the tree
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Placement
• Place logic cells within the flexible blocks
• Ideal objectives
– guarantee the router can complete the routing step
– minimize all the critical net delays
– make the chip as dense as possible
– minimize power, crosstalk between signals
• Realistic objectives
– minimize total estimated interconnect length
– meet the timing requirement for critical nets
– minimize the interconnect congestion
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Placement Terms
• Over the cell routing (OTC) • Feedthroughs (feedthrus)
• Channel capacity • Jumper (unused vertical
track in a cell)
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Reference
• Cadence Encounter Tutorial posed online
• ASIC ebook, Chapter 16
– http://www10.edacafe.com/book/ASIC/Book/CH16/
CH16.php
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Questions?
Comments?
Discussion?
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LEF and DEF Files (Cadence)
• Library exchange format (LEF)
– Standard Cadence tools
– Describe IC process and a logic cell library
• gate array: cells, logic, size, connectivity
• Design exchange format (DEF)
– Describe all physical aspects of a chip design
– Netlist and physical location
– Exchange information between designs
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